JP2010226355A - Filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a filter circuit which is fast at low current consumption, and can increase an input signal level even when an absolute value of a threshold value voltage of a MOS transistor is low. <P>SOLUTION: The filter circuit includes MOS transistors (Tr)1 and Tr2 for inputting a signal from a gate, a MOS transistor Tr3 which has a drain connected to a source of the MOS transistor 1 and a gate connected to a source of the MOS transistor 2, a MOS transistor Tr4 which has a drain connected to the source of the MOS transistor Tr2 and a gate connected to the source of the MOS transistor Tr1, a current source 5 for supplying a current to the source of the MOS transistor Tr3, a current source 6 for supplying a current to the source of the MOS transistor Tr4, and capacitors 7 and 8 connected to each source of the MOS transistors Tr1 to Tr4. In this filter circuit, there are provided voltage sources 101 and 102 for applying a voltage so that operating points of the MOS transistors Tr3 and Tr4 shift from the side close to a linear area inside a saturated area to the side far therefrom. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

    The present invention relates to a filter circuit, and more particularly to a filter circuit based on a source follower circuit.

  Currently, there are two types of filters that remove noise and interference signals from electrical signals: time continuous filters and time discrete filters. Although the time continuous filter is more suitable for high-speed operation than a time discrete filter such as an SCF (switched capacitor filter), it has a drawback that the linear performance is inferior to that of the SCF. In order to improve the linear performance of a time-continuous filter, there is a technique for configuring a time-continuous filter based on a source follower circuit. Examples of such conventional techniques include Patent Document 1 and Non-Patent Document 1.

US Patent Application Publication No. 2008/157864

Stefano D'Amico, Matteo Conta, Andrea Baschirotto, IEEE Journal of Solid State Circuits, 41, 12, 2713-2719, 2006. Paper title "A 4.1-mW 10-MHz Fourth-Order Source Follower-Based Continuous-Time Filter With 79-dB DR"

However, the filter circuit based on the conventional source follower type transistor has a problem that the maximum input signal level is limited by the threshold voltage of the transistor used. Hereinafter, this problem will be described in detail with reference to FIG.
FIG. 12 is a diagram showing a conventional time-continuous filter circuit based on a source follower circuit. The illustrated filter circuit includes PMOS transistors 201 to 204, current sources 205 and 206, capacitors 207 and 208, differential input terminals 209 and 210, output terminals 211 and 212, and terminals 213 to 216. Yes. Of the terminals 213 to 216, the terminal 215 is a negative power supply terminal connected to the ground, and the terminal 216 is a positive power supply terminal for supplying positive power.

Since the filter shown in FIG. 12 is based on a source follower circuit, it is excellent in linear performance, and can realize a high-speed and low current consumption filter circuit.
The operation of the filter circuit shown in FIG. 12 will be described. In the description, the voltage of the output terminal 211 that is the source terminal of the PMOS transistor 203 is V1, the voltage of the terminal 214 that is the gate terminal is V2, and the voltage of the terminal 213 that is the drain terminal is V3.

In order for the PMOS transistor 203 to operate as a source follower, it is necessary to satisfy Expression (1), which is a saturation region condition.
V3-V1 <V2-V1-Vth (1)
In Formula (1), Vth is a threshold voltage of the PMOS transistor 203, and is a negative numerical value when the PMOS transistor 203 is an enhancement type. When the input signal is 0, that is, when the voltages applied to the differential input terminals 209 and 210 are the same, the voltages V3 and V2 at the terminals 213 and 214 have the same value, and this value is Va.

When a signal having a voltage value Vin is applied to the differential input terminals 209 and 210, the voltage Va at the terminals 213 and 214 shifts opposite to each other around the voltage Va. For this reason, V2 and V3 are respectively represented by Expression (2) and Expression (3).
V2 = Va−b · Vin Formula (2)
V3 = Va + b · Vin Formula (3)

Here, b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Hereinafter, when b = 1 for brevity, Expression (4) is obtained by substituting Expression (2) and Expression (3) into Expression (1) and rearranging.
− (Vth / 2)> Vin (4)
As can be seen from equation (4), in the filter circuit shown in FIG. 12, when the input signal voltage Vin exceeds one half of the absolute value of the threshold voltage, the MOS transistor 203 moves out of the saturation region, and as a filter. It will not work properly. Although the equations (1) to (4) are obtained for the PMOS transistor 203, the equation (4) can also be obtained for the PMOS transistor 204 by calculating similarly.

  In many analog circuits, the signal range is limited when the power supply voltage is low or the threshold value of the transistor is large. However, in the filter circuit shown in FIG. 12, the operation of the filter is limited by the absolute value of the threshold value Vth, as shown in Expression (4), regardless of the power supply voltage. The absolute value of the threshold value is set in consideration of a decrease due to the environmental temperature (at a high temperature) and a variation at the time of manufacture, and is generally set in a range of 0.5 to 0.8 V at present. Accordingly, the maximum input signal level is 0.25 V in order for the filter circuit shown in FIG. 12 to obtain good linear characteristics.

That is, the filter circuit based on the conventional source follower type transistor has a problem that the maximum input signal level is limited to about half of the threshold voltage of the MOS transistors 203 and 204.
The present invention has been made in view of the above points, and has a high speed and low current consumption, and can increase the input signal level even when the absolute value of the threshold voltage of the MOS transistor is low. An object of the present invention is to provide a filter circuit based on a follower circuit.

  In order to solve the above problems, a filter circuit according to claim 1 of the present invention includes a first MOS transistor (for example, PMOS transistor 1 shown in FIG. 1) having a first input signal input to the gate and a second input to the gate. A first transistor pair including a second MOS transistor (for example, PMOS transistor 2 shown in FIG. 1) to which a signal is input, a drain connected to the source of the first MOS transistor, and a gate connected to the source of the second MOS transistor A third MOS transistor (for example, PMOS transistor 3 shown in FIG. 1) that is connected and from which a first output signal is output, a drain connected to the source of the second MOS transistor, and a gate connected to the source of the first MOS transistor A fourth MOS transistor that is connected and outputs a second output signal from the source. A second transistor pair including a register (for example, the PMOS transistor 4 illustrated in FIG. 1), a first current source (for example, the current source 5 illustrated in FIG. 1) for supplying current to the source of the third MOS transistor, A current source pair including a second current source (for example, current source 6 shown in FIG. 1) for supplying a current to the source of the fourth MOS transistor, and each of the sources of the first to fourth MOS transistors. And a capacitor circuit (for example, the capacitors 7 and 8 shown in FIG. 1), the operating point of the third MOS transistor and the fourth MOS transistor being close to a linear region in the saturation region. Voltage applying means for applying a voltage so as to shift in a direction from the side toward the far side (for example, the voltage source shown in FIG. 1) And 01,102), characterized in that it comprises a.

  A filter circuit according to a second aspect of the present invention is the filter circuit according to the first aspect, wherein the voltage applying means is connected between a gate of the third MOS transistor and a drain of the fourth MOS transistor, and the third MOS transistor is connected to the third MOS transistor. A first voltage source (for example, voltage source 101 shown in FIG. 1) for applying a voltage so that the operating point of the 3MOS transistor shifts in a direction from the side closer to the linear region in the saturation region to the side farther from the linear region; Connected between the gate of the transistor and the drain of the third transistor, the operating point of the fourth MOS transistor is shifted from the side closer to the linear region in the saturation region to the side farther from the fourth MOS transistor. And a second voltage source for applying a voltage (for example, the voltage source 102 shown in FIG. 1).

  A filter circuit according to a third aspect of the present invention is the filter circuit according to the first aspect, wherein the voltage applying unit is connected between a source of the first MOS transistor and a drain of the third transistor, and the third MOS transistor includes: A third voltage source (for example, voltage source 301 shown in FIG. 4) for applying a voltage so that the operating point of the third MOS transistor shifts in a direction from the side closer to the linear region in the saturation region toward the far side; Connected between the source of the second MOS transistor and the drain of the fourth transistor, the operating point of the fourth MOS transistor is shifted in the direction from the side closer to the linear region in the saturation region to the side farther from the fourth MOS transistor. And a fourth voltage source for applying a voltage (for example, the voltage source 302 shown in FIG. 4).

  A filter circuit according to a fourth aspect of the present invention is the filter circuit according to any one of the first to third aspects, wherein the voltage application means is configured such that the conductivity type of the first MOS transistor and the second MOS transistor is the third MOS transistor, the second MOS transistor, The third MOS transistor is connected in parallel with the first MOS transistor, the fourth MOS transistor is connected in parallel with the second MOS transistor, and the source of the first MOS transistor and the first MOS transistor are different from the conductivity type of the 4MOS transistor. A third current source (for example, the current source 35 shown in FIG. 6) connected to the drain of the 3MOS transistor, and a fourth current source (for example, FIG. 6) connected to the source of the second MOS transistor and the drain of the fourth MOS transistor. And a current source 36) shown in FIG. To.

A filter circuit according to a fifth aspect of the present invention is the filter circuit according to any one of the first to fourth aspects, wherein the first terminal receives current supplied from a fifth current source (for example, the PMOS transistor 61 shown in FIG. 3). And a voltage source including a resistance element having a second terminal that receives a current from a sixth current source (for example, the NMOS transistor 62 shown in FIG. 3).
The filter circuit according to a sixth aspect of the present invention is the filter circuit according to the fifth aspect, wherein the voltage source adds a voltage value applied by the voltage source and an absolute value of the MOS transistor threshold value of the second transistor pair. Alternatively, it is an adaptive voltage generating circuit that generates a voltage such that a subtracted value becomes a constant voltage value.

  The filter circuit according to a seventh aspect of the present invention is the filter circuit according to the sixth aspect, wherein the adaptive voltage generation circuit is configured to apply a voltage applied by a voltage source when the electric type of the MOS transistor of the second transistor pair is an N type. When a voltage is generated so that a voltage value obtained by adding the value and the MOS transistor threshold value of the second transistor pair becomes a constant value, and the electric type of the MOS transistor of the second transistor pair is P type, A voltage is generated so that a voltage value obtained by subtracting a MOS transistor threshold value of the second transistor pair from a voltage value applied by a voltage source becomes a constant value.

  The filter circuit according to an eighth aspect of the present invention is the filter circuit according to the third aspect, wherein the third voltage source is a second resistance element (for example, the resistance element 71 shown in FIG. 5), the first current source, and the first current source. A third MOS transistor, a seventh current source (for example, the current source 72 shown in FIG. 5) connected in parallel with the second resistance element, and an eighth current connected in parallel with the second resistance element and the first MOS transistor. A current value supplied by the seventh current source and the eighth current source, both of which are supplied by the first current source and a current value supplied by the first current source, for example, a current source 73 shown in FIG. The fourth voltage source is connected in parallel with the third resistance element, the second current source, the fourth MOS transistor, and the third resistance element. A ninth current source and the third resistance element; A tenth current source connected in parallel with the second MOS transistor, and the current values supplied by the ninth current source and the tenth current source are both current values supplied by the second current source. It is equal to the sum of the value and the value of the current flowing through the third resistance element.

  A filter circuit according to a ninth aspect of the present invention is the filter circuit according to the third aspect, wherein the first MOS transistor and the second MOS transistor have different conductivity types from the third MOS transistor and the fourth MOS transistor. A third current source (for example, current source 35 shown in FIG. 7) connected to the source of the second MOS transistor, a fourth current source (for example, current source 36 shown in FIG. 7) connected to the source of the second MOS transistor, And the third voltage source is connected to the first MOS transistor in parallel with the first current source, the third current source, and the third MOS transistor in series with a fourth resistance element (for example, FIG. 8), the first MOS transistor, the first current source and the fourth resistance element, and the third MOS transistor. An eleventh current source (for example, the current source 77 shown in FIG. 8) connected in parallel to any of the above, and a twelfth current source (in parallel with the fourth resistance element and the third current source) For example, the current source 78) shown in FIG. 8 is provided, and the eleventh current source supplies a current having the same current value as the current flowing through the fourth resistance element, and the current value supplied by the twelfth current source. Is equal to the sum of the value of the current supplied by the eleventh current source and the value of the current supplied by the first current source, and the fourth voltage source is in parallel with the second MOS transistor, and A fifth resistance element connected in series with the second current source, the fourth current source, and the fourth MOS transistor; the second MOS transistor; the second current source; the fifth resistance element; and the fourth MOS. Transistor A thirteenth current source connected in parallel with respect to the shift, and a fourteenth current source connected in parallel with the fifth resistor element and the fourth current source. A current having the same current value as the current flowing in the five-resistance element is supplied, and the current value supplied by the fourteenth current source is supplied by the current value supplied by the thirteenth current source and the second current source. It is characterized by being equal to the sum of the current value.

  A filter circuit according to a tenth aspect of the present invention is the filter circuit according to the sixth aspect, wherein the fifth current source is a fifth MOS transistor (for example, the NMOS transistors 81 and 86 shown in FIG. 10), and the sixth current source is a sixth MOS transistor. (For example, the PMOS transistors 82 and 87 shown in FIG. 10), which are input to the non-inverting terminal and the inverting terminal and output the difference as an output signal (for example, the differential amplifier 96 shown in FIG. 10). ), A seventh MOS transistor (for example, NMOS transistor 91 shown in FIG. 10) having a gate to which the output signal of the differential amplifier is input, a gate connected to the gate of the seventh MOS transistor, and the non-inverting terminal; An eighth MOS transistor having a connected drain (for example, the NMOS transistor shown in FIG. 10) 3), a drain connected to the drain of the eighth MOS transistor via a sixth resistance element (for example, the resistance element 95 shown in FIG. 10), and a ninth MOS transistor having a gate connected to the drain (for example, FIG. 10, a drain connected to the drain of the seventh MOS transistor, a gate connected to the drain, and a source connected to the source of the ninth MOS transistor (for example, FIG. 10). The output signal of the differential amplifier is input to the gate of the fifth MOS transistor to control the fifth MOS transistor, and is connected to the gate and drain of the tenth MOS transistor. The connected terminal is the sixth MOS And inputted to the gate of the transistor and controls the first 6MOS transistor.

  The filter circuit according to an eleventh aspect of the present invention is the filter circuit according to the tenth aspect, wherein the eleventh MOS transistor (for example, the NMOS transistor 911 shown in FIG. 11) having a gate terminal connected to the output terminal of the differential amplifier, A twelfth MOS transistor (for example, PMOS transistor 912 shown in FIG. 11) having a drain connected to the drain terminal of the 11MOS transistor and a gate connected to the drain, and a gate having a gate connected to the drain and gate of the twelfth MOS transistor. A sixth MOS transistor (for example, a PMOS transistor 913 shown in FIG. 11) and a fifteenth current source (for example, a current source 914 shown in FIG. 11) connected to the drain of the ninth MOS transistor; The element is the eighth. The drain of the OS transistor, a drain and a gate of the 9MOS transistor, characterized in that it is connected to the drain of the second 13MOS transistor.

According to the first aspect of the present invention, it is possible to apply a voltage in a direction in which the third MOS transistor and the fourth MOS transistor are operated in a saturated state. Therefore, the input voltage range in which the third MOS transistor and the fourth MOS transistor operate as source follower type MOS transistors is expanded by half of the applied voltage. Therefore, it is possible to provide a filter circuit capable of expanding the range of input voltages while using a source follower type MOS transistor as a base.

According to the second aspect of the present invention, the voltage source is connected to the gate or drain of the third MOS transistor or the fourth MOS transistor, and the operating region of the third MOS transistor or the fourth MOS transistor is set to the saturation region by applying a voltage. Can be shifted.
According to the third aspect of the present invention, the voltage source is connected to the drains of the third MOS transistor and the fourth MOS transistor, and the operating region of the third MOS transistor and the fourth MOS transistor is shifted to the saturation region by applying the voltage. Can do.

According to the fourth aspect of the present invention, even when the first transistor pair and the second transistor pair are folded back and connected, the operation regions of the third MOS transistor and the fourth MOS transistor can be shifted to the saturation region.
The inventions of claims 2 to 4 increase the variation of the specific circuit configuration for realizing the filter circuit of claim 1 and increase the degree of freedom in designing the filter circuit.
According to the fifth aspect of the present invention, it is possible to provide a voltage source that shifts the operation region of the third MOS transistor and the fourth MOS transistor to the saturation region with a relatively simple configuration.

According to the sixth aspect of the present invention, the voltage source can be an adaptive voltage generation circuit, and the voltage can be efficiently applied to the filter circuit in accordance with the threshold value of the MOS transistor.
According to the seventh aspect of the present invention, it is possible to efficiently apply a voltage to the filter circuit regardless of whether the MOS transistor of the filter circuit is P-type or N-type.
According to the invention described in claim 8, it is possible to provide a voltage source suitable when the third voltage source and the fourth voltage source are arranged between the source of the first transistor pair and the drain of the second transistor pair. .

According to the ninth aspect of the present invention, the voltage suitable for the filter circuit disposed between the source of the first transistor pair and the drain of the second transistor pair in a state where the first transistor pair and the second transistor pair are folded back to each other. A source can be provided.
According to the tenth aspect of the present invention, it is possible to provide a voltage source for a filter circuit that is optimal for the present invention.
According to the eleventh aspect of the present invention, it is possible to provide a voltage source circuit capable of supplying a voltage with higher accuracy in a filter circuit optimum for the present invention.

It is a circuit diagram for demonstrating the filter circuit of Embodiment 1 of this invention. It is a figure for demonstrating the wording used in embodiment of this invention. It is a figure for demonstrating the voltage source applicable to the voltage source shown in FIG.1 and FIG.6. It is a circuit diagram for demonstrating the filter circuit of Embodiment 2 of this invention. It is a figure for demonstrating the voltage source shown in FIG. It is a figure for demonstrating the filter circuit of Embodiment 3 of this invention. It is a figure for demonstrating the filter circuit of Embodiment 4 of this invention. It is a figure for demonstrating the voltage source shown in FIG. FIG. 10 is a diagram for explaining a filter circuit according to a fifth embodiment. FIG. 3 is a diagram illustrating a specific example of a voltage source of the filter circuit according to the first embodiment. FIG. 6 is a diagram illustrating a specific example of a voltage source of a filter circuit according to a second embodiment. It is the figure which showed the circuit of the conventional time continuous filter based on a source follower circuit.

Hereinafter, filter circuits of Embodiments 1 to 5 according to the present invention will be described with reference to the drawings.
(Embodiment 1)
1 Configuration FIG. 1 is a circuit diagram for explaining a filter circuit according to a first embodiment of the present invention. The configuration of the filter circuit of the first embodiment shown in FIG. 1 is obtained by adding voltage sources 101 and 102 to the conventional filter circuit shown in FIG. The voltage sources 101 and 102 apply voltages to PMOS transistors 3 and 4 to be described later so that the operating points of the transistors shift in a direction from the side closer to the linear region to the side farther from the saturation region.

  Note that the wording of the operating point, saturation region, and linear region of the transistor used in this specification will be described here. FIG. 2 is a diagram showing the relationship (Id-Vds characteristics) with the current Id flowing into the drain of the MOS transistor on the vertical axis and the voltage Vds applied between the drain and source of the MOS transistor on the horizontal axis. Since the Id-Vds characteristic varies depending on the voltage Vgs applied between the gate and the source, a plurality of curves showing the Id-Vds characteristic are drawn by changing the voltage Vgs.

  As is well known, the operating region of the MOS transistor is divided into a linear region (non-saturated region) and a saturated region. As shown in the figure, the linear region is an operation region in which the value of the current Id changes according to the change in the voltage Vds. The saturation region is an operation region where the current Id takes a substantially constant value regardless of the change in the voltage Vds. The operating point refers to a voltage input from the outside to the gate, source, and drain of the MOS transistor, and the point P1 shown in the figure indicates the operating point of the conventional filter circuit. In the conventional filter circuit, the value of the current Id becomes IL at the operating point where Vds is VL.

  The present invention adds voltage sources 101 and 102 to such a conventional filter circuit. Then, by applying a voltage from the voltage sources 101 and 102, the current IH obtained at the operating point P2 when Vds is raised to VH is obtained without changing the voltages Vds and Vgs inputted from the outside to the filter circuit. . In the present invention, such a method of applying a voltage is described as “applying a voltage so that the operating point of the transistor shifts in a direction from the side closer to the linear region in the saturation region to the side farther from the linear region”.

As described above, “applying a voltage so that the operating point of the transistor shifts in a direction from the side closer to the linear region in the saturation region toward the far side” means that by applying a voltage using a voltage source, for example, This means that the correspondence between Vds applied to the MOS transistor from the outside and the current Id is shifted from the point P1 to the point P2.
That is, the filter circuit shown in FIG. 1 includes PMOS transistors 1, 2, 3, 4, capacitors 7, 8, current sources 5, 6, and voltage sources 101, 102. The voltage value applied by the voltage sources 101 and 102 is Vc.

  The power supply terminal 23 is a negative power supply terminal, and the power supply terminal 24 is a positive power supply terminal. Differential signals are input to the differential input terminals 11 and 12 of the filter circuit. Terminals denoted by reference numerals 13 and 14 are output terminals of the filter circuit. Further, reference numerals 15, 16, 17, and 18 shown in the drawing are reference numerals for explaining a relationship with a voltage source of FIG. 3 to be described later, and all indicate nodes.

  As for the PMOS transistor 1, the drain is connected to the power supply terminal 23, the gate is connected to the differential input terminal 11, and the source is connected to the drain of the PMOS transistor 3, the capacitor 7, and the voltage source 101. One terminal of the voltage source 101 is connected to the terminal 18 of the gate of the PMOS transistor 4. As for the PMOS transistor 2, the drain is connected to the negative power supply terminal 23, the gate is connected to the differential input terminal 12, the source is the other terminal of the capacitor 7, one terminal of the voltage source 102, and the PMOS transistor 4. Connected to the drain. The other terminal of the voltage source 102 is connected to the gate terminal 17 of the PMOS transistor 3.

As for the PMOS transistor 3, the source is connected to one terminal of the input terminal 13, the current source 5, and the capacitor 8. As for the PMOS transistor 4, the source is connected to the input terminal 14, the current source 6, and the other terminal of the capacitor 8.
The filter circuit of the first embodiment described above has the same configuration as the source follower type filter circuit described in Non-Patent Document 1 and Patent Document 1 except for the voltage sources 101 and 102.

FIG. 3 is a diagram for explaining a voltage source applicable to the voltage source 101 shown in FIG.
The voltage source 101 includes a PMOS transistor 61, an NMOS transistor 62, and a resistance element 63. The power supply terminal 68 is a positive power supply terminal, and the power supply terminal 69 is a negative power supply terminal. The terminal 66 is a terminal connected to the node 18 shown in FIG. 1, and the terminal 67 is a terminal connected to the node 15 shown in FIG. The current flowing through the PMOS transistor 61 and the NMOS transistor 62 may be fixed or variable.
The PMOS transistor 61 and the NMOS transistor 62 function as a current source that supplies current to the resistance element 63. The value of the current supplied by the PMOS transistor 61 and the NMOS transistor 62 is controlled by the voltage applied by the terminals 64 and 65.

As for the PMOS transistor 61, the gate is connected to the current control terminal 64, the source is connected to the positive power supply terminal 68, and the drain is connected to one terminal 66 of the resistance element 63. The NMOS transistor 62 has a gate connected to the current control terminal 65, a drain connected to the other terminal 67 of the resistance element 63, and a source connected to the negative power supply terminal 69.
Since the configuration of the voltage source 101 is the same as that of the voltage source 102 shown in FIG. 1, the description of the voltage source 101 is replaced with the description of the voltage source 102. However, the terminal 66 of the voltage source 102 is connected to the node 17 shown in FIG. 1 and the terminal 67 is connected to the node 16.

In the voltage source having the above configuration, the MOS transistors 61 and 62 operate as a current source in which the current value of the current flowing between the source and the drain is controlled by the voltage applied to the current control terminals 64 and 65. The current value flowing through the MOS transistors 61 and 62 is Ic. A current having a current value Ic is supplied from the MOS transistor 61 to the resistance element 63 and flows to the power supply terminal 69 through the MOS transistor 62. At this time, assuming that the resistance value of the resistance element 63 is R, a voltage Vc is generated between the terminal 66 and the terminal 67 of the resistance element 63. The voltage value Vc can be obtained from the resistance value R and the current value Ic as shown in Equation (5).
Vc = Ic · R (5)
According to such a voltage source, the voltage value Vc can be adjusted by controlling the current value Ic flowing through the MOS transistors 61 and 62 by the current control terminals 64 and 65.

2 Operation Next, the operation of the PMOS transistor 3 in the filter circuit of the first embodiment shown in FIG. 1 will be described. The source voltage (voltage of the output terminal 13) of the PMOS transistor 3 is Vs1, the gate voltage is Vg1, and the drain voltage is Vd1. At this time, in order for the transistor 3 to operate as a source follower, each voltage needs to satisfy Expression (6), which is a saturation region condition.
Vd1-Vs1 <Vg1-Vs1-Vth Formula (6)
In Expression (6), Vth is a threshold voltage of the PMOS transistor 3, and is a negative numerical value when the PMOS transistor 3 is an enhancement type. When the input signal is 0, that is, when the voltages applied to the differential input terminals 11 and 12 which are differential input terminals are the same, the voltages Vd1 and Vd1 ′ also have the same voltage value, and the voltage value at this time is expressed as Va. To do.
Here, the voltage Vg1 and the voltage Vg1 ′ are Va + Vc obtained by adding the voltage value Vc of the voltage sources 101 and 102 to the voltage value Va.

Further, when a signal having a voltage value Vin is given to the differential input terminals 11 and 12, the voltages Vd1 and Vd1 ′ are shifted in opposite directions with the voltage Va as a center, so that the expressions (7) and (8) Can be represented.
Vd1 = Va + b · Vin (7)
Vd1 ′ = Va−b · Vin (8)

In equations (7) and (8), b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Further, the voltages Vg1 and Vg1 ′ can be expressed by Expression (9) and Expression (10).
Vg1 = Va + Vc−b · Vin (9)
Vg1 ′ = Va + Vc + b · Vin Equation (10)
For brevity, assuming that b = 1 and substituting Equations (7) and (9) into Equation (6) and rearranging, Equation (11) is obtained.
(Vc−Vth) / 2> Vin Formula (11)

  According to Expression (11), as long as the voltage value Vin of the input signal does not exceed (Vc−Vth) / 2, the filter circuit of the first embodiment operates normally as a filter circuit based on a source follower transistor. Therefore, the filter circuit of the first embodiment can set the limit of the input signal within an appropriate voltage value range by adjusting the voltage Vc supplied by the voltage sources 101 and 102. In the first embodiment, the voltage sources 101 and 102 for supplying the voltage Vc are added, so that the voltage value Vin of the input signal is limited to 1/2 of the threshold voltage. It can be said that the voltage value Vin of the input signal can be expanded by two.

(Embodiment 2)
1 Configuration FIG. 4 is a circuit diagram for explaining a filter circuit according to a second embodiment of the present invention. In FIG. 4, the same reference numerals are given to the configuration described with reference to FIG. 1, and a part of the description will be omitted. Reference numerals 15, 16, 21, and 22 shown in FIG. 4 are reference numerals used for explaining the relationship between FIG. 5 and FIG. 4 when the voltage source is described with reference to FIG. , Both indicate nodes.
The filter circuit according to the second embodiment includes PMOS transistors 1 to 4, capacitors 7 and 8, current sources 5 and 6, and voltage sources 301 and 302. The value of the voltage supplied by the voltage sources 301 and 302 is Vc.
The filter circuit of the second embodiment is different from the first embodiment in that voltage sources 301 and 302 are provided at positions different from the voltage sources 101 and 102 shown in FIG.

  In other words, the PMOS transistor 1 has a drain connected to the power supply terminal 23 and a gate connected to the differential input terminal 11. The source of the PMOS transistor 1 is connected to one terminal of the capacitor 7, the gate of the PMOS transistor 4, and one terminal of the voltage source 301. The other terminal of the voltage source 301 is connected to the drain of the PMOS transistor 3. As for the PMOS transistor 2, the drain is connected to the power supply terminal 23 and the gate is connected to the differential input terminal 12. The source of the PMOS transistor 2 is connected to the other terminal of the capacitor 7, the gate of the PMOS transistor 3, and one terminal of the voltage source 302. The other terminal of the voltage source 302 is connected to the drain of the PMOS transistor 4.

As for the PMOS transistor 3, the source is connected to the output terminal 13, one terminal of the capacitor 8, and the current source 5. Further, the source of the MOS transistor 4 is connected to the output terminal 14, the other terminal of the capacitor 8, and the current source 6.
FIG. 5 is a diagram for explaining the voltage source 301 shown in FIG. 4, and in order to simply express the circuit, only the left half of the circuit shown in FIG. The voltage source 301 is represented by using an actual current source circuit. Since the voltage sources 301 and 302 have the same configuration, the description of the voltage source 301 is replaced with the description of the voltage source 302.

The voltage source 301 includes current sources 72 and 73 and a resistance element 71. The same current flows through the current sources 72 and 73. The current flowing through the current source 5 is assumed to be I1. The current I1 is a current value that should flow through the MOS transistors 1 and 3 in order for the filter circuit to achieve appropriate characteristics. Further, the current value that should flow through the resistance element 71 in order for the voltage sources 301 and 302 to function properly as voltage sources is Ic. Under the above conditions, the currents IA, IB, ID flowing in each of the current sources 5, 72, 73 are expressed by the following equations.
IA = I1 Formula (12)
IB = ID = Ic + I1 (13)
With this setting, the value of the current flowing through the resistor 71 can be set to Ic, and the voltage Vc generated between both terminals 15 and 21 of the voltage source 301 can be given by Expression (5). Similarly, the voltage generated between both terminals 16 and 22 of the voltage source 302 can be given by a similar expression.

2 Operation Next, the operation of the PMOS transistor 3 in the filter circuit of the second embodiment described above will be described. The source voltage of the PMOS transistor 3 is Vs2, the gate voltage is Vg2, and the drain voltage is Vd2. In order for the PMOS transistor 3 to operate as a source follower, it is necessary to satisfy Expression (14) which is a saturation region condition.
Vd2-Vs2 <Vg2-Vs2-Vth (14)

  Vth is a threshold voltage of the PMOS transistor 3, and is a negative value when the PMOS transistor is an enhancement type. The voltage supplied by the voltage sources 301 and 302 is Vc. When the input signal is 0, that is, when the voltages of the differential input terminals 11 and 12 are the same, the voltages Vg2 'and Vg2 are also the same voltage. The voltages Vg2 'and Vg2 at this time are set as the voltage Va. The drain voltages Vd2 and Vd2 'of the PMOS transistors 3 and 4 are Va-Vc obtained by subtracting the voltage value Vc of the voltage sources 301 and 302 from the voltages Vg2' and Vg2.

When the signal Vin is applied to the differential input terminals 11 and 12, the voltages Vg2 ′ and Vg2 shift in opposite directions around the voltage Va. Therefore, the voltages Vg2 and Vg2 ′ can be expressed by equations (15) and (16).
Vg2 ′ = Va + b · Vin Formula (15)
Vg2 = Va−b · Vin Equation (16)

Here, b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Further, the drain voltages Vd2 and Vd2 ′ of the PMOS transistors 3 and 4 can be expressed by equations (17) and (18).
Vd2 = Va−Vc + b · Vin Equation (17)
Vd2 ′ = Va−Vc−b · Vin Equation (18)
For brevity, b = 1 and substituting Equation (16) and Equation (17) into Equation (14) for rearrangement yields Equation (19).
(Vc−Vth) / 2> Vin Formula (19)

Expression (19) is the same as Expression (11) obtained in the first embodiment. Therefore, in the second embodiment, the voltage sources 301 and 302 are connected to the drain terminals of the PMOS transistors 3 and 4, but the same as in the first embodiment in which the voltage source is connected to the gate terminals of the PMOS transistors 3 and 4. It turns out that an effect is acquired.
The filter circuit according to the second embodiment normally operates as a source follower-based filter unless the input signal voltage Vin exceeds (Vc−Vth) / 2. For this reason, by adding the voltage sources 301 and 302, it is possible to expand the input signal voltage by Vc / 2 as compared with the prior art.

(Embodiment 3)
1 Configuration FIG. 6 is a diagram for explaining a filter circuit according to a third embodiment of the present invention. The filter circuit of the third embodiment includes NMOS transistors 31 and 32, PMOS transistors 33 and 34, capacitors 39 and 40, current sources 35 to 38, and voltage sources 501 and 502. The power value supplied by the voltage sources 501 and 502 is Vc.
The gates of the NMOS transistors 31 and 32 are differential input terminals 43 and 44, respectively. Reference numerals 45 and 46 denote output terminals, reference numeral 58 denotes a positive power supply terminal, and reference numeral 57 denotes a negative power supply terminal. Further, reference numerals 47, 48, 51, and 52 shown in the figure are reference numerals for explaining the relationship with the voltage source shown in FIG. 3, and all indicate nodes.

  As for the NMOS transistor 31, the drain is connected to the positive power supply terminal 58 and the gate is connected to the differential input terminal 43. The source of the NMOS transistor 31 is connected to the drain of the PMOS transistor 33, one terminal of the voltage source 501, one terminal of the capacitor 40, and the current source 35. The other terminal of the voltage source 501 is connected to the gate of the PMOS transistor 34.

As for the NMOS transistor 32, the drain is connected to the positive power supply terminal 58 and the gate is connected to the differential input terminal 44. The source of the NMOS transistor 32 is connected to the drain of the PMOS transistor 34, one terminal of the voltage source 502, the other terminal of the capacitor 40, and the current source 36. The other terminal of the voltage source 502 is connected to the gate terminal 51 of the PMOS transistor 33.
As for the PMOS transistor 33, the source is connected to the current source 37, one terminal of the capacitor 39, and the output terminal 45. The source of the PMOS transistor 34 is connected to the current source 38, the other end of the capacitor 39, and the output terminal 46.

  The voltage sources 501 and 502 have the same configuration as the voltage source 101 shown in FIG. 3 in the first embodiment. However, in the third embodiment, when the voltage source shown in FIG. 3 is the voltage source 501, the terminal 66 shown in FIG. 3 is connected to the terminal 52 in FIG. 6, and the terminal 67 shown in FIG. Connected to terminal 47. When the voltage source shown in FIG. 3 is the voltage source 502, the terminal 66 shown in FIG. 3 is connected to the terminal 51 in FIG. 6, and the terminal 67 shown in FIG. 3 is connected to the terminal 48 in FIG. The

2 Operation Next, the operation of the PMOS transistor 33 in the third embodiment will be described. The source voltage of the PMOS transistor 33 is Vs3, the gate voltage is Vg3, and the drain voltage is Vd3. In order for the PMOS transistor 33 to operate as a source follower, it is necessary to satisfy Expression (20), which is a saturation region condition.
Vd3-Vs3 <Vg3-Vs3-Vth Formula (20)

  Vth is a threshold voltage of the PMOS transistor 33, and is a negative value when the PMOS transistor 33 is an enhancement type. The voltage supplied by the voltage sources 501 and 502 is Vc. When the input signal is 0, that is, when the voltages of the differential input terminals 43 and 44 are the same, the voltages Vd3 and Vd3 'are the same voltage. The voltages Vd3 and Vd3 'at this time are Va. The voltages Vg3 and Vg3 'at the terminals 51 and 52 are Va + Vc obtained by adding the voltage value Vc supplied from the voltage sources 501 and 502 to Vd3 and Vd3'.

When the signal Vin is applied to the differential input terminals 43 and 44, the voltages Vd3 and Vd3 ′ of the terminals 47 and 48 shift in opposite directions with the voltage Va as a center. The voltages Vd3 and Vd3 ′ are expressed by the following equations (21) and (22).
Vd3 = Va + b · Vin Equation (21)
Vd3 ′ = Va−b · Vin Formula (22)

Here, b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Further, Vg3 and Vg3 ′ can be expressed by Expression (23) and Expression (24).
Vg3 = Va + Vc−b · Vin Formula (23)
Vg3 ′ = Va + Vc + b · Vin Formula (24)
Hereinafter, when b = 1 for brevity and Expression (21) and Expression (23) are substituted into Expression (20) and rearranged, Expression (25) is obtained.
(Vc−Vth) / 2> Vin Formula (25)

  From Expression (25), it can be seen that, in the third embodiment, the filter circuit operates normally as a filter circuit based on the source follower as long as the voltage Vin of the input signal does not exceed (Vc−Vth) / 2. Further, Expression (25) is the same expression as Expression (10) obtained in the first embodiment. Therefore, as shown in FIG. 6, when the MOS transistor 31 and the MOS transistor 33 and the MOS transistor 32 and the MOS transistor 34 are folded back and the voltage sources 501 and 502 are added, the input signal voltage is expanded as in the first embodiment. can do.

(Embodiment 4)
1 Configuration FIG. 7 is a diagram for explaining a filter circuit according to a fourth embodiment of the present invention. In the fourth embodiment, in FIG. 7, the same components as those described in FIG. 6 are denoted by the same reference numerals, and the description thereof is partially omitted.
The filter circuit of the fourth embodiment includes NMOS transistors 31 and 32, PMOS transistors 33 and 34, capacitors 39 and 40, current sources 35 to 38, and voltage sources 601 and 602. The power value supplied by the voltage sources 601 and 602 is Vc. The gate terminals of the NMOS transistors 31 and 32 are connected to the differential input terminals 43 and 44, respectively. Reference numerals 45 and 46 denote output terminals, reference numeral 58 denotes a positive power supply terminal, and reference numeral 57 denotes a negative power supply terminal. Reference numerals 47, 48, 55, and 56 are symbols assigned to indicate the relationship with the voltage source of FIG. 8 described later, and all indicate nodes.

The fourth embodiment is different from the third embodiment in which the voltage sources 501 and 602 are provided at the gates of the PMOS transistors 33 and 34 in that the voltage sources 601 and 602 are provided at the drains of the PMOS transistors 33 and 34.
That is, in the fourth embodiment, the drain of the NMOS transistor 31 is connected to the power supply terminal 58, the gate is connected to the differential input terminal 43, the source is the gate of the PMOS transistor 34, one terminal of the voltage source 601, and the capacitor 40. Is connected to the current source 35. The other terminal of the voltage source 601 is connected to the drain of the PMOS transistor 33 at the terminal 55.

As for the NMOS transistor 32, the drain is connected to the power supply terminal 58, the gate is connected to the differential input terminal 44, the source is the gate of the PMOS transistor 33, one terminal of the voltage source 602, the other terminal of the capacitor 40, the current. Connected to source 36. The other terminal of the voltage source 602 is connected to the drain of the PMOS transistor 34.
The source of the PMOS transistor 33 is connected to the current source 37, one terminal of the capacitor 39, and the output terminal 45. The source of the PMOS transistor 34 is connected to the current source 38, the other terminal of the capacitor 39, and the output terminal 46.

  FIG. 8 is a diagram for explaining the voltage source 601 shown in FIG. In the fourth embodiment, for simplification of description, only the left half of the filter circuit shown in FIG. 7 excluding the capacitor is shown using an actual current source circuit. Since the voltage sources 601 and 602 have the same configuration, the description of the voltage source 601 is replaced with the description of the voltage source 602. However, in the case of the voltage source 602, the node 55 shown in the figure becomes the node 56 shown in FIG.

As illustrated, the voltage source 601 according to the fourth embodiment includes current sources 77 and 78 and a resistance element 76. Assuming that the current values flowing in each of the current sources 35, 37, 77, and 78 are IE, IF, IG, and IH, IE, IF, IG, and IH are expressed by the following equations (26) to (29). .
IE = I2 Formula (26)
IF = I3 Formula (27)
IG = Ic Formula (28)
IH = I3 + Ic Formula (29)

In the above equation, Ic is a current value that should flow through the resistance element 76 in order for the voltage source 601 to function as an appropriate voltage source. I2 and I3 are current values to be passed through the MOS transistors 31 and 33 in order for the filter circuit to realize appropriate characteristics.
With this setting, the value of the current flowing through the resistor 76 can be set to Ic, and the voltage Vc generated between both terminals 47 and 55 of the voltage source 601 can be given by the equation (5). Similarly, the voltage generated between both terminals 48 and 56 of the voltage source 602 can be given by a similar expression.

2 Operation Next, the operation of the PMOS transistor 33 in the filter circuit of the fourth embodiment described above will be described. The source voltage of the PMOS transistor 33 is Vs4, the gate voltage is Vg4, the drain voltage is Vd4, the source voltage of the PMOS transistor 34 is Vs4 ′, the gate voltage is Vg4 ′, and the drain voltage is Vd4 ′. In order for the PMOS transistor 33 to operate as a source follower, it is necessary to satisfy Expression (30), which is a saturation region condition.
Vd4-Vs4 <Vg4-Vs4-Vth Formula (30)

Vth is a threshold voltage of the PMOS transistor 33, and is a negative numerical value when the PMOS transistor 33 is an enhancement type.
When the input signal is 0, that is, when the voltages of the differential input terminals 43 and 44 are the same, the voltages Vg4 ′ and Vg4 are also the same voltage. The values of voltages Vg4 ′ and Vg4 at this time are Va. Similarly, the voltages Vd4 and Vd4 ′ are Va−Vc obtained by subtracting the voltage value Vc supplied from the voltage sources 601 and 602 from the voltage Va of Vg4 ′ and Vg4.

When the signal Vin is applied to the differential input terminal, the voltages Vg4 ′ and Vg4 of the terminals 47 and 48 shift in opposite directions with the voltage Va as the center. Therefore, the voltages Vg4 ′ and Vg4 are expressed by equations (31) and (32).
Vg4 ′ = Va−b · Vin Formula (31)
Vg4 = Va + b · Vin Equation (32)

b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Further, the voltages Vd4 and Vd4 ′ of the terminals 55 and 56 are expressed by Expression (33) and Expression (34).
Vd4 = Va−Vc + b · Vin Equation (33)
Vd4 ′ = Va−Vc−b · Vin Formula (34)

Hereinafter, when b = 1 for brevity, Expression (35) is obtained by substituting Expression (32) and Expression (33) into Expression (30) and rearranging.
(Vc−Vth) / 2> Vin Formula (35)
The expression (35) is the same as the expression (11) obtained in the first embodiment, the expression (19) obtained in the second embodiment, and the expression (25) obtained in the third embodiment. Therefore, it is apparent that the input signal voltage of the filter circuit can be expanded by Vc / 2 by adding the voltage sources 601 and 602 even in the fourth embodiment.

(Embodiment 5)
1 Configuration FIG. 9 is a diagram for explaining a filter circuit according to a fifth embodiment. In the fifth embodiment, in FIG. 9, the same components as those described in FIG. 4 are denoted by the same reference numerals, and the description thereof is partially omitted.
In the filter circuit of the fifth embodiment, all the circuit elements except the positive and negative power supply terminals 24 and 23 of the filter circuit of the second embodiment shown in FIG. -4 are replaced with NMOS transistors 803-806.

2 Operation Next, the operation of the NMOS transistor 803 in the filter circuit of the fifth embodiment shown in FIG. 9 will be described. The source voltage of the NMOS transistor 803 is Vs5, the gate voltage is Vg5, the drain voltage is Vd5, the source voltage of the NMOS transistor 804 is Vs5 ′, the gate voltage is Vg5 ′, and the drain voltage is Vd5 ′. At this time, in order for the NMOS transistor 803 to operate as a source follower, each voltage needs to satisfy Expression (36), which is a saturation region condition.
Vd5-Vs5> Vg5-Vs5-Vth Formula (36)

  In Expression (36), Vth is a threshold voltage of the NMOS transistor 803, and is a positive numerical value when the NMOS transistor 803 is an enhancement type. The voltage supplied by the voltage sources 801 and 802 is Vc. When the input signal is 0, that is, when the voltages of the differential input terminals 11 and 12 are the same, the voltages Vg5 'and Vg5 are also the same voltage. The voltages Vg5 'and Vg5 at this time are set as the voltage Va. The voltages Vd5 and Vd5 'are Va + Vc obtained by adding the voltage value Vc of the voltage sources 801 and 802 to Vg5' and Vg5.

When the signal Vin is supplied to the differential input terminals 11 and 12, the voltages Vg5 ′ and Vg5 are shifted in directions opposite to each other around the voltage Va. Therefore, the voltages Vg5 and Vg5 ′ can be expressed by equations (37) and (38).
Vg5 ′ = Va−b · Vin Formula (37)
Vg5 = Va + b · Vin Equation (38)

Here, b is a value determined by the frequency characteristics of the filter, and is 1 in the case of DC (direct current). Further, the voltages Vd5 and Vd5 ′ can be expressed by Expression (39) and Expression (40).
Vd5 = Va + Vc−b · Vin Formula (39)
Vd5 ′ = Va + Vc + b · Vin Formula (40)
For brevity, b = 1 and substituting Equation (38) and Equation (39) into Equation (36) for rearrangement yields Equation (41).
(Vc + Vth) / 2> Vin Formula (41)

  According to Expression (41), as long as the voltage value Vin of the input signal does not exceed (Vc + Vth) / 2, the filter circuit of Embodiment 5 operates normally as a filter circuit based on a source follower transistor. Therefore, the filter circuit of the fifth embodiment can set the limit of the input signal within an appropriate voltage value range by adjusting the voltage Vc supplied by the voltage sources 801 and 802. In the fifth embodiment, since the voltage sources 801 and 802 for supplying the voltage Vc are added, the voltage value Vin of the input signal is limited to ½ of the threshold voltage. It can be said that the voltage value Vin of the input signal can be expanded by two.

  The expression (41) is obtained from the operating conditions of the NMOS transistor 803, and the expression (11) applied in the case of the first to fourth embodiments is the same as the PMOS transistor 3 of the first and second embodiments. This is derived from the fact that the conductivity type of the MOS transistor is P-type, like the PMOS transistors 33 of 3 and 4. That is, the filter circuit of the fifth embodiment also includes the voltage sources 801 and 802, so that the input signal voltage of the filter circuit can be expanded as in the second to fourth embodiments. The formula applied in this case is formula (41) in which the conductivity type of the MOS transistor is N-type.

  Furthermore, in the first embodiment, the capacitors 1 and 2 are connected between the source terminals of the MOS transistors 1 and 2 and the MOS transistors 3 and 4, respectively, as shown in FIG. A capacitor having a capacitance value twice that of the capacitor 1 is connected between the source of 2 and 2 and the analog ground (for example, a negative power supply terminal or a positive power supply terminal), and between the sources of the MOS transistors 3 and 4 and the analog ground. Even if a capacitor having a capacitance value twice that of the capacitor 2 is connected to the capacitor, the same characteristics can be realized as a filter. Such a configuration change can also be implemented in the second to fifth embodiments. Such a configuration change is not performed because the number of capacitors is doubled and the capacitance value is also doubled. However, when utilizing the diode junction capacitance between the MOS source and the substrate, such a method is used. Become.

Example 1
As described above, Embodiments 1 to 5 can increase the input signal level of the filter circuit by adding a voltage source. As is clear from Equation (11) and the like, Embodiments 1 to 5 can increase the input signal level as the voltage value Vc of the voltage source is increased. However, a lower power supply voltage is used by setting the voltage value supplied by the voltage source to the voltage value Vcst satisfying the equation (42) or the equation (43), not the voltage value Vc set as the design value. Thus, the input signal level can be expanded efficiently.

As shown in the equation (42) or the equation (43), the voltage value Vcst is the threshold value Vth of the MOS transistors (for example, the PMOS transistors 3 and 4 shown in FIG. 1) constituting the filter circuit from the voltage value Vc. This is a value obtained as a result of subtraction or as a result of adding the voltage value Vc and the threshold value Vth of the MOS transistors (for example, NMOS transistors 803 and 804 shown in FIG. 9).
Vcst = Vc−Vth Formula (42)
Vcst = Vc + Vth Formula (43)

FIG. 10 is a circuit diagram illustrating a specific example of a voltage source that satisfies the equation (42). The circuit of FIG. 10 is a circuit that generates the voltage Vc of the voltage source corresponding to the threshold voltage Vth of the MOS transistor. In this specification, the voltage source in which the generated voltage value is adjusted according to the conditions of other elements included in the circuit is referred to as an adaptive voltage generation circuit.
The voltage source circuit shown in FIG. 10 includes PMOS transistors 94, 92, 82, 87, NMOS transistors 93, 91, 81, 86, resistance elements 83, 88, 95, a differential amplifier 96, and a voltage source. Functional circuits 97, 98, current control terminals 901, 902, terminals 84, 85, 89, 90, 99, 900, 903, and positive and negative power supply terminals 904, 905 are provided.

  The gate and drain of the PMOS transistor 94 are connected to the terminal 903. The source of the PMOS transistor 94 is connected to the positive power supply terminal 904. The terminal 903 is connected to one end of the resistance element 95, the other terminal 99 of the resistance element 95 is connected to the drain of the NMOS transistor 93 and the non-inverting input terminal of the differential amplifier 96, and the inverting input terminal of the differential amplifier. The voltage Vdd-Vref is supplied to 900.

  The current control terminal 901 which is the output terminal of the differential amplifier 96 is connected to the gates of the NMOS transistors 93, 91, 81 and 86, and the sources of the NMOS transistors 93, 91, 81 and 86 are connected to the negative power supply terminal 905. ing. A current control terminal 902 which is a drain terminal of the NMOS transistor 91 is connected to a terminal connecting the gate and drain of the PMOS transistor 92 and to gate terminals of the PMOS transistors 82 and 87.

  The sources of the PMOS transistors 92, 82, 87 are connected to the positive power supply terminal 904, the drain of the PMOS transistor 82 is connected to one terminal 84 of the resistance element 83, and the drain of the MOS transistor 87 is the one terminal of the resistance element 88. The drain of the NMOS transistor 81 is connected to the other terminal 85 of the resistance element 83, and the drain of the NMOS transistor 86 is connected to the other terminal 90 of the resistance element 88.

  In FIG. 10, a circuit 97 surrounded by a dotted line is a circuit similar to the voltage source shown in FIG. 3, and corresponds to the voltage source 101 shown in FIG. The terminals 84 and 85 shown in FIG. 10 correspond to the terminals 18 and 15 shown in FIG. A circuit 98 surrounded by a dotted line corresponds to the voltage source 102 of the circuit of FIG. 1, and terminals 89 and 90 correspond to the terminals 17 and 16 of FIG. 1, respectively. Therefore, the voltage Vc of the voltage source is generated between the terminals 84 and 85 and between the terminals 89 and 90.

Next, the operation of the voltage source circuit of FIG. 10 will be described.
In the description of FIG. 10, for the sake of easy understanding, the NMOS transistors 93, 91, 81, 86 have the same element size, and the PMOS transistors 92, 82, 87 have the same size. Further, the resistance values of the resistance elements 83, 88, and 95 are all the same. Under such conditions, NMOS transistors 93, 91, 81, 86 having a common gate terminal, PMOS transistors 92, 82, 87, and resistance elements 95, 83, 88, supplied with current from these MOS transistors. The currents flowing through the NMOS transistor 94 are all the same.

For this reason, the voltage Vc generated at both terminals of the resistance elements 83, 88, and 95 has the same value. The output signal of the differential amplifier 96 is applied to the gate of the NMOS transistor 93 to control the current flowing through the NMOS transistor 93. The voltage generated at the terminal 99 is controlled by this controlled current. Terminal 99 is connected to the non-inverting input terminal of differential amplifier 96.
Therefore, the differential amplifier 96, the NMOS transistor 93, the MOS transistor 94, and the resistance element 95 form a negative feedback circuit. If the loop gain in the negative feedback circuit is sufficiently high, the voltage at the terminal 99 becomes equal to the voltage V900 at the terminal 900 as shown in equation (44).
V99 = V900 Formula (44)

Here, the voltage of the terminal 900 is Vdd−Vref which is a value lower than the positive power supply voltage Vdd by the reference voltage Vref as shown in the equation (45).
V900 = Vdd−Vref Equation (45)
Here, the reference voltage Vref is always constant regardless of the power supply voltage and the environmental temperature, and is normally generated from the reference voltage source. Further, the voltage V99 at the terminal 99 is a value obtained by subtracting the inter-terminal voltage Vc of the resistance element 95 and the source-gate voltage Vsg of the MOS transistor 94 from the positive power supply voltage Vdd as shown in the equation (46).
V99 = Vdd−Vsg−Vc Equation (46)

Since the gate-source voltage Vgs and the source-gate voltage Vsg of the MOS transistor have a relationship of Vgs = −Vsg, the relational expression (47) is obtained from the expressions (44) to (46).
Vref = Vc−Vgs Equation (47)
When the current flowing through the PMOS transistor 94 is small or the size of the PMOS transistor is sufficiently large, the gate-source voltage Vgs can be set to a value close to the threshold voltage Vth of the PMOS transistor. In such a case, the reference voltage Vref can be approximated as shown in Expression (48).
Vref = Vc−Vth (48)

  Expression (49) shows that the value obtained by subtracting the threshold voltage Vth of the PMOS transistor from the voltage value Vc is always a constant value Vref regardless of the fluctuation of the threshold voltage. That is, Formula (42) is implement | achieved. In other words, since the circuit of FIG. 10 can always be controlled to be constant regardless of Vc−Vth, the input signal voltage can be set to the maximum with a low power supply voltage.

  In addition, FIG. 10 implement | achieves Formula (42). However, as the second embodiment has the configuration of the fifth embodiment, all the circuit elements except the positive and negative power supply terminals 904 and 905 of the circuit shown in FIG. By replacing all the PMOS transistors with NMOS transistors and all the NMOS transistors with PMOS transistors, a circuit that realizes equation (43) can be obtained. In this case, the voltage at the terminal 900 may be Vss + Vref, which is higher than the negative power supply voltage Vss by the reference voltage Vref instead of the equation (45).

(Example 2)
FIG. 11 is a diagram illustrating a circuit of a voltage source that can supply the voltage Vc with higher accuracy than the voltage source shown in FIG. The circuit shown in FIG. 11 is configured by adding PMOS transistors 912 and 913, an NMOS transistor 911, and a current source 914 to the circuit of the first embodiment shown in FIG.
That is, in the voltage source of the second embodiment, the current control terminal 901 of the differential amplifier 96 is connected to the gate of the NMOS transistor 911, and the drain of the MOS transistor 911 is connected to the drain and gate of the PMOS transistor 912 via the terminal 915. It is connected. The PMOS transistor 913 has a gate connected to the terminal 915 and a drain connected to the terminal 903. The current source 914 is connected to the terminal 903.

In the voltage source of the second embodiment configured as described above, the element sizes of the MOS transistor 911 and the MOS transistor 93 having a common gate are made the same. The element sizes of the MOS transistors 912 and 913 are the same as those of the MOS transistor 94. In such a case, the same current flows in all the MOS transistors and all the resistance elements included in the circuit of FIG. The voltage Vr between the terminals of the resistance elements 83, 88, and 95 is also equal.
Here, the currents flowing through the NMOS transistor 93 and the PMOS transistor 913 are equal. For this reason, the current flowing through the MOS transistor 94 is determined by the current flowing through the current source 914 without depending on the value of the current flowing through the resistance element 95.

  Therefore, in the second embodiment, if the current value of the current source 914 is set so that the voltage between the gate and the source of the MOS transistor becomes the threshold voltage Vth more accurately, the voltage with higher accuracy than in the first embodiment. It becomes possible to provide a voltage source capable of supplying the value Vc. According to the voltage source of the second embodiment, the fluctuation of the supplied voltage value can be estimated to be small, so that the input signal level can be efficiently expanded by using a voltage source having a lower power supply voltage. . FIG. 11 more accurately realizes the equation (42). However, all circuit elements except the positive and negative power supply terminals 904 and 905 of the circuit shown in FIG. In addition, by replacing all the PMOS transistors with NMOS transistors and all the NMOS transistors with PMOS transistors, a circuit that realizes the equation (43) more accurately can be obtained. In this case, the voltage at the terminal 900 may be Vss + Vref, which is higher than the negative power supply voltage Vss by the reference voltage Vref instead of the equation (45).

  The present invention can be applied to all filter circuits in which it is desirable that the maximum input signal level is not limited by the threshold voltage of the MOS transistor.

1, 2, 3, 4, 33, 34, 61, 82, 87, 92, 94, 912, 913
PMOS transistor 5, 6, 35, 36, 37, 38, 72, 77, current source 7, 8, 39, 40 Capacitor 11, 12, 43, 44 Differential input terminal 13, 14, 45, 46 Output terminal 23, 24, 57, 58, 68, 69, 105 Power supply terminal 31, 32, 62, 81, 86, 91, 93, 911 NMOS transistor 63, 71, 76, 83, 88, 95 Resistive element 96 Differential amplifier 97, 98 Circuit 101, 102, 301, 302, 501, 502, 601, 602, 801, 802
Voltage source 900 Inverting input terminal 901, 902 Current control terminal

Claims (11)

A first transistor pair comprising: a first MOS transistor having a first input signal input to the gate; and a second MOS transistor having a second input signal input to the gate;
The drain is connected to the source of the first MOS transistor, the gate is connected to the source of the second MOS transistor, the third MOS transistor from which the first output signal is output, and the drain is connected to the source of the second MOS transistor. A second transistor pair comprising: a fourth MOS transistor having a gate connected to the source of the first MOS transistor and a second output signal output from the source;
A current source pair comprising: a first current source that supplies current to the source of the third MOS transistor; and a second current source that supplies current to the source of the fourth MOS transistor;
A capacitor connected to each of the sources of the first to fourth MOS transistors;
A filter circuit comprising:
Voltage applying means for applying a voltage to the third MOS transistor and the fourth MOS transistor so that the operating points of the transistors shift in a direction from the side closer to the linear region in the saturation region to the side farther from the linear region;
A filter circuit comprising: The voltage applying means includes
The third MOS transistor is connected between the gate of the third MOS transistor and the drain of the fourth MOS transistor, and the operating point of the third MOS transistor is in a direction from the side closer to the linear region in the saturation region to the side farther from the linear region. A first voltage source for applying a voltage so as to shift, and a gate of the fourth MOS transistor and a drain of the third transistor are connected, and the operating point of the fourth MOS transistor is in a saturation region in the fourth MOS transistor The filter circuit according to claim 1, further comprising: a second voltage source that applies a voltage so as to shift in a direction from a side closer to the linear region to a side farther from the linear region. The voltage applying means includes
The third MOS transistor is connected between the source of the first MOS transistor and the drain of the third transistor, and the operating point of the third MOS transistor is in a direction from the side closer to the linear region in the saturation region to the side farther from the linear region. A third voltage source for applying a voltage so as to shift; and a source connected to the source of the second MOS transistor and a drain of the fourth transistor; the operating point of the fourth MOS transistor is in a saturation region in the fourth MOS transistor The filter circuit according to claim 1, further comprising: a fourth voltage source that applies a voltage so as to shift in a direction from a side closer to a linear region to a side farther from the linear region.   A conductivity type of the first MOS transistor and the second MOS transistor is different from a conductivity type of the third MOS transistor and the fourth MOS transistor, a third current source connected to a source of the first MOS transistor, and a source of the second MOS transistor The filter circuit according to claim 1, further comprising a fourth current source connected to the filter circuit. The voltage applying means includes
2. A voltage source including a first resistance element having a first terminal that receives a current supply from a fifth current source and a second terminal that receives a current supply from a sixth current source. 5. The filter circuit according to any one of 4 above. The voltage source is
An adaptive voltage generating circuit that generates a voltage such that a value obtained by adding or subtracting a voltage value applied by the voltage source and a MOS transistor threshold value of the second transistor pair becomes a constant voltage value; The filter circuit according to claim 5. The adaptive voltage generation circuit includes:
When the electric type of the MOS transistor of the second transistor pair is N-type, the voltage value obtained by adding the voltage value applied by the voltage source and the MOS transistor threshold value of the second transistor pair becomes a constant value. When the electric type of the MOS transistor of the second transistor pair is P type, the voltage value obtained by subtracting the MOS transistor threshold value of the second transistor pair from the voltage value applied by the voltage source The filter circuit according to claim 6, wherein the voltage is generated so that becomes a constant value. The third voltage source is
A second resistance element;
A seventh current source connected in parallel with the first current source, the third MOS transistor, and the second resistance element;
An eighth current source connected in parallel with the second resistance element and the first MOS transistor;
The current values supplied by the seventh current source and the eighth current source are both equal to the sum of the current value supplied by the first current source and the current value flowing through the second resistance element,
The fourth voltage source is
A third resistance element;
A ninth current source connected in parallel with the second current source, the fourth MOS transistor, and the third resistance element;
A third current element, a tenth current source connected in parallel with the second MOS transistor,
The current values supplied by the ninth current source and the tenth current source are both equal to the sum of the current value supplied by the second current source and the current value flowing through the third resistance element. The filter circuit according to claim 3. A conductivity type of the first MOS transistor and the second MOS transistor is different from a conductivity type of the third MOS transistor and the fourth MOS transistor, a third current source connected to a source of the first MOS transistor, and a source of the second MOS transistor A fourth current source connected to
The third voltage source is
A fourth resistance element connected in parallel with the first MOS transistor and in series with the first current source, the third current source, and the third MOS transistor;
An eleventh current source connected in parallel to any of the first MOS transistor, the first current source and the fourth resistance element, and the third MOS transistor;
A twelfth current source connected in parallel with the fourth resistance element and the third current source,
The eleventh current source supplies a current having the same current value as the current flowing through the fourth resistance element, and the current value supplied by the twelfth current source is the value of the current supplied by the eleventh current source. Equal to the sum of the values of current supplied by the first current source, and
The fourth voltage source is
A fifth resistance element connected in parallel with the second MOS transistor and in series with the second current source, the fourth current source, and the fourth MOS transistor;
A thirteenth current source connected in parallel to any of the second MOS transistor, the second current source and the fifth resistance element, and the fourth MOS transistor;
A fourteenth current source connected in parallel with the fifth resistance element and the fourth current source,
The thirteenth current source supplies a current having the same current value as the current flowing through the fifth resistance element, and the current value supplied by the fourteenth current source is the value of the current supplied by the thirteenth current source. 4. The filter circuit according to claim 3, wherein the filter circuit is equal to a sum of current values supplied by the second current source. The fifth current source is a fifth MOS transistor, and the sixth current source is a sixth MOS transistor;
A differential amplifier that inputs an input signal from a non-inverting terminal and an inverting terminal and outputs a difference as an output signal;
A seventh MOS transistor having a gate to which an output signal of the differential amplifier is input;
An eighth MOS transistor having a gate connected to the gate of the seventh MOS transistor and a drain connected to the non-inverting terminal;
A ninth MOS transistor having a drain connected to the drain of the eighth MOS transistor via a sixth resistance element, and a gate connected to the drain;
A tenth MOS transistor having a drain connected to the drain of the seventh MOS transistor, a gate connected to the drain, and a source connected to the source of the ninth MOS transistor;
Further comprising
An output signal of the differential amplifier is input to the gate of the fifth MOS transistor to control the fifth MOS transistor,
7. The filter circuit according to claim 6, wherein a terminal connected to the gate and drain of the tenth MOS transistor is input to the gate of the sixth MOS transistor to control the sixth MOS transistor. An eleventh MOS transistor having a gate terminal connected to the output terminal of the differential amplifier, a drain connected to the drain terminal of the eleventh MOS transistor, a twelfth MOS transistor having a gate connected to the drain, and a drain of the twelfth MOS transistor And a thirteenth MOS transistor having a gate connected to the gate; a fifteenth current source connected to the drain of the ninth MOS transistor;
Further comprising
11. The filter circuit according to claim 10, wherein the sixth resistance element is connected to a drain of the eighth MOS transistor, a drain and a gate of a ninth MOS transistor, and a drain of the thirteenth MOS transistor.

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