JP2010225851A - Substrate for controlling solder deposition - Google Patents

Substrate for controlling solder deposition Download PDF

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JP2010225851A
JP2010225851A JP2009071552A JP2009071552A JP2010225851A JP 2010225851 A JP2010225851 A JP 2010225851A JP 2009071552 A JP2009071552 A JP 2009071552A JP 2009071552 A JP2009071552 A JP 2009071552A JP 2010225851 A JP2010225851 A JP 2010225851A
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substrate
electrode
solder
side electrode
deposition control
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Masahiko Furuno
雅彦 古野
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Tamura Corp
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Tamura Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for controlling solder deposition which makes an electrode hardly peeled off from the substrate, can cope with the fine pitch of the electrode, and does not cause a short circuit between the electrodes. <P>SOLUTION: There is provided a substrate 1 for controlling solder deposition which mounts a connecting electrode of an electronic component in a flip-chip manner via solder on the arrangement of a substrate side electrode 2 the portion of which is exposed from a solder resist opening 4 formed at the substrate 1. At least one of both ends forming longitudinal directions of ends of an exposed portion of the substrate side electrode 2 is inclined by a predetermined electrode spread angle. One of both the ends forming the transverse directions of the ends of the exposed portion of the substrate side electrode 2 forms a maximum width in the transverse direction of the exposed portion of the substrate side electrode 2. The other end forms a minimum width in the transverse direction of the exposed portion of the substrate side electrode 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、シリコンチップに代表される半導体チップ等の電子部品を、電極パターンが形成された基板に、はんだ材料を用いてフリップチップ実装する場合の基板に関する。   The present invention relates to a substrate in which an electronic component such as a semiconductor chip represented by a silicon chip is flip-chip mounted on a substrate on which an electrode pattern is formed using a solder material.

近年、半導体チップ等の電子部品の高密度は急速に進められており、これに伴い電子部品に配設された外部接続端子となる電極のピッチも微細化してきている。従って、この電子部品がフリップチップ実装されるフリップチップ実装基板においても、電子部品が接合される電極を高密度に形成する必要があり、かつ高い接続信頼性を持ってフリップチップ実装する必要がある。   In recent years, the density of electronic components such as semiconductor chips has been rapidly increased, and accordingly, the pitch of electrodes serving as external connection terminals provided in the electronic components has also been reduced. Therefore, even in a flip chip mounting substrate on which this electronic component is flip-chip mounted, it is necessary to form electrodes with high density and to be flip-chip mounted with high connection reliability. .

一般には、半導体チップ等の電子部品をフリップチップ実装基板にフリップチップ実装する場合、予めフリップチップ実装基板に形成されている電極に接続媒体であるはんだを配設しておく。そして、前記電極に半導体チップに設けられている接続用電極を接合することにより、半導体チップをフリップチップ実装基板にフリップチップ実装することが行なわれている。   In general, when an electronic component such as a semiconductor chip is flip-chip mounted on a flip-chip mounting substrate, solder as a connection medium is disposed in advance on an electrode formed on the flip-chip mounting substrate. A semiconductor chip is flip-chip mounted on a flip-chip mounting substrate by bonding a connection electrode provided on the semiconductor chip to the electrode.

フリップチップ実装基板に形成されている電極へのはんだ供給法には、例えば、はんだ粉を含有したはんだペーストを前記電極に印刷し、はんだペーストをリフロー炉で加熱溶融する方法がある。このとき、溶融して液状になったはんだには表面張力が発生し、この表面張力によりはんだは瘤状となって、フリップチップ実装基板側電極上の不特定位置にはんだ溜りが形成される。   As a method for supplying solder to an electrode formed on a flip chip mounting substrate, for example, there is a method in which a solder paste containing solder powder is printed on the electrode, and the solder paste is heated and melted in a reflow furnace. At this time, surface tension is generated in the melted and liquid solder, and the surface tension causes the solder to form a bump, and a solder pool is formed at an unspecified position on the flip chip mounting board side electrode.

従って、電子部品をフリップチップ実装基板に対向させた際に、電子部品の接続用電極とはんだ溜りとの位置にずれが生じてしまう。位置ずれが生じると、電子部品の接続用電極と対向する位置には、はんだ薄膜のみが形成された状態となっているので、電子部品をフリップチップ実装基板に実装しても、電子部品の接続用電極とフリップチップ実装基板の電極との間に十分な接合力を得ることができず、接続信頼性が低下してしまうという問題がある。さらには、電極ピッチの微細化により、フリップチップ実装基板側電極への十分なはんだ供給が困難になっているという問題がある。   Therefore, when the electronic component is made to face the flip chip mounting substrate, the position of the connection electrode of the electronic component and the solder pool is displaced. When the misalignment occurs, only the solder thin film is formed at the position facing the connection electrode of the electronic component. Therefore, even if the electronic component is mounted on the flip chip mounting board, the electronic component is connected. There is a problem that a sufficient bonding force cannot be obtained between the electrodes for use and the electrodes of the flip chip mounting substrate, and the connection reliability is lowered. Furthermore, there is a problem that sufficient solder supply to the flip chip mounting substrate side electrode is difficult due to the miniaturization of the electrode pitch.

そこで、これらの問題を解決するために、配線となる配線パターンと、電子部品のはんだバンプが接合される位置に配線パターンと連続的に形成された接続パッドとにより構成した接続部導体パターンであって、配線パターンの幅寸法に対し、接続パッドの幅寸法を大きくしたフリップチップ実装用基板がある(特許文献1)。この基板は、はんだ溜りを接続パッド上に形成させるので、電子部品をフリップチップ実装基板に実装する際に、はんだバンプの接続位置にはんだ溜りが存在することとなり、電子部品とフリップチップ実装基板との接続信頼性を高めることができるとしている。また、接続パッドの幅寸法を大きくしたので、フリップチップ実装基板側電極への十分なはんだ供給量を確保できるというものである。   Therefore, in order to solve these problems, a connection portion conductor pattern constituted by a wiring pattern to be a wiring and a wiring pattern and a connection pad formed continuously at a position where a solder bump of an electronic component is joined. Thus, there is a flip chip mounting substrate in which the width dimension of the connection pad is larger than the width dimension of the wiring pattern (Patent Document 1). Since this board forms solder pools on the connection pads, when mounting electronic components on flip chip mounting boards, there will be solder pools at the solder bump connection positions, and the electronic parts and flip chip mounting boards The connection reliability can be improved. Further, since the width dimension of the connection pad is increased, a sufficient amount of solder can be secured to the flip chip mounting board side electrode.

しかし、特許文献1では、前記配線パターン部分は細長い長方形状なので、該部分は基板との接触面積が小さい。従って、該部分は、基板との密着強度が弱くなり、基板から剥離し易いので、機械的信頼性に問題がある。また、接続パッドは幅寸法を大きくした長方形状なので、依然として接続パッド上の不特定部位にはんだ溜りが形成されることとなる。さらに、その形状から電極配列のファインピッチ化には不向きである一方、接続パッド間では、そのスペースが小さくなって、隣接する電極とのショート不良をおこすという問題もある。   However, in Patent Document 1, since the wiring pattern portion is an elongated rectangular shape, the contact area with the substrate is small. Accordingly, the adhesion strength with the substrate becomes weak and the portion is easily peeled off from the substrate, which causes a problem in mechanical reliability. In addition, since the connection pad has a rectangular shape with a large width dimension, a solder pool is still formed at an unspecified portion on the connection pad. Further, the shape is not suitable for fine pitching of the electrode arrangement, but the space between the connection pads becomes small, and there is a problem that a short circuit with an adjacent electrode is caused.

特開2000−77471JP 2000-77471 A

本発明は、上記事情に鑑み、電極が基板から剥離しにくく、電極配列のファインピッチ化にも対応可能であり、電極間のショートを起こさないはんだ堆積制御用基板を提供することを目的とする。   SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a solder deposition control substrate that does not cause electrodes to be peeled off from the substrate, can cope with fine pitches in the electrode arrangement, and does not cause a short circuit between the electrodes. .

本発明の第1の態様は、基板上に形成されたソルダーレジスト開口部からその一部が露出した基板側電極の配列に、電子部品の接続用電極を、はんだを介してフリップチップ実装するはんだ堆積制御用基板であって、前記基板側電極の露出部の端部のうち、長手方向を形成する両端部のうちの少なくとも一方が、所定の電極広がり角度で傾斜し、前記基板側電極の露出部の端部のうち、短手方向を形成する両端部の一端が前記基板側電極の露出部の短手方向における最大幅を形成し、他端が前記基板側電極の露出部の短手方向における最小幅を形成することを特徴とするはんだ堆積制御用基板である。   According to a first aspect of the present invention, a solder for flip-chip mounting a connection electrode of an electronic component via a solder on an array of substrate-side electrodes partially exposed from a solder resist opening formed on a substrate A deposition control substrate, wherein at least one of both end portions forming the longitudinal direction of the exposed portion of the substrate-side electrode is inclined at a predetermined electrode spreading angle, and the substrate-side electrode is exposed. One end of both ends forming the short direction among the ends of the portion forms the maximum width in the short direction of the exposed portion of the substrate side electrode, and the other end is the short direction of the exposed portion of the substrate side electrode The solder deposition control board is characterized in that a minimum width is formed.

第1の態様では、基板側電極について、その長手方向を形成する両端部のうちの少なくとも一方が、所定の電極広がり角度により傾斜している。この傾斜部により、電極は、短手方向における最小幅を形成する端部から長手方向に進むにつれて、連続的に短手方向の幅が広がっていく形状となる。はんだは加熱溶融されて液状化すると、形状の大きい液滴の方が内部圧力が低いので、液状化したはんだは大きい液滴へと集まっていくこと、及び溶融はんだの表面張力と溶融はんだが電極上を濡れ広がろうとする力とのバランスから、短手方向の電極幅が所定量広がっている特定位置に、はんだ溜りが形成される構成となる。一方で、はんだ溜りが形成された位置以外の部分には、はんだの薄膜が形成される。   In the first aspect, at least one of both end portions forming the longitudinal direction of the substrate side electrode is inclined at a predetermined electrode spreading angle. By this inclined portion, the electrode has a shape in which the width in the lateral direction continuously increases as it proceeds in the longitudinal direction from the end forming the minimum width in the lateral direction. When the solder is heated and melted and liquefied, the large droplets have a lower internal pressure, so the liquefied solder collects into large droplets, and the surface tension of the molten solder and the molten solder are the electrodes. From the balance with the force to wet and spread the top, the solder pool is formed at a specific position where the width of the electrode in the short direction is widened by a predetermined amount. On the other hand, a solder thin film is formed in a portion other than the position where the solder pool is formed.

ここで、「電極広がり角度」とは、電極露出部の長手方向の端部と、電極露出部の短手方向の最小幅を形成する端部の法線方向とがなす角度をいう。   Here, the “electrode spreading angle” refers to an angle formed by an end portion in the longitudinal direction of the electrode exposed portion and a normal direction of the end portion forming the minimum width in the short side direction of the electrode exposed portion.

本発明の第2の態様は、前記電極広がり角度が、0.5°から10°であることを特徴とするはんだ堆積制御用基板である。   According to a second aspect of the present invention, there is provided the solder deposition control substrate, wherein the electrode spreading angle is 0.5 ° to 10 °.

本発明の第3の態様は、前記長手方向を形成する両端部が、同一の前記電極広がり角度で傾斜しており、前記電極広がり角度が、1°から3°であることを特徴とするはんだ堆積制御用基板である。   According to a third aspect of the present invention, both end portions forming the longitudinal direction are inclined at the same electrode spread angle, and the electrode spread angle is 1 ° to 3 °. This is a deposition control substrate.

本発明の第4の態様は、前記短手方向における最大幅を形成する端部と、前記短手方向における最小幅を形成する端部とが、交互に配列されていることを特徴とするはんだ堆積制御用基板である。この態様では、基板側電極の配列について、短手方向における最大幅を形成する端部が、基板外縁部方向と基板中央部方向とを交互に向くように、つまり、ソルダーレジスト開口部内を千鳥状に配置されている。従って、はんだ溜りも基板表面に対して千鳥状に配置されることとなる。   According to a fourth aspect of the present invention, the end portion forming the maximum width in the short direction and the end portion forming the minimum width in the short direction are alternately arranged. This is a deposition control substrate. In this aspect, with respect to the arrangement of the substrate-side electrodes, the end portions forming the maximum width in the lateral direction are alternately directed in the substrate outer edge direction and the substrate center direction, that is, in the zigzag pattern in the solder resist opening. Is arranged. Therefore, the solder pools are also arranged in a staggered manner with respect to the substrate surface.

本発明の第5の態様は、前記長手方向を形成する両端部のうちの少なくとも一方が所定の前記電極広がり角度で傾斜し、かつ前記短手方向の端部以外の部位で前記基板側電極の露出部の前記短手方向における最大幅を形成する電極が、更に配置されていることを特徴とするはんだ堆積制御用基板である。この態様では、短手方向を形成する両端部の一端が電極露出部の短手方向における最大幅を形成し、かつ他端が電極露出部の短手方向における最小幅を形成している上記電極(A)の配列中に、さらに、電極露出部の短手方向における最大幅が短手方向の端部以外の部位に形成されている電極(B)が、適宜、配置されている。従って、電極(B)の短手方向の幅広部は、電極(A)と比較して、長手方向中央部よりに形成されるので、電極(B)の部分では、電極(A)と比較して、長手方向中央部よりにはんだ溜りが形成されることとなる。   According to a fifth aspect of the present invention, at least one of both end portions forming the longitudinal direction is inclined at a predetermined electrode spreading angle, and the substrate-side electrode is formed at a portion other than the end portion in the short direction. An electrode for forming a maximum width of the exposed portion in the short side direction is further disposed. In this embodiment, one end of both end portions forming the short direction forms the maximum width in the short direction of the electrode exposed portion, and the other end forms the minimum width in the short direction of the electrode exposed portion. In the arrangement of (A), an electrode (B) in which the maximum width in the short direction of the electrode exposed portion is formed at a portion other than the end portion in the short direction is appropriately disposed. Therefore, the wide part in the short direction of the electrode (B) is formed from the central part in the longitudinal direction as compared with the electrode (A), and therefore the part of the electrode (B) is compared with the electrode (A). Thus, a solder pool is formed from the central portion in the longitudinal direction.

本発明の第6の態様は、上記電極(B)について、前記短手方向における最大幅が、前記基板側電極の露出部の長手方向中央部に形成されていることを特徴とするはんだ堆積制御用基板である。従って、電極(B)の短手方向の幅広部は、長手方向中央部に形成されるので、電極(B)の部分では、はんだ溜りは長手方向中央部に形成される。   According to a sixth aspect of the present invention, in the electrode (B), the maximum width in the lateral direction is formed at the center in the longitudinal direction of the exposed portion of the substrate-side electrode. Substrate. Therefore, since the wide part in the short direction of the electrode (B) is formed in the central part in the longitudinal direction, the solder pool is formed in the central part in the longitudinal direction in the part of the electrode (B).

本発明の第7の態様は、前記基板側電極の表面が、Cu,Ag,Au,Sn,Ni,Ni/Au及びNi/Pd/Auからなる群から選択された金属で形成されていることを特徴とするはんだ堆積制御用基板である。   In a seventh aspect of the present invention, the surface of the substrate side electrode is formed of a metal selected from the group consisting of Cu, Ag, Au, Sn, Ni, Ni / Au, and Ni / Pd / Au. A solder deposition control board characterized by the following.

本発明の第8の態様は、前記基板側電極の表面に、さらに有機皮膜にて防錆処理が施されていることを特徴とするはんだ堆積制御用基板である。   According to an eighth aspect of the present invention, there is provided a solder deposition control substrate, wherein the surface of the substrate-side electrode is further subjected to rust prevention treatment with an organic film.

本発明の第1の態様によれば、短手方向を形成する電極幅は、短手方向の最小幅を形成する端部から連続的に広がっていく態様なので、短手方向の電極幅が狭い部分でも基板と電極との間の面積を確保できる。よって、基板側電極の基板への密着力が低下するのを抑えることができ、基板側電極・基板間の機械的信頼性が向上する。さらには、基板側電極・基板間の機械的信頼性が向上するので、短手方向における最小幅を更に小さくでき、更なる電極配列のファインピッチ化が可能となる。   According to the first aspect of the present invention, the width of the electrode that forms the short direction is a form that continuously spreads from the end that forms the minimum width in the short direction, so the electrode width in the short direction is narrow. Even in the portion, the area between the substrate and the electrode can be secured. Therefore, it can suppress that the adhesive force of the board | substrate side electrode to the board | substrate falls, and the mechanical reliability between a board | substrate side electrode and a board | substrate improves. Furthermore, since the mechanical reliability between the substrate-side electrode and the substrate is improved, the minimum width in the short direction can be further reduced, and a further fine pitch of the electrode arrangement can be achieved.

また、基板側電極の形状は、短手方向の最大幅を形成する端部から長手方向に進むにつれて短手方向の幅が連続的に狭まっていくので、隣接する他の電極とのスペースを確保することができ、ファインピッチ化しても短絡を防止できる。さらに、基板側電極は、短手方向の幅が連続的に広がるシンプルな形状なので、電極作製用マスクを製造する際に、電極形状に対応する座標データが少なくて済み、基板の製造が容易である。また、はんだ溜りは所定量電極幅の広がった特定位置に形成されるので、電子部品の接続用電極とはんだ溜りとの対向が容易となり、基板と電子部品との接続信頼性が向上する。   In addition, the shape of the substrate-side electrode is such that the width in the short direction continuously narrows from the end that forms the maximum width in the short direction in the longitudinal direction, thus ensuring space with other adjacent electrodes. It is possible to prevent a short circuit even if the pitch is fine. Furthermore, since the substrate-side electrode has a simple shape in which the width in the short-side direction continuously increases, when manufacturing an electrode manufacturing mask, less coordinate data corresponding to the electrode shape is required, and manufacturing of the substrate is easy. is there. Further, since the solder reservoir is formed at a specific position where the electrode width is increased by a predetermined amount, the connection between the electrode for connecting the electronic component and the solder reservoir is facilitated, and the connection reliability between the substrate and the electronic component is improved.

本発明の第2の態様によれば、電極広がり角度を0.5°〜10°にすることで、一定の位置に適量のはんだ溜りを形成させることができる。   According to the second aspect of the present invention, an appropriate amount of solder pool can be formed at a certain position by setting the electrode spreading angle to 0.5 ° to 10 °.

本発明の第3の態様によれば、電極広がり角度を1°〜3°に限定したので、はんだ溜りの位置の精度を向上させつつ、電極配列のファインピッチ化に対応することができる。また、長手方向を形成する両端部が同一の電極広がり角度を有するので、各電極間のスペースを均一にすることができ、短絡防止が容易となる。   According to the third aspect of the present invention, since the electrode spreading angle is limited to 1 ° to 3 °, it is possible to cope with the fine pitch of the electrode arrangement while improving the accuracy of the position of the solder pool. Further, since both end portions forming the longitudinal direction have the same electrode spreading angle, the space between the electrodes can be made uniform, and short circuit prevention is facilitated.

本発明の第4の態様によれば、短手方向における最大幅を形成する端部が交互に配置されるので、各電極間のスペース、特に、短手方向の幅広部間のスペースを確保することができることから、短絡を確実に防止しつつ、厳しいファインピッチ化にも対応することが可能となる。また、各電極間に十分なスペースがあるので、エッティングによる電極のパターニングを正確に行うことができる。   According to the fourth aspect of the present invention, since the end portions forming the maximum width in the short direction are alternately arranged, a space between the electrodes, particularly a space between the wide portions in the short direction is ensured. Therefore, it is possible to cope with severe fine pitch while reliably preventing a short circuit. In addition, since there is a sufficient space between the electrodes, it is possible to accurately perform electrode patterning by etching.

本発明の第5の態様によれば、短手方向の幅広部を長手方向中央部よりに形成した電極(B)が、更に配置されるので、ファインピッチ化された電子部品の接続用電極について、その一部が特定の位置からずれていても、基板側電極のはんだ溜りに対向した接続が可能となる。   According to the fifth aspect of the present invention, since the electrode (B) in which the wide portion in the short direction is formed from the central portion in the longitudinal direction is further arranged, the connection electrode for the electronic component having a fine pitch is provided. Even if a part thereof deviates from a specific position, the connection facing the solder pool of the substrate side electrode is possible.

本発明の第6の態様によれば、前記電極(B)は、長手方向中央部に短手方向の最大幅が形成されているので、電極間スペースの制御が容易であり、電極間の短絡を防止できる。   According to the sixth aspect of the present invention, since the electrode (B) has a maximum width in the short direction at the central portion in the longitudinal direction, the control of the space between the electrodes is easy, and the short circuit between the electrodes. Can be prevented.

本発明の第7の態様によれば、電極表面を上記金属とすることで、種々の電極表面処理への対応が可能となる。   According to the seventh aspect of the present invention, it is possible to cope with various electrode surface treatments by making the electrode surface the above metal.

本発明の第8の態様によれば、基板側電極の表面に防錆処理が施されているので、基板側電極からはんだ溜りが剥落するのを防止できる。   According to the eighth aspect of the present invention, since the surface of the substrate side electrode is subjected to rust prevention treatment, it is possible to prevent the solder pool from peeling off from the substrate side electrode.

本発明の第1実施形態例に係るはんだ堆積制御用基板の部分平面図である。It is a partial top view of the board | substrate for solder deposition control which concerns on the example of 1st Embodiment of this invention. 本発明の第2実施形態例に係るはんだ堆積制御用基板の部分平面図である。It is a partial top view of the board | substrate for solder deposition control which concerns on the 2nd Example of this invention. (a)図は、ソルダーレジスト開口部から露出した基板側電極の平面図、(b)図は、はんだプリコート時における基板側電極露出部の側面図である。(A) A figure is a top view of the board | substrate side electrode exposed from the soldering resist opening part, (b) A figure is a side view of the board | substrate side electrode exposure part at the time of solder precoat. 本発明の他の実施形態例に係るソルダーレジスト開口部から露出した基板側電極の平面図である。It is a top view of the board | substrate side electrode exposed from the soldering resist opening part which concerns on the other embodiment of this invention.

つぎに、本発明の実施形態例に係るはんだ堆積制御用基板を図面に基づいて説明する。図1は、第1実施形態例に係るはんだ堆積制御用基板の部分平面図、図2は、第2実施形態例に係るはんだ堆積制御用基板の部分平面図、図3(a)は、ソルダーレジスト開口部から露出した基板側電極の平面図、同(b)図は、はんだプリコート時における基板側電極の側面図、図4は、本発明の他の実施形態例に係るソルダーレジスト開口部から露出した基板側電極の平面図である。   Next, a solder deposition control substrate according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a partial plan view of a solder deposition control substrate according to the first embodiment, FIG. 2 is a partial plan view of a solder deposition control substrate according to the second embodiment, and FIG. The top view of the board | substrate side electrode exposed from the resist opening part, the same figure (b) is a side view of the board | substrate side electrode at the time of solder precoat, FIG. 4 is from the soldering resist opening part which concerns on the other embodiment of this invention. It is a top view of the exposed substrate side electrode.

第1実施形態例に係るはんだ堆積制御用基板1には、図1に示すように、その表面に同一形状かつ同一寸法の基板側電極2が同一の電極ピッチで複数個配列され、絶縁材であるソルダーレジスト3が、この基板側電極2を被覆している。ただし、はんだ堆積制御用基板1の周縁部には、長方形状のソルダーレジスト開口部4が形成されており、そこから、基板側電極2の一部が露出している。ソルダーレジスト開口部4の開口幅Wは、特に限定されないが、例えば、その下限値は、基板側電極2に塗布するはんだの容量を確保して接続信頼性を向上させるために150μmが好ましく、その上限値は、はんだの過剰供給による短絡を防止するために500μmが好ましく、特に、はんだ堆積制御用基板1の小型化のために200μmが好ましい。   As shown in FIG. 1, a plurality of substrate-side electrodes 2 having the same shape and the same dimensions are arranged on the surface of the solder deposition control substrate 1 according to the first embodiment at the same electrode pitch. A certain solder resist 3 covers the substrate side electrode 2. However, a rectangular solder resist opening 4 is formed at the peripheral edge of the solder deposition control substrate 1, and a part of the substrate-side electrode 2 is exposed therefrom. The opening width W of the solder resist opening 4 is not particularly limited. For example, the lower limit is preferably 150 μm in order to secure the capacity of the solder applied to the substrate side electrode 2 and improve the connection reliability. The upper limit is preferably 500 μm in order to prevent a short circuit due to excessive supply of solder, and particularly preferably 200 μm in order to reduce the size of the solder deposition control substrate 1.

基板側電極2は、例えば銅により形成されており、パターンエッティングにより所定のパターンにパターニングされている。本実施形態例では、基板側電極2は、基板外縁部に一定間隔にて配列されている。   The substrate side electrode 2 is made of copper, for example, and is patterned into a predetermined pattern by pattern etching. In this embodiment, the substrate side electrodes 2 are arranged at regular intervals on the outer edge of the substrate.

この基板側電極2は、電極幅W2である細長い矩形部6と、この矩形部6と連続して構成されている最大電極幅W1の台形部5とからなる。第1実施形態例では、基板側電極2は、全て、台形部5が基板周端部と対向するよう配列されている。この基板側電極2は、矩形部6及び台形部5の基板周縁側端部の近傍がソルダーレジスト3で被覆されている。一方、矩形部6と台形部5との境界部から台形部5にかけての部位は、ソルダーレジスト開口部4により外部に露出しており、電子部品との接続部7となっている。従って、ソルダーレジスト開口部に配列された接続部7は、同一形状かつ同一寸法であり、また、接続部7の長手方向の寸法はソルダーレジスト開口幅であるWとなり、接続部7の短手方向の最小幅は矩形部6の電極幅W2、短手方向の最大幅は台形部5の最大電極幅W1よりも若干狭いW1´となっている。   The substrate-side electrode 2 includes an elongated rectangular portion 6 having an electrode width W2 and a trapezoidal portion 5 having a maximum electrode width W1 that is formed continuously with the rectangular portion 6. In the first embodiment, all the substrate-side electrodes 2 are arranged so that the trapezoidal portion 5 faces the peripheral edge of the substrate. The substrate-side electrode 2 is covered with a solder resist 3 in the vicinity of the end portions on the peripheral edge side of the rectangular portion 6 and the trapezoidal portion 5. On the other hand, a portion from the boundary between the rectangular portion 6 and the trapezoidal portion 5 to the trapezoidal portion 5 is exposed to the outside through the solder resist opening 4 and serves as a connection portion 7 with an electronic component. Accordingly, the connecting portions 7 arranged in the solder resist opening have the same shape and the same dimensions, and the length in the longitudinal direction of the connecting portion 7 is W, which is the solder resist opening width, and the width of the connecting portion 7 is short. Is the electrode width W2 of the rectangular portion 6, and the maximum width in the short direction is W1 ′ slightly narrower than the maximum electrode width W1 of the trapezoidal portion 5.

図1及び図3(a)に示すように、接続部7の長手方向を形成する両端部は、接続部7の短手方向の最小幅W2を形成する端部の法線方向に対して、所定の電極広がり角度8を有している。従って、接続部7の短手方向の電極幅は、基板周端部に向かってW2からW1´へと徐々に広がっていく構成となり、基板側電極2相互間のスペースは基板中央部に向かって徐々に広がっていく構成となっている。電極幅W2は、特に限定されないが、エッティング精度及び基板側電極2の間隔の微細化の点から、例えば20〜50μmである。   As shown in FIGS. 1 and 3 (a), both end portions forming the longitudinal direction of the connecting portion 7 are in the normal direction of the end portion forming the minimum width W2 of the connecting portion 7 in the short direction. A predetermined electrode spread angle 8 is provided. Accordingly, the electrode width in the short direction of the connecting portion 7 is configured to gradually widen from W2 to W1 ′ toward the peripheral edge of the substrate, and the space between the substrate side electrodes 2 is directed toward the center of the substrate. It is structured to gradually spread. The electrode width W2 is not particularly limited, but is, for example, 20 to 50 μm from the viewpoints of etching accuracy and miniaturization of the distance between the substrate-side electrodes 2.

図3(a)に示すように、本実施形態例では、接続部7の長手方向を形成する両端部は、ともに同じ電極広がり角度8を有している。電極広がり角度8は特に限定されないが、その下限値は、エッティング精度の点から0.5°が好ましく、長手方向の端部を精度よく傾斜させて確実に一定の位置に後述するはんだ溜り9を形成させる点から1.0°が特に好ましい。また、上限値は、はんだ溜り9の位置精度の点から10°が好ましく、基板側電極2配列のファインピッチ化の点から3.0°が特に好ましい。   As shown in FIG. 3A, in the present embodiment example, both end portions forming the longitudinal direction of the connecting portion 7 have the same electrode spreading angle 8. The electrode spreading angle 8 is not particularly limited, but the lower limit is preferably 0.5 ° from the viewpoint of the etching accuracy, and the solder reservoir 9 described later is surely placed at a certain position by accurately inclining the end in the longitudinal direction. The angle of 1.0 ° is particularly preferable from the viewpoint of forming. Further, the upper limit is preferably 10 ° from the viewpoint of the positional accuracy of the solder reservoir 9, and particularly preferably 3.0 ° from the viewpoint of fine pitching of the substrate side electrode 2 array.

つぎに、本実施形態例のはんだプリコート方法を説明する。基板側電極2上に、例えば、はんだペーストを印刷方法にて、ソルダーレジスト開口部4に供給後、はんだを加熱溶融して液状化させる。すると、形状の大きい液滴の方が内部圧力が低いので、液状化したはんだは大きい液滴へと集まって行き、図3(b)に示すように、基板側電極2の接続部7上にはんだ溜り9が形成される。このとき、溶融はんだの表面張力と溶融はんだが基板側電極2上を濡れ広がろうとする力とのバランスから、短手方向の電極幅が所定幅広がった特定位置に、はんだ溜り9が形成される。従って、はんだ溜り9は、はんだ堆積制御用基板1上を一定間隔で略一直線状に配列される。一方で、はんだ溜り9が形成された位置よりも短手方向の電極幅が狭い部位には、はんだの薄膜10が形成される。   Next, a solder pre-coating method according to this embodiment will be described. On the substrate side electrode 2, for example, a solder paste is supplied to the solder resist opening 4 by a printing method, and then the solder is heated and melted to be liquefied. Then, since the large-sized droplet has a lower internal pressure, the liquefied solder gathers into the large droplet, and as shown in FIG. 3B, on the connection portion 7 of the substrate-side electrode 2. A solder pool 9 is formed. At this time, the solder pool 9 is formed at a specific position where the width of the electrode in the short direction is widened from the balance between the surface tension of the molten solder and the force with which the molten solder wets and spreads on the substrate-side electrode 2. The Therefore, the solder pools 9 are arranged in a substantially straight line at regular intervals on the solder deposition control substrate 1. On the other hand, a solder thin film 10 is formed at a portion where the electrode width in the short direction is narrower than the position where the solder pool 9 is formed.

基板側電極2配列のピッチ間隔は、特に限定されず、ソルダーレジスト開口幅W、電極広がり角度8、電極幅W2などに応じて適宜設定可能である。ただし、電子部品の接合時にはんだ溜り9が接続部7からはみ出ることによる基板側電極2間の短絡を防止するためには、接続部7の短手方向の両端部のうち、電極幅W1´の端部間の間隔を25μm以上とするのが好ましく、従って、電極ピッチの微細化に対応するためには50〜60μmの電極ピッチを確保するのが好ましい。   The pitch interval of the substrate-side electrode 2 array is not particularly limited, and can be appropriately set according to the solder resist opening width W, the electrode spreading angle 8, the electrode width W2, and the like. However, in order to prevent a short circuit between the substrate-side electrodes 2 due to the solder pool 9 protruding from the connection portion 7 when the electronic components are joined, the electrode width W1 ′ of both ends in the short direction of the connection portion 7 is reduced. The distance between the end portions is preferably 25 μm or more. Therefore, it is preferable to secure an electrode pitch of 50 to 60 μm in order to cope with the miniaturization of the electrode pitch.

つぎに、本発明の第2実施形態例について説明する。第2実施形態例に係るはんだ堆積制御用基板31は、隣接する基板側電極32間の配置関係の点で、第1実施形態例に係るはんだ堆積制御用基板1と相違する。以下、詳細に説明する。   Next, a second embodiment of the present invention will be described. The solder deposition control substrate 31 according to the second embodiment is different from the solder deposition control substrate 1 according to the first embodiment in the arrangement relationship between adjacent substrate-side electrodes 32. Details will be described below.

図2に示すように、第2実施形態例に係るはんだ堆積制御用基板31は、その表面に基板側電極32が、規則的に複数配列されている。基板側電極32は、電極幅W2である細長い矩形部36と、この矩形部36と連続して構成されている最大電極幅W1の台形部35とからなる。第2実施形態例では、基板側電極32は、その台形部35と矩形部36が交互に配置されるようになっている。つまり、基板側電極32は、台形部35と矩形部36とが交互に基板周端部と対向する配置となっている。   As shown in FIG. 2, the solder deposition control substrate 31 according to the second embodiment has a plurality of substrate-side electrodes 32 regularly arranged on the surface thereof. The substrate-side electrode 32 includes an elongated rectangular portion 36 having an electrode width W2 and a trapezoidal portion 35 having a maximum electrode width W1 that is formed continuously with the rectangular portion 36. In the second embodiment, the substrate-side electrode 32 has its trapezoidal portions 35 and rectangular portions 36 arranged alternately. That is, the substrate-side electrode 32 is arranged such that the trapezoidal portions 35 and the rectangular portions 36 are alternately opposed to the peripheral edge of the substrate.

第2実施形態例も、絶縁材であるソルダーレジスト33が、基板側電極32を被覆しているが、はんだ堆積制御用基板30の周縁部には、上記第1実施形態例と同様の構成にて、長方形状のソルダーレジスト開口部34が形成され、そこから、基板側電極32の一部が露出している。従って、ソルダーレジスト開口部には、同一形状かつ同一寸法の接続部37が配列されており、また、接続部37の短手方向の最小幅は矩形部36の電極幅W2となり、最大幅は台形部35の最大電極幅W1よりも若干狭いW1´となっている。   In the second embodiment as well, the solder resist 33, which is an insulating material, covers the substrate-side electrode 32, but the peripheral portion of the solder deposition control substrate 30 has the same configuration as the first embodiment. Thus, a rectangular solder resist opening 34 is formed, from which a part of the substrate-side electrode 32 is exposed. Accordingly, the connection portions 37 having the same shape and the same dimensions are arranged in the solder resist opening, and the minimum width in the short direction of the connection portion 37 is the electrode width W2 of the rectangular portion 36, and the maximum width is a trapezoid. W1 'is slightly narrower than the maximum electrode width W1 of the portion 35.

図2及び図3(a)に示すように、接続部37の長手方向を形成する両端部は、接続部37の短手方向の最小幅W2を形成する端部の法線方向に対して、所定の電極広がり角度38を有している。従って、接続部37の短手方向の電極幅は、W2からW1´へと連続的に徐々に広がっていく構成となっている。   As shown in FIGS. 2 and 3 (a), both ends forming the longitudinal direction of the connecting portion 37 are in the normal direction of the end portion forming the minimum width W2 of the connecting portion 37 in the short direction. A predetermined electrode spread angle 38 is provided. Accordingly, the electrode width in the short direction of the connecting portion 37 is configured to gradually and gradually expand from W2 to W1 ′.

図2に示すように、本実施形態例でも、接続部37の長手方向を形成する両端部はともに所定の電極広がり角度38を有し、かつその角度も同一となっている。一方で、電極幅W1´を有する接続部37の端部と電極幅W2を有する接続部37の端部とが、基板周端部に対し交互に対向するよう配置されているので、はんだ溜り9は千鳥状に形成されることになる。また、隣接する基板側電極32相互間のスペースは、長手方向に沿って均一な構成となっているので、第1実施形態例と比較して、基板側電極32の間隔を(W1−W2)/2は詰めることができる。実際には、上記の通り、はんだ溜り9の配列は直線状ではなく千鳥状なので、電子部品接合時の電極間の短絡を抑えることができることから、基板側電極32の間隔を(W1−W2)/2以上詰めることも可能である。   As shown in FIG. 2, also in this embodiment, both end portions forming the longitudinal direction of the connecting portion 37 have a predetermined electrode spreading angle 38, and the angles are also the same. On the other hand, since the end portion of the connection portion 37 having the electrode width W1 ′ and the end portion of the connection portion 37 having the electrode width W2 are arranged so as to alternately oppose the peripheral edge portion of the substrate, the solder pool 9 Will be formed in a staggered pattern. Further, since the space between the adjacent substrate-side electrodes 32 is uniform along the longitudinal direction, the distance between the substrate-side electrodes 32 is (W1-W2) compared to the first embodiment. / 2 can be packed. Actually, as described above, the arrangement of the solder reservoirs 9 is not a straight line but a staggered pattern, so that it is possible to suppress a short circuit between the electrodes when joining the electronic components. / 2 or more can be packed.

第2実施形態例でも、電極広がり角度38は特に限定されないが、その下限値は、エッティング精度の点から0.5°が好ましく、長手方向の端部を精度よく傾斜させて確実に特定の位置にはんだ溜りを形成させる点から1.0°が特に好ましい。また上限値は、はんだ供給過多による短絡を防止する点から10°が好ましく、基板側電極32配列のファインピッチ化の点から3.0°が特に好ましい。   Also in the second embodiment, the electrode spread angle 38 is not particularly limited, but the lower limit is preferably 0.5 ° from the viewpoint of the etching accuracy, and the end portion in the longitudinal direction is inclined with high accuracy to ensure a specific value. From the point of forming a solder pool at the position, 1.0 ° is particularly preferable. The upper limit is preferably 10 ° from the viewpoint of preventing short circuit due to excessive supply of solder, and particularly preferably 3.0 ° from the viewpoint of fine pitching of the substrate side electrode 32 array.

つぎに、本発明の他の実施形態例を説明する。上記実施形態例では、接続部7、37の長手方向を形成する両端部は、ともに同じ電極広がり角度8、38を有していたが、電極広がり角度8、38は同一でなくてもよく、また、どちらか一方の端部のみ電極広がり角度8、38を有していてもよい。また、接続部7、37が配列しているソルダーレジスト開口部4、34の位置は基板外縁部に限定されず、基板中央部などでもよく、また、電極ピッチは一定でなくてもよい。   Next, another embodiment of the present invention will be described. In the above embodiment example, both end portions forming the longitudinal direction of the connecting portions 7 and 37 have the same electrode spread angles 8 and 38, but the electrode spread angles 8 and 38 may not be the same, Further, only one of the end portions may have electrode spreading angles 8 and 38. Further, the positions of the solder resist openings 4 and 34 in which the connecting portions 7 and 37 are arranged are not limited to the outer edge of the substrate, but may be the central portion of the substrate, and the electrode pitch may not be constant.

上記実施形態例では、各基板側電極2、32の接続部7、37は、全て、同一形状、同一寸法であったが、形状、寸法は基板側電極2、32の接続部7、37ごとに異なっていてもよく、例えば、電極広がり角度8、38の異なる基板側電極2、32を配列させてもよい。また、上記実施形態例の基板側電極2、32では、いずれも、接続部7、37の端部が短手方向の最大幅を有していたが、図4に示すように、前記接続部7、37の配列中に、さらに、端部以外の部位で接続部の短手方向における最大幅が形成された接続部40を適宜配置してもよい。また、上記「端部以外の部位」とは、接続部の長手方向中央部でも長手方向周縁部でもよい。   In the above embodiment example, all the connection portions 7 and 37 of the substrate side electrodes 2 and 32 have the same shape and the same size, but the shape and dimensions are the same as the connection portions 7 and 37 of the substrate side electrodes 2 and 32. For example, the substrate-side electrodes 2 and 32 having different electrode spreading angles 8 and 38 may be arranged. Further, in the substrate side electrodes 2 and 32 of the above-described embodiment example, the end portions of the connection portions 7 and 37 have the maximum width in the short direction, but as shown in FIG. In addition, in the arrangement of 7 and 37, the connecting portion 40 in which the maximum width in the short direction of the connecting portion is formed in a portion other than the end portion may be appropriately arranged. Further, the “part other than the end portion” may be a central portion in the longitudinal direction of the connection portion or a peripheral portion in the longitudinal direction.

また、上記実施形態例では、各基板側電極2、32はCuにより形成されていたが、少なくともその表面が、Cu,Ag,Au,Sn,Ni,Ni/AuまたはNi/Pd/Auで形成されていてもよく、さらに基板側電極2、32表面に有機皮膜にて防錆処理が施されていてもよい。   In the above embodiment, each of the substrate side electrodes 2 and 32 is made of Cu, but at least the surface thereof is made of Cu, Ag, Au, Sn, Ni, Ni / Au or Ni / Pd / Au. Further, the surface of the substrate side electrodes 2 and 32 may be subjected to an antirust treatment with an organic film.

[実施例1]
はんだプリコートした基板の作製
厚み9μmの銅箔を被覆した縦40mm×横40mm×厚さ0.6mmのFR4基板に、パターンエッティングにより電極配列を基板外縁部に形成した。電極配列を構成するそれぞれの電極は、矩形部と台形部とからなり、同一形状かつ同一寸法とした。矩形部の寸法は、幅40μm×長さ300μmとし、台形部の長手方向の寸法は220μmとした。電極配列は、電極広がり角度0°〜3°では80μmピッチ、6°〜11°では160μmピッチとし、基板上に形成させた全電極数は、80μmピッチの場合は124個、160μmピッチの場合は62個とした。上記実施形態例1と同様に、全ての電極について、その台形部が基板周端部と対向する向きに規則的に配列させた。それぞれの電極について、台形部の長手方向を形成する両端部の電極広がり角度は、ともに同一とした。また、各FR4基板の電極が有する電極広がり角度は、おのおの0°、0.5°、1°、2°、3°、6°、8°、10°、11°とした。
[Example 1]
Preparation of Solder Precoated Substrate An electrode array was formed on the outer edge of the substrate by pattern etching on a FR4 substrate having a length of 40 mm, a width of 40 mm, and a thickness of 0.6 mm coated with a 9 μm thick copper foil. Each electrode constituting the electrode array was composed of a rectangular part and a trapezoidal part, and had the same shape and the same dimensions. The dimensions of the rectangular part were 40 μm width × 300 μm length, and the longitudinal dimension of the trapezoidal part was 220 μm. The electrode arrangement is 80 μm pitch when the electrode spread angle is 0 ° to 3 °, and 160 μm pitch when the angle is 6 ° to 11 °. The total number of electrodes formed on the substrate is 124 when the pitch is 80 μm and when the pitch is 160 μm. The number was 62. As in the first embodiment, all the electrodes were regularly arranged in a direction in which the trapezoidal portion faces the peripheral edge of the substrate. About each electrode, the electrode spreading angle of the both ends which form the longitudinal direction of a trapezoid part was made the same. The electrode spreading angles of the electrodes of each FR4 substrate were 0 °, 0.5 °, 1 °, 2 °, 3 °, 6 °, 8 °, 10 °, and 11 °, respectively.

実施形態例1と同様に、上記各電極広がり角度を有する電極配列を形成したおのおののFR4基板に、ソルダーレジスト開口部内から同一形状・同一寸法である台形部の一部が露出して接続部の配列が形成されるように、ソルダーレジストを塗布し(ソルダーレジストの厚さは25μm)、露光・現像・熱硬化の工程を経て、ソルダーレジスト開口幅200μm×10000μmを有する試験材を作成した。従って、接続部の長手方向の幅は200μmとなり、接続部の短手方向の最小幅は、ソルダーレジスト開口部の端部に位置しており、その幅は矩形部の幅である40μmとなる。作成した各試験材は、前記9種の電極広がり角度に応じて試験材1〜9とした。つぎに、ソルダーレジスト開口部から露出した電極配列に、ビヒクルとはんだ粉を混合して作製したはんだ粉含有量40質量%のはんだペーストを、厚さ30μmのメタルマスクを用いた印刷方法にて供給した。その後、FR4基板をピーク温度250℃のリフロー炉に通して、電極上にはんだプリコート層を形成した。電極上に形成したはんだ溜りの位置は、接続部の短手方向最大幅の端部からはんだ溜り中央部までの距離を顕微鏡で観察することにより測定した。   As in Embodiment 1, a part of the trapezoidal part having the same shape and the same size is exposed from the inside of the solder resist opening to each FR4 substrate in which the electrode array having each electrode spreading angle is formed, and the connection part A solder resist was applied so that the array was formed (the thickness of the solder resist was 25 μm), and a test material having a solder resist opening width of 200 μm × 10000 μm was prepared through the steps of exposure, development, and thermosetting. Therefore, the width in the longitudinal direction of the connecting portion is 200 μm, and the minimum width in the short direction of the connecting portion is located at the end of the solder resist opening, and the width is 40 μm, which is the width of the rectangular portion. Each created test material was made into the test materials 1-9 according to the said 9 types of electrode spreading angles. Next, a solder paste having a solder powder content of 40% by mass prepared by mixing a vehicle and solder powder is supplied to the electrode array exposed from the opening of the solder resist by a printing method using a metal mask having a thickness of 30 μm. did. Thereafter, the FR4 substrate was passed through a reflow furnace having a peak temperature of 250 ° C. to form a solder precoat layer on the electrode. The position of the solder pool formed on the electrode was measured by observing the distance from the edge of the maximum width in the short direction of the connecting portion to the center of the solder pool with a microscope.

はんだ溜りの評価
顕微鏡観察の結果、全ての電極にはんだ溜りが形成していた。電極広がり角度とはんだ溜りの位置との関係については表1に示す。表1中、はんだ溜り位置とは、ソルダーレジスト開口幅200μmを1とした場合の、接続部の短手方向最大幅の端部からはんだ溜り中央部までの距離、つまり、接続部の短手方向最大幅の端部からはんだ溜り中央部までの距離A(μm)を200で除した値を意味する。また、はんだ溜り位置の平均値は、全はんだ溜りを対象に算出した。
Evaluation of solder pool As a result of microscopic observation, solder pools were formed on all electrodes. Table 1 shows the relationship between the electrode spreading angle and the position of the solder pool. In Table 1, the solder pool position is the distance from the edge of the maximum width in the short direction of the connecting portion to the center of the solder pool when the solder resist opening width of 200 μm is 1, that is, the short direction of the connecting portion. It means a value obtained by dividing the distance A (μm) from the end of the maximum width to the center of the solder pool by 200. Moreover, the average value of the solder pool position was calculated for all solder pools.

Figure 2010225851
Figure 2010225851

表1より、電極広がり角度が0.5°〜10°の場合に、電極広がり角度が0°の試験材と比べて、はんだ溜り位置の標準偏差が1/5以下に抑えられており、はんだ溜り位置のばらつきが著しく低減した。特に、1°〜3°では、標準偏差が1/20程度に抑えられ、はんだ溜り位置の制御能に特に優れていた。電極広がり角度が11°の場合も、はんだ溜りを形成できたが、その位置精度は若干劣っていた。なお、上記0.5°〜10°の各電極広がり角度を有する電極配列には、いずれも、電極間の短絡及び短手方向最小幅近傍を含めた電極剥離の現象は認められなかった。   From Table 1, when the electrode spread angle is 0.5 ° to 10 °, the standard deviation of the solder pool position is suppressed to 1/5 or less compared to the test material having the electrode spread angle of 0 °. The dispersion of the reservoir position was remarkably reduced. In particular, at 1 ° to 3 °, the standard deviation was suppressed to about 1/20, and the solder pool position control ability was particularly excellent. Even when the electrode spreading angle was 11 °, a solder pool could be formed, but the positional accuracy was slightly inferior. In any of the electrode arrays having the electrode spreading angles of 0.5 ° to 10 °, no electrode peeling phenomenon including short-circuiting between electrodes and the vicinity of the minimum width in the short direction was observed.

[実施例2]
電極広がり角度がおのおの1°、2°である各FR4基板について、その電極配列のピッチを160μmとする以外は実施例1と同一構成のFR4基板(それぞれ試験材10、11とする)に、はんだ粉含有量60質量%のはんだペーストを、厚さ50μmであって開口率が実施例1の2倍であるメタルマスクを用いた印刷方法にて供給することで、はんだ供給量を実施例1の約4倍とした。その後、このFR4基板をピーク温度250℃のリフロー炉に通して、電極上にはんだプリコート層を形成した。電極広がり角度とはんだ溜りの位置との関係を表2に示す。
[Example 2]
For each FR4 substrate having an electrode spreading angle of 1 ° and 2 °, solder the FR4 substrate having the same configuration as that of Example 1 (referred to as test materials 10 and 11 respectively) except that the electrode arrangement pitch is 160 μm. By supplying a solder paste having a powder content of 60 mass% by a printing method using a metal mask having a thickness of 50 μm and an aperture ratio twice that of Example 1, the amount of solder supplied is that of Example 1. About 4 times. Thereafter, the FR4 substrate was passed through a reflow furnace having a peak temperature of 250 ° C. to form a solder precoat layer on the electrode. Table 2 shows the relationship between the electrode spreading angle and the position of the solder pool.

Figure 2010225851
Figure 2010225851

表2より、はんだ供給量を増やしても、全ての電極にはんだ溜りが形成され、はんだ溜りを一定の位置に制御することができた。また、はんだ供給量を増やすと、はんだ溜りは電極幅の狭まった側に移動することが判明した。従って、はんだ供給量を調節することにより、はんだ溜り位置を調整することが可能である。   From Table 2, even if the solder supply amount was increased, solder pools were formed on all the electrodes, and the solder pools could be controlled at a certain position. It was also found that when the amount of solder supplied was increased, the solder pool moved to the side where the electrode width was narrowed. Therefore, it is possible to adjust the solder pool position by adjusting the solder supply amount.

電極が基板から剥離しにくく、電極のファインピッチ化にも対応可能であり、電極間のショートも起こさないので、フリップチップ実装基板の分野で利用価値が高い。   Since the electrodes are difficult to peel off from the substrate, the electrodes can be made finer, and no short circuit occurs between the electrodes, which is highly useful in the field of flip chip mounting substrates.

1、31 はんだ堆積制御用基板
2、32 基板側電極
3、33 ソルダーレジスト
4、34 ソルダーレジスト開口部
5、35 台形部
6、36 矩形部
8、38 電極広がり角度
DESCRIPTION OF SYMBOLS 1,31 Board | substrate for solder deposition control 2,32 Board | substrate side electrode 3,33 Solder resist 4,34 Solder resist opening part 5,35 Trapezoid part 6,36 Rectangular part 8,38 Electrode spreading angle

Claims (8)

基板上に形成されたソルダーレジスト開口部からその一部が露出した基板側電極の配列に、電子部品の接続用電極を、はんだを介してフリップチップ実装するはんだ堆積制御用基板であって、
前記基板側電極の露出部の端部のうち、長手方向を形成する両端部のうちの少なくとも一方が、所定の電極広がり角度で傾斜し、前記基板側電極の露出部の端部のうち、短手方向を形成する両端部の一端が前記基板側電極の露出部の短手方向における最大幅を形成し、他端が前記基板側電極の露出部の短手方向における最小幅を形成することを特徴とするはんだ堆積制御用基板。
A solder deposition control board that flip-chip-mounts connection electrodes for electronic components via solder on an array of board-side electrodes, part of which is exposed from a solder resist opening formed on the board,
Of the end portions of the exposed portion of the substrate side electrode, at least one of both end portions forming the longitudinal direction is inclined at a predetermined electrode spreading angle, and the end portion of the exposed portion of the substrate side electrode is short. One end of both end portions forming the hand direction forms a maximum width in the short direction of the exposed portion of the substrate side electrode, and the other end forms a minimum width in the short direction of the exposed portion of the substrate side electrode. A board for solder deposition control.
前記電極広がり角度が、0.5°から10°であることを特徴とする請求項1に記載のはんだ堆積制御用基板。   The solder deposition control substrate according to claim 1, wherein the electrode spreading angle is 0.5 ° to 10 °. 前記長手方向を形成する両端部が、同一の前記電極広がり角度で傾斜しており、前記電極広がり角度が、1°から3°であることを特徴とする請求項1に記載のはんだ堆積制御用基板。   2. The solder deposition control according to claim 1, wherein both end portions forming the longitudinal direction are inclined at the same electrode spreading angle, and the electrode spreading angle is 1 ° to 3 °. substrate. 前記短手方向における最大幅を形成する端部と、前記短手方向における最小幅を形成する端部とが、交互に配列されていることを特徴とする請求項1に記載のはんだ堆積制御用基板。   2. The solder deposition control according to claim 1, wherein an end portion that forms a maximum width in the short-side direction and an end portion that forms a minimum width in the short-side direction are alternately arranged. substrate. 前記長手方向を形成する両端部のうちの少なくとも一方が所定の前記電極広がり角度で傾斜し、かつ前記短手方向の端部以外の部位で前記基板側電極の露出部の前記短手方向における最大幅を形成する電極が、更に配置されていることを特徴とする請求項1または4に記載のはんだ堆積制御用基板。   At least one of both end portions forming the longitudinal direction is inclined at a predetermined electrode spreading angle, and the exposed portion of the substrate-side electrode is the outermost portion in the short direction at a portion other than the end portion in the short direction. The solder deposition control substrate according to claim 1, wherein an electrode forming a large portion is further arranged. 前記短手方向における最大幅が、前記基板側電極の露出部の長手方向中央部に形成されていることを特徴とする請求項5に記載のはんだ堆積制御用基板。   6. The solder deposition control substrate according to claim 5, wherein the maximum width in the lateral direction is formed at a central portion in the longitudinal direction of the exposed portion of the substrate-side electrode. 前記基板側電極の表面が、Cu,Ag,Au,Sn,Ni,Ni/Au及びNi/Pd/Auからなる群から選択された金属で形成されていることを特徴とする請求項1に記載のはんだ堆積制御用基板。   The surface of the substrate side electrode is formed of a metal selected from the group consisting of Cu, Ag, Au, Sn, Ni, Ni / Au, and Ni / Pd / Au. PCB for solder deposition control. 前記基板側電極の表面に、さらに有機皮膜にて防錆処理が施されていることを特徴とする請求項7に記載のはんだ堆積制御用基板。   The solder deposition control substrate according to claim 7, wherein the surface of the substrate-side electrode is further subjected to rust prevention treatment with an organic film.
JP2009071552A 2009-03-24 2009-03-24 Substrate for controlling solder deposition Pending JP2010225851A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012119361A (en) * 2010-11-29 2012-06-21 Kyocer Slc Technologies Corp Wiring board
JP2014068015A (en) * 2012-09-25 2014-04-17 Samsung Electronics Co Ltd Bump structures, electrical connection structures, and methods of forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147620A (en) * 2004-11-16 2006-06-08 Toshiba Corp Method of manufacturing flip chip mounting semiconductor device, and flip chip mounting semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147620A (en) * 2004-11-16 2006-06-08 Toshiba Corp Method of manufacturing flip chip mounting semiconductor device, and flip chip mounting semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012119361A (en) * 2010-11-29 2012-06-21 Kyocer Slc Technologies Corp Wiring board
JP2014068015A (en) * 2012-09-25 2014-04-17 Samsung Electronics Co Ltd Bump structures, electrical connection structures, and methods of forming the same

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