JP2010225686A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain the high performance and high reliability of a semiconductor device which has a channel of SiGe. <P>SOLUTION: The semiconductor device includes: an element formation region 103 which is provided on one principal surface of a semiconductor substrate 101 which is mainly composed of silicon and defined by an element isolation insulating film 102, a semiconductor film 104 which is mainly composed of Si and Ge serving as a channel region and formed on the element formation region 103, a gate electrode 106 which is provided on the semiconductor film 104 through the gate insulating film 105, an S/D region 110 which is formed in the semiconductor film 104 and the substrate 101 across the channel region, a sidewall insulating film 109 which is formed on both side surfaces of the gate electrode 106, and a metal compound film 111 which is formed by making the semiconductor film 104 react with a metal, on the S/D contact region defined by the sidewall insulating film 109 on the S/D region 110, and has a film thickness thinner than that of the semiconductor films 104 except the S/D contact region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a MOSFET, and more particularly to a semiconductor device having a SiGe channel and a manufacturing method thereof.

  In recent years, semiconductor devices such as MOSFETs have been miniaturized, and ultra-miniaturized / high-speed FETs having a gate length of less than 65 nm have been realized. In such an ultra-miniaturized / high-speed FET, the area of the channel region immediately below the gate electrode is very small compared to the conventional FET. For this reason, the mobility of electrons or holes traveling in the channel region is greatly affected by the stress applied to the channel region.

  Therefore, recently, many attempts have been made to improve the operation speed of the FET by optimizing the stress applied to the channel region. For example, in the technique of forming a biaxial compression strained SiGe thin film in the channel region of the Si substrate, the hole mobility in the strained SiGe channel is increased, and the performance of the p-type FET can be improved.

  However, when the present inventors formed Ni silicide or NiPt alloy silicide in the source / drain contact region in order to achieve higher performance in a MOSFET having a strained SiGe channel, the characteristics deteriorated and the operation failed. It was found that good device characteristics could not be obtained.

JP 2001-1119026 A

  An object of the present invention is to provide a semiconductor device capable of achieving high performance and high reliability, such as a MOSFET having a SiGe channel, and a manufacturing method thereof.

  A semiconductor device according to one embodiment of the present invention is provided over one main surface of a semiconductor substrate containing silicon as a main component, and is formed over an element formation region partitioned by an element isolation insulating film and the element formation region A semiconductor film mainly composed of Si and Ge which becomes a channel region of a field effect transistor, a gate electrode provided on a part of the semiconductor film via a gate insulating film, and a channel region under the gate electrode A source / drain region provided on the semiconductor film and the substrate, a sidewall insulating film provided on both side surfaces of the gate electrode, and a source / drain partitioned by the sidewall insulating film on the source / drain region. The film thickness is formed on the drain contact region by the reaction of the semiconductor film and metal and is thinner than the semiconductor film other than the source / drain contact region. And a metal compound film formed, characterized by comprising comprises a.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an element isolation region on one main surface of a semiconductor substrate containing silicon as a main component so as to partition an element formation region; A step of epitaxially growing a semiconductor film mainly composed of Si and Ge, which serves as a channel region of a field effect transistor, on the element formation region; and a step of forming a gate electrode on a part of the semiconductor film via a gate insulating film Forming a sidewall insulating film on both side surfaces of the gate electrode, forming a source / drain region in the semiconductor film and the substrate with the gate electrode and the sidewall insulating film interposed therebetween, and the source / drain region Forming a metal film on the semiconductor film, and a metal comprising the metal film and the metal including Si and Ge by a reaction between the metal film and the semiconductor film. It includes a step of forming a compound film, and the film thickness of the semiconductor film, characterized by being larger than the thickness corresponding to the Si consumption in the formation of the metal compound film.

  According to the present invention, the metal compound film containing Si and Ge formed on the source / drain contact region is formed to be thinner than the film thickness of the semiconductor film, so that the high performance and high performance of the MOSFET having the SiGe channel can be achieved. Reliability can be achieved.

1 is a cross-sectional view showing an element structure of a p-channel MOSFET according to a first embodiment. Sectional drawing which shows the manufacturing process of p channel MOSFET concerning 1st Embodiment. Sectional drawing which shows the manufacturing process of p channel MOSFET concerning 1st Embodiment. Sectional drawing which shows the element structure process of p channel MOSFET concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of p channel MOSFET concerning 2nd Embodiment. Sectional drawing for demonstrating the problem at the time of forming a metal silicide on the source / drain contact area | region of MOSFET which has a SiGe channel.

  As described above, the present inventors formed Ni silicide or NiPt alloy silicide in the source / drain contact region in the MOSFET having the SiGe channel for the purpose of reducing the resistance of the source / drain region. The silicide is formed by forming a metal film (Ni or NiPt) having a thickness of about 8 to 12 nm on a SiGe thin film having a thickness of about 5 to 10 nm in the source / drain contact region, and then reacting the metal film with Si. Ni silicide or NiPt alloy silicide was formed.

  When Ni is used as the metal film, germanoid (NiGe) or mixed crystal film (NiSiGe) is actually formed in addition to the silicide (NiSi). The metal compound film formed by the reaction with the SiGe film can be substantially regarded as a metal silicide.

  FIG. 6 is a cross-sectional view showing the element structure of a MOSFET fabricated as described above. In the figure, 101 is a Si substrate, 102 is an element isolation insulating film, 103 is a p-type well diffusion layer region (element forming region), 104 is a SiGe thin film, 105 is a gate insulating film 105, 106 is a gate electrode, and 107 is a first electrode. 1 is a side wall insulating film, 108 is a source / drain extension layer, 109 is a second side wall insulating film, 110 is a source / drain region, and 111 is a metal silicide (metal compound film).

  As shown in FIG. 6, due to the difference in reaction rate and stability between Ni or NiPt alloy and Ge and Si, the morphological roughness of the silicide interface with irregularities (part A of broken line), under the gate sidewall of Ni silicide or NiPt alloy silicide Abnormal growth (part indicated by a broken line B) and further desilicide formation occurred. In such a structure, there is a concern about deterioration of fine FET characteristics and malfunction.

  The present embodiment has been made in consideration of the above circumstances, and the thickness of the SiGe thin film 104 is set so that the bottom of the metal compound film 111 does not reach the well diffusion layer region 103 even if the metal compound film 111 is formed. It is characterized by being thick. However, as the SiGe thin film 104 becomes thicker, the crystallinity decreases, so the upper limit is about 50 nm with a Ge composition of 30%. Therefore, even if the metal compound film 111 is formed in a range not exceeding this film thickness, the thickness of the SiGe thin film 104 is set so that the bottom of the metal compound film 111 does not reach the well diffusion layer region 103. What is necessary is just to make it thicker than the film thickness corresponding to Si consumption in formation of 111.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a sectional view showing an element structure of a p-channel MOSFET according to the first embodiment of the present invention.

In the figure, reference numeral 101 denotes a silicon substrate, and an element isolation insulating film 102 made of a silicon oxide film is surrounded by a surface portion of the substrate 101 so as to surround a p-type well diffusion layer region (element formation region) 103 serving as an element formation region. Is formed. On the element formation region 103, a SiGe thin film 104 having a thickness of 20 nm, which becomes a channel of the MOSFET, is formed. The SiGe thin film 104 is a Si _0.7 Ge _0.3 film having a Ge composition ratio of 30% and has a biaxial lattice strain.

A gate electrode 106 made of a polycrystalline silicon film is formed on a part of the SiGe thin film 104 via a gate insulating film 105 such as SiO ₂ , and side wall insulating films 107 and 109 are formed on the sides of the gate electrode 106. Yes.

  A source / drain extension layer 108 is formed in the SiGe thin film 104 and the element formation region 103 under the sidewall insulating films 107 and 109, and a source / drain region 110 is formed outside the source / drain extension layer 108.

A nickel silicide film (NixSi (1 ≦ x ≦ 2)) is formed as the metal compound film 111 on the gate electrode 106. On the exposed surface of the SiGe thin film 104, a nickel silicide film (NixSi (1 ≦ x ≦ 2)), a nickel germanide film (NixGe (1 ≦ x ≦ 2)) and a mixture thereof are formed as the metal compound film 111. Akiramaku _{(Ni x Si y Ge 1-} y (1 ≦ x ≦ 2)) is formed.

  2 and 3 are cross-sectional views showing the manufacturing process of the p-channel MOSFET 100 of this embodiment.

First, as shown in FIG. 2A, an element isolation insulating film 102 made of a silicon oxide film is formed on the surface portion of the silicon substrate 101. Subsequently, a p-type well diffusion layer region (element formation region) 103 is formed in a silicon region surrounded by 102 in the element isolation insulating film. Thereafter, a SiGe thin film 104 having a film thickness of 20 nm which becomes a channel of the MOSFET is epitaxially grown on the well diffusion layer region 103. Here, as the SiGe thin film 104 becomes thicker, the crystallinity decreases, so the upper limit of Si _0.7 Ge _{0.3 having} a Ge composition of 30% is about 50 nm. Further, the SiGe thin film 104 has a biaxial strain due to a difference in lattice constant from the underlying Si.

  Next, as shown in FIG. 2B, a silicon oxide film and a polycrystalline silicon film are sequentially deposited on the entire surface, and then the laminated structure film is patterned to form a gate electrode structure. That is, the gate insulating film 105 and the gate electrode 106 are formed. Subsequently, an offset spacer (first sidewall insulating film) 107 is formed by depositing a thin (about 2 to 10 nm) silicon oxide film and performing anisotropic etching such as RIE. Then, an impurity such as boron is implanted by an ion implantation technique, and high-temperature and short-time heat treatment such as RTA is performed, so that only the exposed surface of the SiGe thin film 104 and the element formation region 103 or the surface of the SiGe thin film 104 are p-type. A diffusion layer (source / drain extension region) 108 is formed.

  Next, as shown in FIG. 2C, after a silicon nitride film is deposited on the entire surface, anisotropic etching such as RIE is performed to form a silicon nitride film sidewall (second sidewall insulating film) 109. .

  Next, as shown in FIG. 3D, the surface of the SiGe thin film 104 and the element formation region 103 in which p-type impurities such as boron are exposed by an ion implantation technique using the gate electrode structure and the sidewall insulating films 107 and 109 as a mask. Type in. Subsequently, a p-type diffusion layer (source / drain region) 110 is formed on the exposed surface of the SiGe thin film 104 and the element formation region 103 by performing a high-temperature short-time heat treatment such as RTA.

  Next, as shown in FIG. 3E, for example, a nickel (Ni) film 112 is deposited on the entire surface as a metal for forming a silicide by about 8 nm by sputtering.

  Here, if the Ni film 112 is thin, it is formed non-uniformly like an island and causes deterioration of electrical characteristics. Therefore, the Ni film 112 needs to have a thickness of 6 nm or more. The Ni film 112 is about 1.8 times thicker due to silicidation, and 8 × 1.8 = 14.4 nm at 8 nm. Therefore, the thickness of the SiGe thin film 104 needs to be 15 nm or more so that the silicide portion does not reach the element formation region 103 due to silicidation of the Ni film 112 described later.

Next, RTA treatment at about 350 ° C. using a halogen lamp is performed, and the Ni film 112 is silicided. Specifically, the portion of the Ni film in contact with the surface of the polycrystalline gate electrode 106 and the exposed SiGe thin film 104 is reacted with Si and Ge. As a result, a nickel silicide film (Ni _x Si (1 ≦ x ≦ 2)) is formed on the polycrystalline gate electrode 106 as shown in FIG. On the other hand, on the exposed surface of the SiGe thin film 104, a nickel silicide film (Ni _x Si (1 ≦ x ≦ 2)), a nickel germanide film (Ni _x Ge (1 ≦ x ≦ 2)) and a mixed crystal thereof are formed. film _{(Ni x Si y Ge 1-} y (1 ≦ x ≦ 2)) is formed. At this time, the Ni film 112 deposited on the element isolation insulating film 102 and the film-side insulating film 109 does not change to silicide, germanide, or a mixed crystal film thereof.

  When Ni is used as the metal film, NiGe or NiSiGe is formed in addition to NiSi as described above. However, since most of the Ni is NiSi, the metal compound formed by the reaction between the Ni film and the SiGe film. The film can be substantially regarded as a NiSi film.

Next, the unreacted Ni film 112 is removed by etching using an etchant such as sulfuric acid / hydrogen peroxide solution or ammonia / hydrogen peroxide solution. At this time, the nickel silicide film (Ni _x Si), nickel germanide layer (Ni _x Ge) and mixed crystal layer _{(Ni x Si y Ge 1-} y) is remain intact because they are not etched in these etchants.

Subsequently, an RTA treatment at about 500 ° C. is performed, and a nickel silicide film (Ni _x Si), a nickel germanide film (Ni _x Ge) film and its mixed crystal film (Ni _x Si _y Ge _1-y ), Si Then, the reaction of Ge and Ge is further advanced to form a nickel monosilicide (NiSi), a nickel monogermanide (NiGe) film and a mixed crystal film (NiSi _y Ge _1-y ). As a result, a metal compound film 111 is formed on the gate electrode 106 and the SiGe thin film 104.

Thereafter, a nickel monosilicide (NiSi) film, a nickel monogermanide (NiGe) film and a mixed crystal film (NiSi _y Ge ₁₋ ) formed on the surface of the polycrystalline gate electrode 106 and the surface of the source / drain contact region 110. By forming the wiring layer connected to _y ), the transistor element is completed.

  As described above, according to the present embodiment, when the metal compound film 111 such as the silicide film, the germanide film, and the mixed crystal film thereof is formed on the source / drain region of the p-channel MOSFET, the silicon substrate 101 is not included and the SiGe film is not included. By performing silicidation and germanization only in the thin film 104, stable silicidation and germanization can be achieved. That is, when the thickness of the SiGe thin film 104 epitaxially grown in the channel region is made larger than the thickness corresponding to the amount of Si consumed in the formation of the metal compound film 111, the silicon substrate is formed when the metal compound film 111 is formed. Thus, silicidation and germanization can be performed only in the SiGe thin film 104.

  Therefore, stable silicidation and germanization can be achieved, the interface morphology between the silicide film, germanide film and its mixed crystal film and the SiGe thin film 104 is smoothed, and the silicide film, germanide film and its mixture under the side wall are smoothed. The submerged growth of the crystal film can be suppressed. As a result, a high-performance and highly reliable fine p-type MOSFET can be realized.

In addition, the Si _0.7 Ge _0.3 film with a high dopant activation rate is arranged at the interface between the silicide film, germanide film and its mixed crystal film and the substrate, so that the contact resistance can be reduced, and a highly reliable fine p-type. A MOSFET can be realized.

(Second Embodiment)
FIG. 4 is a sectional view showing an element structure process of a p-channel MOSFET according to the second embodiment of the present invention. Note that 201 to 211 in FIG. 2 correspond to 101 to 111 in FIG.

  The difference between this embodiment and the first embodiment described above is that the gate sidewall insulating film has three layers. That is, on the side surface of the gate structure portion, an offset spacer (first sidewall insulating film) 207 made of a silicon oxide film, a sidewall film (second sidewall insulating film) 209 made of a silicon nitride film, and a silicon oxide film are formed. A sidewall film (third sidewall insulating film) 215 is formed.

  FIGS. 5A to 5C are cross-sectional views showing a manufacturing process of a p-channel FET according to the second embodiment of the present invention.

  Until the gate electrode structure is manufactured, the process is the same as the process of FIGS. 2A to 2C of the first embodiment.

  2A, after forming a p-type well diffusion layer region (element formation region) 203 surrounded by the element isolation insulating film 202 on the surface portion of the silicon substrate 201, well diffusion is performed. A 20 nm-thickness SiGe thin film 204 is grown epitaxially on the surface of the layer region 203.

  Next, a polycrystalline silicon gate electrode 206 is formed through the gate insulating film 205 in the same manner as in FIG. 2C, after an offset spacer (first sidewall insulating film) 207 is formed on the side surface of the gate structure, a p-type diffusion layer (source / drain extension region) 108 is formed. Further, a silicon nitride film side wall (second side wall insulating film) 209 is formed.

  Next, as shown in FIG. 5A, after a silicon nitride film is deposited on the entire surface, anisotropic etching such as RIE is performed to form a silicon oxide film side wall (third side wall insulation) only on the side surface of the gate portion. Film) 215 is formed. Thereby, the gate length direction length as the whole side wall insulating film becomes long. Subsequently, a p-type impurity such as boron is implanted into the exposed surface of the SiGe thin film and the element formation region 203 by an ion implantation technique, and is subjected to high-temperature and short-time heat treatment such as RTA, thereby forming the exposed surface of the SiGe thin film 204 and the element formation. A p-type diffusion layer (source / drain region) 210 is formed in the region 203.

  Next, as shown in FIG. 5B, for example, a nickel (Ni) film 212 is deposited to a thickness of about 8 nm as a silicide forming metal on the entire surface. Then, an RTA process at about 350 ° C. using a halogen lamp is performed, and the Ni film 212 is silicided. Specifically, a portion of the Ni film in contact with the surface of the polycrystalline gate electrode 206 and the exposed SiGe thin film 204 is reacted with Si and Ge.

As a result, as shown in FIG. 5C, a nickel silicide film (Ni _x Si (1 ≦ x ≦ 2)) is formed on the polycrystalline gate electrode 206. On the exposed surface of the SiGe thin film 204, a nickel silicide film (Ni _x Si (1 ≦ x ≦ 2)), a nickel germanide film (Ni _x Ge (1 ≦ x ≦ 2)), and a mixed crystal film thereof ( Ni _x Si _y Ge _1-y (1 ≦ x ≦ 2)) is formed. On the other hand, the nickel film deposited on the element isolation insulating film 202 and the sidewall insulating film 215 does not change to silicide, germanide, or a mixed crystal film thereof.

Next, the unreacted Ni film is removed by etching using an etchant such as sulfuric acid / aqueous ammonia or aqueous ammonia. At this time, the nickel silicide film (Ni _x Si), nickel germanide layer (Ni _x Ge) and mixed crystal layer _{(Ni x Si y Ge 1-} y) is remain intact because they are not etched in these etchants.

Subsequently, an RTA treatment at about 500 ° C. is performed, and a nickel silicide film (Ni _x Si), a nickel germanide film (Ni _x Ge) film and its mixed crystal film (Ni _x Si _y Ge _1-y ), Si Then, the reaction of Ge and Ge is further advanced to form a nickel monosilicide (NiSi), a nickel monogermanide (NiGe) film and a mixed crystal film (NiSi _y Ge _1-y ).

Thereafter, a nickel monosilicide (NiSi) film, a nickel monogermanide (NiGe) film, and a mixed crystal film (NiSi _y Ge ₁ ) formed on the surface of the polycrystalline gate electrode 206 and the surface of the source / drain contact region 210. By forming a wiring layer connected to _-y ), the transistor element is completed.

  As described above, in this embodiment as well, as in the first embodiment, the thickness of the SiGe thin film 204 epitaxially grown in the channel region is larger than the thickness corresponding to the Si consumption amount in the formation of the metal compound film 211. By increasing the thickness, silicidation and germanization can be performed only in the SiGe thin film 204 without including the silicon substrate when the metal compound film 211 is formed. Therefore, the same effect as the first embodiment can be obtained.

  In the present embodiment, the formation of the third sidewall insulating film 215 can adjust the position of the gate-side boundary of the metal compound film 211 formed on the source / drain regions. That is, the gate side boundary of the metal compound film 211 can be further away from the channel side boundary of the source / drain region.

(Modification)
In addition, this invention is not limited to embodiment mentioned above. In the embodiment, Si _0.7 Ge _0.3 having a Ge composition of 30% is used as the SiGe thin film serving as the channel. However, the Ge composition can be appropriately changed according to the specifications. Further, the semiconductor film is not necessarily limited to SiGe but may be a semiconductor film containing Si and Ge as main components. For example, it is also possible to use a Si _1-x Ge _x where C (carbon) were mixed. Addition of C to the Si _1-x Ge _x channel suppresses impurity diffusion to the gate insulating film interface, improves Si _1-x Ge _x crystallinity (increases critical film thickness, suppresses dislocation growth), and further Stable silicidation / germanization is achieved and electrical properties are improved. A thin Si film may be epitaxially grown on Si _0.7 Ge _0.3 in order to improve the interface characteristics of the gate insulating film.

In the embodiment, a nickel film (Ni) is used as the silicide metal film. However, a nickel platinum alloy film (Ni _1-x Pt _x (0.02 <x <0.3) may be used. Here, the addition of Pt improves the thermal stability and crystallinity of Ni silicide, but Pt silicide has a higher specific resistance than Ni silicide, and therefore, if Pt is added excessively, the specific resistance of Ni silicide is increased. degrading the high becomes device performance. Therefore, the range of .Ni _1-x Pt _x of Pt composition x 0.02 <x <0.3 where it is necessary to set the optimum concentration depending on the device design If so, it is possible to avoid significant device characteristic deterioration in terms of physical properties while improving thermal stability and crystallinity.

  In the embodiment, the p-type MOSFET is taken as an example. However, it is also possible to apply to the n-type MOSFET by using the impurity type of the conductivity type opposite to that of the embodiment, and the photolithography process is performed. It is also possible to simultaneously form an n-type MOSFET and a p-type MOSFET on the same substrate.

  Further, in the embodiment, the semiconductor film having the lattice distortion of the semiconductor film constituting the channel is used, but it is also possible to use a semiconductor film having no distortion or relaxing the distortion. Further, the present invention is not necessarily limited to the MOSFET, but can be applied to a MISFET using an insulating film other than an oxide film as a gate insulating film.

  In addition, various modifications can be made without departing from the scope of the present invention.

101, 201 ... silicon substrate 102, 202 ... silicon oxide film 103, 203 ... n-type well diffusion layer region (element formation region)
104, 204 ... strained SiGe thin film 105, 205 ... gate insulating film 106, 206 ... polycrystalline polysilicon gate electrode 107, 207 ... silicon oxide film side wall (first side wall insulating film)
108, 208... P-type source / drain extension regions 109, 209, 211... Silicon nitride film side wall (second side wall insulating film)
110, 210... P-type source / drain regions 111, 212... Metal compound film 215... Silicon oxide film side wall (third side wall insulating film)

Claims (5)

An element formation region provided on one main surface of a semiconductor substrate mainly composed of silicon and partitioned by an element isolation insulating film;
A semiconductor film mainly composed of Si and Ge, which is a channel region of a field effect transistor provided on the element formation region;
A gate electrode provided on a part of the semiconductor film via a gate insulating film;
A source / drain region formed in the semiconductor film and the substrate across a channel region under the gate electrode;
Sidewall insulating films provided on both side surfaces of the gate electrode;
From the semiconductor film formed on the source / drain contact region defined by the sidewall insulating film on the source / drain region by a reaction between the semiconductor film and a metal and other than the source / drain contact region A metal compound film formed in a thin film thickness,
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the semiconductor film has lattice distortion.   The semiconductor device according to claim 1, wherein the metal in the metal compound film is Ni or a NiPt alloy. Forming an element isolation region so as to partition an element formation region on one main surface of a semiconductor substrate containing silicon as a main component;
A step of epitaxially growing a semiconductor film mainly composed of Si and Ge to be a channel region of a field effect transistor on the element formation region;
Forming a gate electrode on a part of the semiconductor film via a gate insulating film;
Forming a sidewall insulating film on both side surfaces of the gate electrode;
Forming source / drain regions in the semiconductor film and the substrate across the gate electrode and the sidewall insulating film;
Forming a metal film on the semiconductor film in the source / drain region;
Forming a metal compound film containing the metal and the Si and Ge by the reaction of the metal film and the semiconductor film; and
Have
A method of manufacturing a semiconductor device, characterized in that the thickness of the semiconductor film is made larger than the thickness corresponding to the amount of Si consumed in forming the metal compound film.   5. The semiconductor device according to claim 4, wherein the metal constituting the metal film is Ni or NiPt, and the film thickness of the semiconductor film is set to 1.8 times or more of the film thickness of the metal film. Method.

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