JP2010223600A - Semiconductor pressure sensor and method of manufacturing the same - Google Patents

Semiconductor pressure sensor and method of manufacturing the same Download PDF

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JP2010223600A
JP2010223600A JP2009068235A JP2009068235A JP2010223600A JP 2010223600 A JP2010223600 A JP 2010223600A JP 2009068235 A JP2009068235 A JP 2009068235A JP 2009068235 A JP2009068235 A JP 2009068235A JP 2010223600 A JP2010223600 A JP 2010223600A
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semiconductor substrate
semiconductor
capacitance
pressure sensor
substrate
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Ryosuke Meshii
良介 飯井
Koji Sakai
浩司 境
Sumihisa Fukuda
純久 福田
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Panasonic Electric Works Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor pressure sensor having a simple structure and manufacturable at low cost, and to provide a method of manufacturing the semiconductor pressure sensor. <P>SOLUTION: The semiconductor pressure sensor for detecting a pressure by a change in a capacitance includes: a first semiconductor substrate 1 to be one electrode of the capacitance; a second semiconductor substrate 2 which forms a diaphragm 7 of a pressure sensing part by being thinned and is to be the other electrode of the capacitance element; and a glass substrate 3 laminated between the first semiconductor substrate 1 and the second semiconductor substrate 2, and forming a space to be a capacitive gap of the capacitance between the first semiconductor substrate 1 and the second semiconductor substrate 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、外部から加わる圧力によるダイヤフラムのたわみを電気的に検出することで圧力を検出する半導体圧力センサ及びその製造方法に関する。   The present invention relates to a semiconductor pressure sensor that detects pressure by electrically detecting deflection of a diaphragm due to pressure applied from the outside, and a method for manufacturing the same.

従来、この種の技術としては、例えば以下に示す文献に記載されたものが知られている(特許文献1参照)。この文献には、絶縁基板となるガラス基板を挟んで2枚のシリコン基板が積層され、一方のシリコン基板がガラス基板に接合される前にシリコン基板の裏面側に凹部を設けることで、半導体圧力センサの受圧部となるダイヤフラムが一方のシリコン基板に形成された半導体圧力センサの発明が記載されている。   Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). In this document, two silicon substrates are stacked with a glass substrate serving as an insulating substrate interposed therebetween, and a recess is formed on the back side of the silicon substrate before one silicon substrate is bonded to the glass substrate. An invention of a semiconductor pressure sensor in which a diaphragm serving as a pressure receiving portion of the sensor is formed on one silicon substrate is described.

特開2001−41837号公報JP 2001-41837 A

上記従来の半導体圧力センサにおいては、ガラス基板にシリコン基板を陽極接合等により接合する前に、シリコン基板に凹部を形成することでセンサの受圧部となる薄肉状のダイヤフラムを予めシリコン基板に形成する必要があった。このため、シリコン基板に凹部を形成して薄肉化する手間が必要となり、コストが上昇するといった不具合を招いていた。   In the conventional semiconductor pressure sensor, a thin diaphragm serving as a pressure receiving portion of the sensor is formed in advance on the silicon substrate by forming a recess in the silicon substrate before bonding the silicon substrate to the glass substrate by anodic bonding or the like. There was a need. For this reason, it is necessary to form a recess in the silicon substrate to reduce the thickness, resulting in an increase in cost.

そこで、本発明は、上記に鑑みてなされたものであり、その目的とするところは、構造が簡単で安価に製造することが可能な半導体圧力センサ及びその製造方法を提供することにある。   Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor pressure sensor that has a simple structure and can be manufactured at low cost, and a manufacturing method thereof.

上記目的を達成するために、本発明に係る半導体圧力センサは、静電容量の変化により圧力を検出する半導体圧力センサにおいて、静電容量の一方の電極となる第1の半導体基板と、薄肉化されて感圧部を構成し、静電容量の他方の電極となる第2の半導体基板と、第1の半導体基板と前記第2の半導体基板との間に積層されて、前記第1の半導体基板と第2の半導体基板との間に静電容量の容量ギャップとなる空間を形成する絶縁性基板とを有することを第1の特徴とする。   In order to achieve the above object, a semiconductor pressure sensor according to the present invention is a semiconductor pressure sensor for detecting pressure by a change in capacitance, and a first semiconductor substrate serving as one electrode of the capacitance, and a thinner wall. The second semiconductor substrate constituting the pressure sensing portion and serving as the other electrode of the capacitance, and laminated between the first semiconductor substrate and the second semiconductor substrate. A first feature is that an insulating substrate is provided which forms a space serving as a capacitance gap of capacitance between the substrate and the second semiconductor substrate.

また、本発明に係る半導体圧力センサは、上記第1の特徴の半導体圧力センサにおいて、第1の半導体基板に接続される電極配線は、第2の半導体基板に形成された引き出し口を介して第2の半導体基板側に引き出され、もしくは第2の半導体基板に接続される電極配線は、第1の半導体基板に形成された引き出し口を介して第1の半導体基板側に引き出されることを第2の特徴とする。   The semiconductor pressure sensor according to the present invention is the semiconductor pressure sensor according to the first feature, wherein the electrode wiring connected to the first semiconductor substrate is connected to the first semiconductor via the lead-out port formed in the second semiconductor substrate. The electrode wiring that is drawn out to the second semiconductor substrate or connected to the second semiconductor substrate is drawn out to the first semiconductor substrate side through the lead-out port formed in the first semiconductor substrate. It is characterized by.

また、本発明に係る半導体圧力センサは、上記第1または第2の特徴の半導体圧力センサにおいて、静電容量の容量ギャップは、絶縁性基板の厚さで規定されることを第3の特徴とする。   According to a third feature of the semiconductor pressure sensor of the present invention, in the semiconductor pressure sensor of the first or second feature, the capacitance gap of the capacitance is defined by the thickness of the insulating substrate. To do.

また、本発明に係る半導体圧力センサは、上記第1〜第3のいずれか1つの特徴の半導体圧力センサにおいて、絶縁性基板の厚さは、絶縁性基板と第2の半導体基板とを陽極接合する際の高電圧印加時に容量ギャップの空間で放電が生じない程度の間隔に設定されることを第4の特徴とする。   The semiconductor pressure sensor according to the present invention is the semiconductor pressure sensor according to any one of the first to third features, wherein the thickness of the insulating substrate is an anodic bonding between the insulating substrate and the second semiconductor substrate. The fourth feature is that the interval is set such that no discharge occurs in the space of the capacity gap when a high voltage is applied.

一方、本発明に係る半導体圧力センサの製造方法は、静電容量の変化により圧力を検出する半導体圧力センサの製造方法において、絶縁性基板に凹部を形成する第1の工程と、静電容量の一方の電極となる第1の半導体基板に、第1の工程で凹部が形成された絶縁性基板を、凹部の開口側を第1の半導体基板に向けて接合する第2の工程と、絶縁性基板の一方の主面を研磨して凹部を貫通させ、静電容量の容量ギャップの空間を形成する第3の工程と、絶縁性基板に静電容量の他方の電極となる第2の半導体基板を接合する第4の工程と、第2の半導体基板の一方の主面を研磨して薄肉化し、圧力を受ける感圧部を形成する第5の工程とを有することを第1の特徴とする。   On the other hand, a method for manufacturing a semiconductor pressure sensor according to the present invention includes a first step of forming a recess in an insulating substrate in a method for manufacturing a semiconductor pressure sensor that detects pressure by a change in capacitance, A second step of bonding an insulating substrate having a recess formed in the first step to the first semiconductor substrate serving as one electrode with the opening side of the recess facing the first semiconductor substrate; A third step of polishing one main surface of the substrate to penetrate the recess to form a capacitance gap space of the capacitance, and a second semiconductor substrate serving as the other electrode of the capacitance on the insulating substrate And a fifth step of forming a pressure-sensitive portion that receives pressure by polishing one of the main surfaces of the second semiconductor substrate to reduce the thickness. .

また、本発明に係る半導体圧力センサの製造方法は、上記第1の特徴の半導体圧力センサの製造方法において、第2の工程では、陽極接合により第1の半導体基板と絶縁性基板とが接合され、絶縁性基板の厚さは、陽極接合する際の高電圧印加時に容量ギャップの空間で放電が生じない程度の間隔に設定されることを第2の特徴とする。   The method for manufacturing a semiconductor pressure sensor according to the present invention is the method for manufacturing a semiconductor pressure sensor according to the first feature, wherein in the second step, the first semiconductor substrate and the insulating substrate are bonded by anodic bonding. The second feature is that the thickness of the insulating substrate is set to an interval that does not cause discharge in the space of the capacity gap when a high voltage is applied during anodic bonding.

本発明に係る第1の特徴の半導体圧力センサでは、圧力センサを簡便に製造することが可能となり、製造コストを安価にすることができる。   In the semiconductor pressure sensor having the first feature according to the present invention, the pressure sensor can be easily manufactured, and the manufacturing cost can be reduced.

本発明に係る第2の特徴の半導体圧力センサでは、電極配線を同方向に容易に引き出し形成することができる。   In the semiconductor pressure sensor according to the second feature of the present invention, the electrode wiring can be easily drawn out in the same direction.

本発明に係る第3の特徴の半導体圧力センサでは、静電容量の容量ギャップを容易に設定することが可能となる。   In the semiconductor pressure sensor of the third feature according to the present invention, it is possible to easily set the capacitance gap of the capacitance.

本発明に係る第4の特徴の半導体圧力センサでは、陽極接合時の放電を防止することが可能となり、放電による悪影響を回避することができる。   In the semiconductor pressure sensor of the fourth feature according to the present invention, it is possible to prevent discharge at the time of anodic bonding, and to avoid adverse effects due to discharge.

本発明に係る第5の特徴の半導体圧力センサの製造方法では、圧力センサを簡便に製造することが可能となり、製造コストを安価にすることができる。   In the semiconductor pressure sensor manufacturing method according to the fifth aspect of the present invention, the pressure sensor can be easily manufactured, and the manufacturing cost can be reduced.

本発明に係る第6の特徴の半導体圧力センサの製造方法では、陽極接合時の放電を防止することが可能となり、放電による損傷を回避することができる。   In the method for manufacturing a semiconductor pressure sensor according to the sixth aspect of the present invention, it becomes possible to prevent discharge during anodic bonding, and damage due to discharge can be avoided.

本発明の実施例1に係る半導体圧力センサの構成を示す図である。It is a figure which shows the structure of the semiconductor pressure sensor which concerns on Example 1 of this invention. 本発明の実施例1に係る半導体圧力センサの他の構成を示す図である。It is a figure which shows the other structure of the semiconductor pressure sensor which concerns on Example 1 of this invention. 本発明の実施例1に係る半導体圧力センサの製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor pressure sensor which concerns on Example 1 of this invention. 本発明の実施例1に係る半導体圧力センサの製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor pressure sensor which concerns on Example 1 of this invention. 本発明の実施例1に係る半導体圧力センサの製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor pressure sensor which concerns on Example 1 of this invention.

以下、図面を用いて本発明を実施するための実施例を説明する。   Embodiments for carrying out the present invention will be described below with reference to the drawings.

図1は本発明の実施例1に係る半導体圧力センサの構成を示す図であり、同図(a)は平面図、同図(b)は断面図である。図1に示す実施例1の半導体圧力センサは、外部から加えられる圧力を受圧するダイヤフラムのたわみを静電容量の変化として検出する半導体圧力センサとして機能し、シリコン等の半導体で構成された第1の半導体基板1ならびに第2の半導体基板2と、絶縁性のガラス基板3とを備えて構成されている。   1A and 1B are diagrams showing a configuration of a semiconductor pressure sensor according to a first embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. The semiconductor pressure sensor of Example 1 shown in FIG. 1 functions as a semiconductor pressure sensor that detects a deflection of a diaphragm that receives a pressure applied from the outside as a change in capacitance, and is configured by a semiconductor such as silicon. The semiconductor substrate 1 and the second semiconductor substrate 2, and an insulating glass substrate 3 are provided.

第1の半導体基板1は、静電容量の一方の電極として機能する固定電極を構成し、第1の半導体基板1上に形成された電極パッド4aに電気的に接続された電極配線5aを介して静電容量を検出する検出回路(図示せず)に接続されている。   The first semiconductor substrate 1 constitutes a fixed electrode that functions as one electrode of capacitance, and is connected via an electrode wiring 5a electrically connected to an electrode pad 4a formed on the first semiconductor substrate 1. Are connected to a detection circuit (not shown) for detecting capacitance.

第1の半導体基板1上には、ガラスが選択的に除去された貫通領域6a,6bが形成されたガラス基板3が接合されて積層されている。ガラス基板3に形成された一方の貫通領域6aは、第1の半導体基板1と第2の半導体基板2との間に、静電容量の対向する電極間の空間、すなわち容量ギャップを形成し、他方の貫通領域6bは、第1の半導体基板1の電極パッド4aに接続された電極配線5aを第2の半導体基板2側に引き出す際の引き出し口を構成する。   On the first semiconductor substrate 1, a glass substrate 3 on which through regions 6a and 6b from which glass has been selectively removed is formed is bonded and laminated. One through region 6a formed in the glass substrate 3 forms a space between electrodes facing the capacitance, that is, a capacitance gap, between the first semiconductor substrate 1 and the second semiconductor substrate 2, The other penetrating region 6b constitutes a lead-out port when the electrode wiring 5a connected to the electrode pad 4a of the first semiconductor substrate 1 is drawn out to the second semiconductor substrate 2 side.

ガラス基板3上には、第2の半導体基板2が接合されて積層されている。第2の半導体基板2は、基板が薄肉化され、受圧した圧力でたわんで圧力を検出する感圧部となるダイヤフラム7が形成され、このダイヤフラム7は静電容量の他方の電極として機能する可動電極を構成する。第2の半導体基板2は、基板上に形成された電極パッド4bに電気的に接続された電極配線5bを介して静電容量を検出する先に触れた検出回路に接続されている。   On the glass substrate 3, the second semiconductor substrate 2 is bonded and laminated. In the second semiconductor substrate 2, the substrate is thinned, and a diaphragm 7 is formed as a pressure-sensitive part that detects the pressure by bending with the received pressure, and this diaphragm 7 functions as the other electrode of the capacitance. Configure the electrode. The second semiconductor substrate 2 is connected to the detection circuit touched earlier for detecting the capacitance via the electrode wiring 5b electrically connected to the electrode pad 4b formed on the substrate.

このような構成において、ダイヤフラム7で圧力を受圧すると、受圧した圧力に応じて薄肉状のダイヤフラム7がたわみ、このたわみにより固定電極と可動電極との間の静電容量が変化し、その静電容量の変化を電気的に検出して圧力を検出するようにしている。   In such a configuration, when pressure is received by the diaphragm 7, the thin-walled diaphragm 7 is deflected according to the received pressure, and the capacitance between the fixed electrode and the movable electrode changes due to this deflection, and the electrostatic capacitance is changed. A change in capacity is detected electrically to detect pressure.

このような構造においては、ダイヤフラム7は全面が薄肉化された第2の半導体基板2として形成されるので、従来のように半導体基板に凹部を形成してダイヤフラムを形成する必要はなくなる。これにより、構造が簡単で製造コストを安価にすることが可能となる。   In such a structure, since the diaphragm 7 is formed as the second semiconductor substrate 2 whose entire surface is thinned, it is not necessary to form a diaphragm in the semiconductor substrate to form a diaphragm as in the prior art. As a result, the structure is simple and the manufacturing cost can be reduced.

第1の半導体基板1、第2の半導体基板2をガラス基板3に接合する場合に、他の接合部材を介在させずに簡便に行うことが可能な陽極接合が多用されている。この陽極接合では、半導体基板とガラス基板との間に例えば500V〜800V程度の高電圧が印加される。このときに、容量ギャップの電極間距離が短いと、この空間で放電が生じやすくなり、この放電により接合不良等の悪影響を招くおそれがあった。   When joining the 1st semiconductor substrate 1 and the 2nd semiconductor substrate 2 to the glass substrate 3, the anodic bonding which can be simply performed without interposing another joining member is used abundantly. In this anodic bonding, a high voltage of about 500 V to 800 V, for example, is applied between the semiconductor substrate and the glass substrate. At this time, if the distance between the electrodes of the capacity gap is short, discharge easily occurs in this space, and this discharge may cause adverse effects such as poor bonding.

したがって、陽極接合時の印加電圧に応じて放電が生じない程度の距離、例えば20μ〜50μ程度に容量ギャップの間隔を設定することで、高電圧印加時に半導体基板とガラス基板とを短絡して放電を防止する短絡配線(放電防止配線)を設けることなく放電を回避することが可能となる。これにより、短絡配線が不要となり、構造の複雑化を回避することができる。また、短絡配線を形成したり、半導体基板とガラス基板との接合後この短絡配線を切断したりといった製造工程が不要となり、製造工程の簡略化、製造コストの安価を実現することができる。   Therefore, by setting the distance of the capacitance gap to a distance that does not cause discharge according to the applied voltage during anodic bonding, for example, about 20 μ to 50 μ, the semiconductor substrate and the glass substrate are short-circuited when high voltage is applied. It is possible to avoid discharge without providing a short-circuit wiring (discharge prevention wiring) that prevents the discharge. This eliminates the need for short-circuit wiring and avoids the complexity of the structure. In addition, a manufacturing process such as forming a short-circuit wiring or cutting the short-circuit wiring after the semiconductor substrate and the glass substrate are joined becomes unnecessary, and the manufacturing process can be simplified and the manufacturing cost can be reduced.

なお、容量ギャップの距離は、実験等の結果に基づいて予め設定されるが、例えば電極間の距離と放電電圧との関係を示す従来から知られているパッシェンの法則に基づいて、印加電圧に応じて適宜設定される。   The distance of the capacity gap is set in advance based on the result of an experiment or the like. For example, based on the conventionally known Paschen's law indicating the relationship between the distance between the electrodes and the discharge voltage, It is set accordingly.

また、図1に示す構造では、半導体圧力センサが設置される面に対して上側にダイヤフラム7を設けかつ上側に電極配線5a、5bを引き出しようにしているが、図2(同図(a)は平面図、同図(b)は断面図)に示すように、電極配線5a、5bは図1と同様に設置面に対して上側に引き出している一方、下側にダイヤフラム7を設けて下側から受圧するタイプであってもかまわない。   Further, in the structure shown in FIG. 1, the diaphragm 7 is provided on the upper side with respect to the surface on which the semiconductor pressure sensor is installed, and the electrode wirings 5a and 5b are drawn on the upper side, but the structure shown in FIG. 1 is a plan view, and FIG. 1B is a cross-sectional view. As in FIG. 1, the electrode wires 5a and 5b are drawn upward with respect to the installation surface, while a diaphragm 7 is provided on the lower side. It may be a type that receives pressure from the side.

次に、製造工程を示す図3(図3−A、図3−B、図3−C)を参照して、図1に示す半導体圧力センサの製造方法を説明する。   Next, a method of manufacturing the semiconductor pressure sensor shown in FIG. 1 will be described with reference to FIG. 3 (FIGS. 3-A, 3-B, and 3-C) showing the manufacturing process.

先ず、ホウ珪酸ガラス等の絶縁性のガラス基板3を用意し(図3−A(a(断面図)))、静電容量の容量ギャップとなる貫通領域6a、ならびに電極配線5aの引き出し口となる貫通領域6bとなる部分のガラスを深堀りして選択的に除去し凹部31a、31bを形成する(図3−A(b1(平面図))、(b2(断面図)))。   First, an insulating glass substrate 3 such as borosilicate glass is prepared (FIG. 3A (a (cross-sectional view))), a through region 6a serving as a capacitance gap of capacitance, and a lead-out port of the electrode wiring 5a; The portion of the glass to be the through region 6b is deeply removed and selectively removed to form the recesses 31a and 31b (FIG. 3-A (b1 (plan view), (b2 (cross-sectional view))).

一方、シリコン等の半導体からなる第1の半導体基板1を用意し(図3−A(c(断面図)))、アルミ等の金属で電極パッド4aを形成する(図3−A(d1(平面図))、(d2(断面図)))。   On the other hand, a first semiconductor substrate 1 made of a semiconductor such as silicon is prepared (FIG. 3-A (c (cross-sectional view))), and an electrode pad 4a is formed of a metal such as aluminum (FIG. 3-A (d1 ( Plan view)), (d2 (sectional view))).

その後、第1の半導体基板1とガラス基板3とを重ね合わせて、第1の半導体基板1とガラス基板3との間に500V〜800V程度の高電圧を印加して両者を陽極接合する(図3−A(e(断面図)))。この陽極接合時に、凹部31a、31bの深さを先に説明したように例えば20μ〜50μ程度とすることで、高電圧印加時に凹部31a、31bでの放電を回避することができる。   Thereafter, the first semiconductor substrate 1 and the glass substrate 3 are overlapped, and a high voltage of about 500 V to 800 V is applied between the first semiconductor substrate 1 and the glass substrate 3 to anodic bond them (see FIG. 3-A (e (sectional view))). At the time of this anodic bonding, the depth of the recesses 31a and 31b is set to, for example, about 20 to 50 μm as described above, whereby discharge in the recesses 31a and 31b can be avoided when a high voltage is applied.

次いで、第1の半導体基板1に接合されたガラス基板3の表面を研磨して除去し、凹部31a、31bを表面側に貫通させ、貫通領域6a、6bを形成する(図3−B(f1(平面図))、(f2(断面図)))。この研磨工程において、ガラス基板3を研磨する量を調整することでガラス基板3の厚さを調整し、静電容量の電極間を所定の間隔に設定して静電容量値を所定の値に設定する。   Next, the surface of the glass substrate 3 bonded to the first semiconductor substrate 1 is polished and removed, and the recesses 31a and 31b are penetrated to the surface side to form the through regions 6a and 6b (FIG. 3-B (f1 (Plan view)), (f2 (sectional view))). In this polishing step, the thickness of the glass substrate 3 is adjusted by adjusting the amount of polishing of the glass substrate 3, and the capacitance value is set to a predetermined value by setting a predetermined interval between the electrodes of the electrostatic capacitance. Set.

一方、シリコン等の半導体からなる第2の半導体基板2を用意し(図3−B(g(断面図)))、第2の半導体基板2の一方の主面にガラス基板3を接合する際に使用する接合方法に応じた接合部材32を形成する。この接合部材32は、例えば低融点ガラス、ポリマー、金(Au)等で構成される(図3−B(h(断面図)))。   On the other hand, a second semiconductor substrate 2 made of a semiconductor such as silicon is prepared (FIG. 3-B (g (cross-sectional view))), and the glass substrate 3 is bonded to one main surface of the second semiconductor substrate 2. The joining member 32 according to the joining method used for is formed. The joining member 32 is made of, for example, low-melting glass, polymer, gold (Au), or the like (FIG. 3-B (h (sectional view))).

その後、低融点ガラスの場合にはスパッタリングにより、ポリマーの場合には接着で、Auの場合には共晶接合により、それぞれの接合に適した温度、圧力の雰囲気を設定して第2の半導体基板2とガラス基板3とを接合する(図3−B(i(断面図)))。なお、この接合に陽極接合を用いてもよい。   Thereafter, an atmosphere of temperature and pressure suitable for each bonding is set by sputtering in the case of low melting point glass, adhesion in the case of polymer, or eutectic bonding in the case of Au, and the second semiconductor substrate. 2 and the glass substrate 3 are joined (FIG. 3-B (i (cross-sectional view)). Note that anodic bonding may be used for this bonding.

次いで、第2の半導体基板2の他方の主面側の全面を研磨して厚さを薄くし薄肉化する(図3−B(j(断面図)))。続いて、第2の半導体基板2の表面に電極パッド4bを形成した後(図3−C(k1(平面図)、(k2(断面図)))、ダイヤフラム7ならびにこのダイヤフラム7と電極パッド4bを電気的に接続する領域を残すように第2の半導体基板2を選択的にエッチング除去し、ダイヤフラム7を形成する(図3−C(l1(平面図)、(l2(断面図)))。最後に、図示しないがウェハ上に形成された多数のチップをダイシングにより個々のチップに分割して半導体圧力センサが完成し、このチップが実装される際に各電極パッド4a、4bに電極配線5a、5bが接続される。   Next, the entire surface on the other main surface side of the second semiconductor substrate 2 is polished to reduce the thickness and reduce the thickness (FIG. 3B (j (cross-sectional view)). Subsequently, after the electrode pad 4b is formed on the surface of the second semiconductor substrate 2 (FIG. 3-C (k1 (plan view), (k2 (cross-sectional view))), the diaphragm 7 and the diaphragm 7 and the electrode pad 4b are formed. The second semiconductor substrate 2 is selectively removed by etching so as to leave a region for electrically connecting the two to form a diaphragm 7 (FIG. 3-C (l1 (plan view), (l2 (cross-sectional view))) Finally, although not shown, a large number of chips formed on the wafer are divided into individual chips by dicing to complete a semiconductor pressure sensor, and when this chip is mounted, electrode wiring is applied to each electrode pad 4a, 4b. 5a and 5b are connected.

このように、上記製造方法においては、固定電極となる第1の半導体基板1と可動電極となる第2の半導体基板2との間に積層されるガラス基板3を研磨して、静電容量の容量ギャップの空間を形成することで、圧力センサの静電容量を簡便に形成することが可能となる。また、第2の半導体基板2を研磨して薄肉化することで、感圧部のダイヤフラムを簡便に形成することが可能となる。これにより、半導体圧力センサの製造方法を簡便にすることが可能となり、製造コストを安価にすることができる。さらに、ガラス基板3の研磨量に応じて静電容量の電極間の間隔を設定することが可能となり、静電容量の値を容易に制御することができる。   As described above, in the above manufacturing method, the glass substrate 3 laminated between the first semiconductor substrate 1 serving as the fixed electrode and the second semiconductor substrate 2 serving as the movable electrode is polished to obtain the capacitance. By forming the space of the capacitance gap, the capacitance of the pressure sensor can be easily formed. Further, by polishing and thinning the second semiconductor substrate 2, it is possible to easily form the diaphragm of the pressure sensitive part. Thereby, the manufacturing method of the semiconductor pressure sensor can be simplified, and the manufacturing cost can be reduced. Furthermore, it becomes possible to set the space | interval between the electrodes of an electrostatic capacitance according to the grinding | polishing amount of the glass substrate 3, and can control the value of an electrostatic capacitance easily.

一方、ガラス基板3を第1の半導体基板1に陽極接合する工程において、放電が生じない程度の深さに掘り込んだ凹部を有するガラス基板3を使用することで、高電圧印加時における凹部空間での放電を防止することが可能となり、放電による接合不良等の悪影響を回避することができる。   On the other hand, in the step of anodic bonding of the glass substrate 3 to the first semiconductor substrate 1, by using the glass substrate 3 having a recess dug to a depth that does not cause discharge, a recess space when a high voltage is applied. It is possible to prevent the discharge at the point of time, and the adverse effects such as poor bonding due to the discharge can be avoided.

1…第1の半導体基板
2…第2の半導体基板
3…ガラス基板
4a,4b…電極パッド
5a,5b…電極配線
6a,6b…貫通領域
6b…貫通領域
7…ダイヤフラム
31a,31b…凹部
32…接合部材
DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor substrate 2 ... 2nd semiconductor substrate 3 ... Glass substrate 4a, 4b ... Electrode pad 5a, 5b ... Electrode wiring 6a, 6b ... Through region 6b ... Through region 7 ... Diaphragm 31a, 31b ... Recess 32 Joining member

Claims (6)

静電容量の変化により圧力を検出する半導体圧力センサにおいて、
前記静電容量の一方の電極となる第1の半導体基板と、
薄肉化されて感圧部を構成し、前記静電容量の他方の電極となる第2の半導体基板と、
前記第1の半導体基板と前記第2の半導体基板との間に積層されて、前記第1の半導体基板と前記第2の半導体基板との間に前記静電容量の容量ギャップとなる空間を形成する絶縁性基板と
を有することを特徴とする半導体圧力センサ。
In a semiconductor pressure sensor that detects pressure by a change in capacitance,
A first semiconductor substrate serving as one electrode of the capacitance;
A second semiconductor substrate that is thinned to form a pressure-sensitive portion and serves as the other electrode of the capacitance;
A space is formed between the first semiconductor substrate and the second semiconductor substrate to form a capacitance gap of the capacitance between the first semiconductor substrate and the second semiconductor substrate. And a semiconductor pressure sensor.
前記第1の半導体基板に接続される電極配線は、前記第2の半導体基板に形成された引き出し口を介して前記第2の半導体基板側に引き出され、もしくは前記第2の半導体基板に接続される電極配線は、前記第1の半導体基板に形成された引き出し口を介して前記第1の半導体基板側に引き出される
ことを特徴とする請求項1に記載の半導体圧力センサ。
The electrode wiring connected to the first semiconductor substrate is drawn out to the second semiconductor substrate side through a lead-out port formed in the second semiconductor substrate, or connected to the second semiconductor substrate. 2. The semiconductor pressure sensor according to claim 1, wherein the electrode wiring is drawn out to the first semiconductor substrate side through a lead-out port formed in the first semiconductor substrate.
前記静電容量の容量ギャップは、前記絶縁性基板の厚さで規定される
ことを特徴とする請求項1または2に記載の半導体圧力センサ。
The semiconductor pressure sensor according to claim 1, wherein a capacitance gap of the capacitance is defined by a thickness of the insulating substrate.
前記絶縁性基板の厚さは、前記絶縁性基板と前記第1の半導体基板とを陽極接合する際の高電圧印加時に前記容量ギャップの空間で放電が生じない程度の間隔に設定される
ことを特徴とする請求項1〜3のいずれか1項に記載の半導体圧力センサ。
The thickness of the insulating substrate is set to an interval that does not cause a discharge in the space of the capacitance gap when a high voltage is applied when the insulating substrate and the first semiconductor substrate are anodic bonded. The semiconductor pressure sensor according to claim 1, wherein the pressure sensor is a semiconductor pressure sensor.
静電容量の変化により圧力を検出する半導体圧力センサの製造方法において、
絶縁性基板に凹部を形成する第1の工程と、
静電容量の一方の電極となる第1の半導体基板に、前記第1の工程で凹部が形成された絶縁性基板を、前記凹部の開口側を前記第1の半導体基板に向けて接合する第2の工程と、
前記絶縁性基板の一方の主面を研磨して前記凹部を貫通させ、静電容量の容量ギャップの空間を形成する第3の工程と、
前記絶縁性基板に前記静電容量の他方の電極となる第2の半導体基板を接合する第4の工程と、
前記第2の半導体基板の一方の主面を研磨して薄肉化し、圧力を受ける感圧部を形成する第5の工程と
を有することを特徴とする半導体圧力センサの製造方法。
In the manufacturing method of the semiconductor pressure sensor for detecting the pressure by the change in capacitance,
A first step of forming a recess in the insulating substrate;
A first semiconductor substrate serving as one electrode of capacitance is bonded to an insulating substrate having a recess formed in the first step with an opening side of the recess facing the first semiconductor substrate. Two steps;
A third step of polishing one main surface of the insulating substrate to penetrate the concave portion to form a capacitance gap space of capacitance;
A fourth step of bonding a second semiconductor substrate serving as the other electrode of the capacitance to the insulating substrate;
And a fifth step of forming a pressure-sensitive portion that receives pressure by polishing one main surface of the second semiconductor substrate to make it thinner.
前記第2の工程では、陽極接合により前記第1の半導体基板と前記絶縁性基板とが接合され、前記絶縁性基板の厚さは、陽極接合する際の高電圧印加時に前記容量ギャップの空間で放電が生じない程度の間隔に設定される
ことを特徴とする請求項5に記載の半導体圧力センサの製造方法。
In the second step, the first semiconductor substrate and the insulating substrate are bonded by anodic bonding, and the thickness of the insulating substrate is determined in the space of the capacitance gap when a high voltage is applied during anodic bonding. 6. The method of manufacturing a semiconductor pressure sensor according to claim 5, wherein the interval is set such that no discharge occurs.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014206775A (en) * 2013-04-10 2014-10-30 株式会社ワコム Position indicator
JP2015167406A (en) * 2015-06-09 2015-09-24 日本高周波株式会社 dummy load

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014206775A (en) * 2013-04-10 2014-10-30 株式会社ワコム Position indicator
JP2015167406A (en) * 2015-06-09 2015-09-24 日本高周波株式会社 dummy load

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