JP2010217992A - Cache controller, cache control method, and cache control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform prefetch in a proper timing so that data that are likely to be accessed in each cycle are read from a cache, in a cyclic processing whose scale is large enough to exceed the capacity of a cache memory. <P>SOLUTION: A cache control analyzing part 115 generates access statistical information 116 showing the statistics of timings of cache miss and addresses for cache misses which have occurred in the same addresses in different timings of 10 micro-seconds in N÷5 or more cycles in 1-N cycles of cyclic processing. A timing correction part 117 sets the prefetch timing from the statistics of the timings shown by the access statistical information 116, the time for prefetch processing and the time for accessing a RAM 111 when the cache miss occurs. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a cache control device, a cache control method, and a cache control program.

  For example, an embedded device such as an industrial controller product is required to have real-time characteristics that respond to a sensor input or a control output within a predetermined time. Software for such an embedded device is generally configured by periodic processing that repeatedly executes processing determined at regular time intervals. In such an embedded device, executing as many processes and calculations as possible in a certain time leads to high performance and high functionality, but one of the factors that greatly affects the processing performance is a memory cache.

  If the cache capacity is sufficient, data that is accessed every cycle is always present in the cache, and the periodic processing can be executed efficiently without waiting for memory access. However, due to the increase in software scale due to the high functionality of embedded devices, the data handled by periodic processing cannot be stored in the cache, so a cache miss occurs at a fixed position every cycle, and the execution speed Cases that cause a drop occur.

  In Patent Document 1, in order to deal with the above case, the period is determined by monitoring the average number of clocks for each section of the program, the position where the cache miss occurred, and the elapsed time, and the elapsed time causing the cache miss. And a system-specific memory access delay time, a prefetch position within the cycle is obtained, and a prefetch is performed at that timing, thereby preventing a cache miss that occurs each time in the cycle processing.

  Further, Patent Document 2 discloses a method of prefetching by recording an access history when there is a predetermined pattern of data access and designating the history at the next access.

JP 2008-2226025 A JP 2005-157711 A

  In the method of Patent Document 1, when determining the prefetch position, a prefetch instruction is given at a timing earlier by the memory access delay time than the elapsed time causing the cache miss. However, with this method, when trying to deal with multiple cache misses within a cycle, the cache miss position that should occur after the cache miss that occurred after pre-fetching has been resolved. Since it is advanced by the delay, there is a possibility that the prefetch timing may be delayed with respect to the actual operation, and there is a problem that prefetch cannot be performed at an appropriate timing.

  In addition, the method of Patent Document 2 enables prefetching by informing the access order in advance, and there is a problem that it cannot be applied to periodic processing because the timing is not considered. In the case of a memory cache, it is not only necessary to prepare data in advance, but the timing for preparing the data is important, and if it is too early, execution of other processing may be hindered.

  An object of the present invention is to perform prefetching at an appropriate timing so that, for example, in a large-scale periodic process exceeding the capacity of a cache memory, data having a high probability of being accessed every cycle is a cache hit.

A cache control device according to one aspect of the present invention includes:
A delay indicating a cache control processing delay time that is a time for prefetch processing for pre-reading data from the main memory to the cache memory, and a memory access delay time that is a time for accessing the main memory when a cache miss occurs A storage device for preliminarily storing time information and access trace information indicating the timing and address at which a cache miss occurs for each cache miss occurring in a plurality of cycles of periodic processing executed at fixed intervals; and data processing And a processing device for performing
From the access trace information stored in the storage device, a cache miss that occurs at the same address with a timing difference within a predetermined range in a predetermined number of cycles or more among the plurality of cycles is extracted as a cache miss set by the processing device. For each extracted cache miss set, the processing device calculates the statistics of the timing at which a cache miss has occurred, and provides access statistical information indicating the calculated timing statistics and the address at which the cache miss has occurred. Cache control analysis unit generated by
For each cache miss set extracted by the cache control analysis unit, the cache control indicated by the timing statistics indicated by the access statistical information generated by the cache control analysis unit and the delay time information stored in the storage device Based on the processing delay time and the memory access delay time, the processing device sets the timing for executing the prefetch processing, and the processing device generates a cache control scenario indicating the set timing and the address indicated by the access statistical information. And a cache control scenario generation unit.

  According to an aspect of the present invention, in the cache control device, the cache control analysis unit generates a cache generated for the same address with a timing difference within a predetermined range in a predetermined number or more of a plurality of cycles of the periodic processing. A miss is extracted as a cache miss set, and for each extracted cache miss set, access statistical information indicating the statistics and address of the timing at which the cache miss occurs is generated, and the cache control scenario generator generates a cache miss set for each cache miss set. , The timing statistics indicated by the access statistical information, the cache control processing delay time that is the time for prefetch processing, and the memory access delay time that is the time to access the main memory when a cache miss occurs To set the timing to execute the prefetch process, In order to generate a cache control scenario that indicates the specified timing and the address indicated by the access statistical information, in a large-scale periodic process exceeding the capacity of the cache memory, data with a high probability of being accessed every cycle is a cache hit. Thus, prefetching can be performed at an appropriate timing according to the cache control scenario.

1 is a block diagram illustrating a configuration of a cache control device according to a first embodiment. 2 is a diagram illustrating an example of a hardware configuration of a cache control device according to Embodiment 1. FIG. 10 is a table showing an example of access trace information according to the first embodiment. It is a figure which shows the method in which the cache control analysis part which concerns on Embodiment 1 extracts the cache miss made into the object of prefetch. 10 is a table showing an example of access statistical information according to the first embodiment. 4 is a table showing an example of a cache control scenario according to the first embodiment. 4 is a flowchart illustrating an operation of a cache control unit according to the first embodiment. 10 is a table showing an example of information defining a synchronization event according to the second embodiment. 10 is a table showing an example of access statistical information according to the second embodiment. 10 is a table showing an example of a cache control scenario according to the second embodiment. 10 is a flowchart illustrating an operation of a cache control unit according to the second embodiment. 10 is a flowchart illustrating an operation of a cache control unit according to the second embodiment. 10 is a flowchart illustrating an operation of a cache control unit according to the second embodiment. FIG. 10 is a block diagram illustrating a configuration of a cache control device according to a third embodiment. 14 is a flowchart illustrating an operation of a cache control unit according to the third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of the cache control apparatus 100 according to the present embodiment.

  In FIG. 1, the cache control device 100 includes a multi-core processor including a main core 101 and a sub-core 102. In the following, the cache control according to the present embodiment is performed in a core (sub-core 102) different from the processor core (main core 101) that executes periodic processing (processing executed at regular intervals) using a multi-core processor. Shows how to do. Note that cache control according to the present embodiment may be performed using a single core processor.

  The cache control apparatus 100 includes, on the main core 101 side, a periodic task 103 that performs normal periodic processing, and an OS 104 (operating system) that manages execution of the periodic task 103. The cache control apparatus 100 further monitors (hooks) the dispatcher 105 responsible for switching execution contexts such as tasks, interrupt handlers, and system calls in the OS 104, and uses the shared memory to monitor the execution status of the periodic task 103. A synchronization unit 106 that notifies the 102 side is provided. As a notification method, in addition to the shared memory, a method of using an interrupt signal, a communication register, and other shared resources between cores is conceivable, but is not limited thereto.

  The cache control device 100 includes, on the sub-core 102 side, a cache control scenario 107 in which an address and timing for performing prefetch (a process for reading data from the main memory to the cache memory in advance) are described, and the periodic processing notified from the synchronization unit 106 A clock counter 108 that measures an elapsed time from the start point of the cache, and a cache control unit 109 that performs prefetching at a designated timing with reference to these.

  In the present embodiment, the cache control device 100 generates data between the shared cache 110 (an example of a cache memory) and a RAM 111 (an example of a random access memory) (an example of a main memory) in order to generate a cache control scenario 107. A memory access monitoring unit 113 that collects address and time information that causes a cache miss by monitoring the behavior of the memory controller 112 that manages the transfer is provided. As a collection method, it is possible to use various methods such as monitoring the behavior of the memory controller 112, tracing a memory bus, and analyzing a cache behavior simulation result by a simulator. Information collected during the execution of the periodic task 103 is stored in the HDD (Hard / Disk / Drive) as access trace information 114 by the memory access monitoring unit 113. The cache control apparatus 100 analyzes the access trace information 114 by the cache control analysis unit 115 to extract a cache miss occurrence timing common to each cycle, and generates access statistical information 116. The access statistical information 116 is stored in the HDD by the cache control analysis unit 115. After that, the timing correction unit 117 (an example of a cache control scenario generation unit) calculates an appropriate timing for prefetching, and the result is stored as a cache control scenario 107 in the HDD.

  The multi-core processor described above is an example of a processing device that performs data processing. The HDD and RAM 111 described above are examples of storage devices that store data (information). The cache control device 100 may include an input device, an output device, and the like in addition to the processing device and the storage device. These hardware are used by each unit of the cache control device 100. For example, the processing device is used for performing calculation, processing, reading, writing, and the like of data in each unit of the cache control device 100. The storage device is used to store the data. Further, the input device is used for inputting the data, and the output device is used for outputting the data.

  FIG. 2 is a diagram illustrating an example of a hardware configuration of the cache control device 100.

  In FIG. 2, a cache control device 100 is a computer such as a microcomputer or a personal computer, and includes an LCD 121 (Liquid / Crystal / Display), a keyboard 122 (K / B), a mouse 123, an FDD 124 (Flexible Disk / Drive), A hardware device such as a CDD 125 (Compact Disc Drive) or a printer 126 is provided. These hardware devices are connected by cables and signal lines. Instead of the LCD 121, a CRT (Cathode / Ray / Tube) or other display device may be used. Instead of the mouse 123, a touch panel, a touch pad, a trackball, a pen tablet, or other pointing devices may be used.

  The cache control device 100 includes a CPU 131 (Central Processing Unit) that executes a program. The CPU 131 is an example of a processing device. In the present embodiment, the CPU 131 is a multi-core processor. The CPU 131 is connected to the ROM 133 (Read / Only / Memory), the RAM 111, the communication board 135, the LCD 121, the keyboard 122, the mouse 123, the FDD 124, the CDD 125, the printer 126, and the HDD 140 (Hard / Disk / Drive) via the bus 132. Control these hardware devices. Instead of the HDD 140, a flash memory, an optical disk device, a memory card reader / writer, or other storage medium may be used.

  The RAM 111 is an example of a volatile memory. The ROM 133, the FDD 124, the CDD 125, and the HDD 140 are examples of nonvolatile memories. These are examples of the storage device. The communication board 135, the keyboard 122, the mouse 123, the FDD 124, and the CDD 125 are examples of input devices. The communication board 135, the LCD 121, and the printer 126 are examples of output devices.

  The communication board 135 is connected to a LAN (Local / Area / Network) or the like. The communication board 135 is not limited to a LAN, but includes an IP-VPN (Internet, Protocol, Private, Network), a wide area LAN, an ATM (Asynchronous / Transfer / Mode) network, a WAN (Wide / Area / Network), or the Internet. It does not matter if it is connected to. LAN, WAN, and the Internet are examples of networks.

  The HDD 140 stores an OS 104, a program group 143, and a file group 144. The programs in the program group 143 are executed by the CPU 131 and the OS 104. The program group 143 includes programs that execute the functions described as “˜units” in the description of the present embodiment. The program is read and executed by the CPU 131. The file group 144 includes data, information, and signal values described as “˜data”, “˜information”, “˜ID (identifier)”, “˜flag”, and “˜result” in the description of the present embodiment. And variable values and parameters are included as items of “˜file”, “˜database”, and “˜table”. The “˜file”, “˜database”, and “˜table” are stored in a storage medium such as the RAM 111 and the HDD 140. Data, information, signal values, variable values, and parameters stored in a storage medium such as the RAM 111 and the HDD 140 are read out to the main memory and the cache memory by the CPU 131 via a read / write circuit, and extracted, searched, referenced, compared, and calculated. It is used for processing (operation) of the CPU 131 such as calculation, control, output, printing, and display. During processing of the CPU 131 such as extraction, search, reference, comparison, calculation, calculation, control, output, printing, and display, data, information, signal values, variable values, and parameters are temporarily stored in the main memory, cache memory, and buffer memory. Remembered.

  The arrows in the block diagrams and flowcharts used in the description of this embodiment mainly indicate input / output of data and signals. Data and signals are recorded in a memory such as the RAM 111, a flexible disk (FD) of the FDD 124, a compact disk (CD) of the CDD 125, a magnetic disk of the HDD 140, an optical disk, a DVD (Digital Versatile Disc), or other recording media. Is done. Data and signals are transmitted by the bus 132, signal lines, cables, or other transmission media.

  In the description of the present embodiment, what is described as “to part” may be “to circuit”, “to device”, “to device”, and “to step”, “to process”, “to”. ~ Procedure "," ~ process ". That is, what is described as “˜unit” may be realized by firmware stored in the ROM 133. Alternatively, what is described as “˜unit” may be realized only by software, or only by hardware such as an element, a device, a board, and wiring. Alternatively, what is described as “to part” may be realized by a combination of software and hardware, or a combination of software, hardware and firmware. Firmware and software are stored as programs in a recording medium such as a flexible disk, a compact disk, a magnetic disk, an optical disk, and a DVD. The program is read by the CPU 131 and executed by the CPU 131. That is, the program causes the computer to function as “to part” described in the description of the present embodiment. Or a program makes a computer perform the procedure and method of "-part" described by description of this Embodiment.

  Next, the operation will be described.

  The present embodiment is realized by a phase for generating the cache control scenario 107 and a phase for executing the cache control scenario 107.

  First, a phase for generating the cache control scenario 107 will be described.

  In this phase, the sub-core 102 is stopped and normal cycle processing is executed only on the main core 101 side. At this time, if a cache miss occurs, the memory controller 112 is instructed to load necessary data from the RAM 111 to the shared cache 110. The memory access monitoring unit 113 traces this and reads the instruction, A set of a time (timing) in which the start point of the processing cycle is set to 0 and a target address that causes a cache miss is stored as access trace information 114 in the storage device.

  FIG. 3 is a table showing an example of the access trace information 114.

  The access trace information 114 is information indicating the timing (elapsed time from the cycle start time) and the address at which a cache miss occurs for each cache miss that occurs in a plurality of cycles of the periodic processing. In the example of FIG. 3, the timing at which a cache miss has occurred is recorded in the “time (millisecond)” column (row), and the address at which the cache miss has occurred is recorded in the “miss occurrence location” column. In the access trace information 114 of FIG. 3, for example, it is recorded that a cache miss for the address 0x00800010 occurs at a timing of 20380 nanoseconds in a certain cycle. In addition, it is recorded that a cache miss with respect to the address 0x00800100 occurred at at least three timings of 856222 nanoseconds, 1019983 nanoseconds, and 3019983 nanoseconds in a certain cycle.

  FIG. 4 is a diagram illustrating a method of extracting a cache miss to be prefetched by the cache control analysis unit 115.

  First, the cache control analysis unit 115 divides the contents of the access trace information 114 into cycle units based on the cycle time of the cycle process. In FIG. 4, the horizontal axis indicates the elapsed time (timing) from the start of each cycle of cycle 1 to cycle N (N is an integer satisfying N> 1), and a downward arrow indicates a cache miss at that time. Indicates the address where. The cache control analysis unit 115 defines a certain time range (for example, a range of 10 microseconds) as a totaling interval, and sets the start time of the totaling interval by S (N is a real number satisfying S> 0) by microseconds (for example, 1 Counting the cache miss addresses included in the counting interval while shifting (by microseconds). At this time, if a section in which an address appears in a cycle equal to or greater than a threshold (for example, N ÷ 5 times) continues one or more times, the cache control analysis unit 115 determines the address as a prefetch target. In addition, the cache control analysis unit 115 calculates the number of appearances, the average elapsed time, and the standard deviation of the elapsed time in the aggregation section that appears continuously in a cycle equal to or greater than the threshold for the target address, and the access statistical information 116 Record as. Note that the values of the totaling section and the threshold are adjusted as appropriate by tuning.

  For example, when N = 10 and a certain address A1, a cache miss occurs at a timing of 11 microseconds in cycle 1, 12 microseconds in cycle 2, and 13 microseconds in cycle 3, and at other timings, It is assumed that no cache miss has occurred in the period. When the length of the total section is 10 microseconds and S = 1, the number of appearances of the address A1 (the number of cycles in which a cache miss has occurred) is 0 times and 1 microsecond in the total section R0 starting from 0 microseconds. It is once in the total section R1 starting from the second, twice in the total section R2 starting from 2 microseconds, and three times in the total section R3 starting from 3 microseconds. The number of appearances of the address A1 remains three times from the total section R4 starting from the next 4 microseconds to the total section R11 starting from 11 microseconds, but the total section starting from 12 microseconds It is twice in R12, once in the total section R13 starting from 13 microseconds, and zero in the total section R14 starting from 14 microseconds. When the threshold value is N ÷ 5 times, the total sections in which the address A1 appears in a cycle equal to or greater than the threshold value are R2 to R12. Therefore, for example, the cache control analysis unit 115 calculates the average of the timing or the like for the aggregation section R3 in which the number of appearances of the address A1 is the maximum among the aggregation sections R2 to R12. In this example, the average timing is (11 microseconds + 12 microseconds + 13 microseconds) ÷ 3 = 12 microseconds.

  FIG. 5 is a table showing an example of the access statistical information 116.

  The access statistical information 116 is information indicating the average and standard deviation of the timing at which a cache miss occurs and an address for each cache miss set. In the example of FIG. 3, the average of the timing at which a cache miss occurred is in the “average elapsed time” column, the standard deviation of the timing at which the cache miss occurred is in the “standard deviation” column, and the address at which the cache miss has occurred is “miss occurrence” Recorded in the "Location" column. The number of appearances of the address is recorded in the “number of times” column. Further, the access statistical information 116 is sorted in ascending order of the value in the “average elapsed time” column, and a “number” is assigned to each record (row). In the access statistical information 116 of FIG. 5, for example, in a certain cache miss set, the address where a cache miss has occurred is 0x00800010, the address appears 892 times within the same aggregation section, and the appearance timing of the address in the aggregation section The average and standard deviation are recorded as 20032 nanoseconds and 270, respectively.

  As described above, the cache control analysis unit 115 calculates a predetermined number (for example, N ÷ 5) or more from a plurality of cycles (cycle 1 to cycle N) of the cycle processing from the access trace information 114 stored in the storage device. A cache miss that occurs at the same address due to a timing difference within a predetermined range (for example, a 10 microsecond counting section) in a cycle is extracted as a cache miss set by the processing device. The cache control analysis unit 115 calculates, for each extracted cache miss set, a statistical amount of the timing at which a cache miss has occurred by the processing device. For each cache miss set, the cache control analysis unit 115 generates and stores access statistical information 116 indicating the average and standard deviation of the calculated timing (an example of a statistic) and the address where the cache miss occurs, by the processing device. Store in the device.

  The timing correction unit 117 determines an appropriate timing for prefetching based on the access statistical information 116. The timing correction unit 117 has memory access delay time and cache control processing delay time as parameters. It is assumed that the storage device stores delay time information indicating the memory access delay time and the cache control processing delay time in advance. The memory access delay time is the time required for data required by the memory controller 112 to be loaded from the RAM 111 to the shared cache 110 when a cache miss occurs (the time for accessing the RAM 111 when a cache miss occurs) ) And is determined by the specifications of the RAM 111 and the target. The cache control processing delay time is the maximum time (time for prefetch processing) required for a series of processing related to one prefetch processing on the sub-core 102 side. Here, when the access statistical information 116 is used, the prefetch time for the first cache miss [i] (i is an integer satisfying i> 1) is “average elapsed time− (standard deviation × range correction value) − ((i −1) × memory access delay time) −cache control processing delay time ”. Here, “(i−1) × memory access delay time” is subtracted when the cache control scenario 107 is executed, [i−1] through [1] to [i−1] prefetches. This is because the number of cache misses does not occur. The range correction value indicates a variation range allowed when the timing deviation is a normal distribution, and is appropriately adjusted by tuning.

  If the [i] -th prefetch time is earlier than “[i−1] -th prefetch time + cache control processing delay time”, the timing correction unit 117 sets “cache control processing delay time− ( [I-1] th prefetch time- [i-1] th prefetch time) ". When the memory access delay time is 150 nanoseconds, the cache control processing delay time is 300 nanoseconds, and the range correction value is 2, in the example of FIG. 5, the second prefetch time is 76554 nanoseconds− (391 × 2) -(1 x 150 nanoseconds)-300 nanoseconds = 75322 nanoseconds The third prefetch time is 76818 nanoseconds-(350 x 2)-(1 x 150 nanoseconds)-300 nanoseconds = 75518 nanoseconds Since the obtained difference is less than the cache control processing delay time at 196 nanoseconds, the second prefetch time is corrected to 75218 nanoseconds that is 104 nanoseconds ahead.

  The timing correction unit 117 converts the finally obtained prefetch time into a unit of the clock counter 108 used for measuring the elapsed time from the start of the periodic processing, and generates the cache control scenario 107.

  FIG. 6 is a table showing an example of the cache control scenario 107 when the frequency of the clock counter 108 is 100 MHz.

  The cache control scenario 107 is information indicating the timing and address for executing prefetch processing for each cache miss set. In the example of FIG. 6, the timing for executing the prefetch processing is recorded in the “prefetch timing” column, and the address for executing the prefetch processing is recorded in the “prefetch location” column. “Number” represents the order in which prefetch processing is performed. In the cache control scenario 107 of FIG. 6, for example, it is indicated that the prefetch process is executed for the address 0x00800EC0 at the timing when the clock counter 108 counts 752180 (corresponding to 75218 nanoseconds).

  As described above, the timing correction unit 117 stores the average and standard deviation of the timing indicated by the access statistical information 116 generated by the cache control analysis unit 115 for each cache miss set extracted by the cache control analysis unit 115 and the memory. The timing for executing the prefetch processing is set by the processing device from the cache control processing delay time and the memory access delay time indicated by the delay time information stored in the device. At this time, the timing correction unit 117 stores the average and standard deviation of the timing indicated by the access statistical information 116 generated by the cache control analysis unit 115 together with the address for executing the i-th prefetch process, and the storage device. The i-th prefetch processing timing is set from the cache control processing delay time indicated by the delay time information and the memory access delay time indicated by i-1 times the delay time information stored in the storage device. To do. In addition, the timing correction unit 117 sets (corrects) the timing so that the difference between the i-th prefetch processing timing and the (i−1) -th prefetch processing timing is equal to or longer than the cache control processing delay time. ). Then, the timing correction unit 117 generates a cache control scenario 107 indicating the set timing and the address indicated by the access statistical information 116 generated by the cache control analysis unit 115 by the processing device.

  Specifically, for each cache miss set extracted by the cache control analysis unit 115, the timing correction unit 117 determines the timing indicated with the address A [i] in the access statistical information 116 generated by the cache control analysis unit 115. The timing P [i] at which the i-th prefetch process is executed from the average M [i] and standard deviation V [i], the predetermined correction value C, the cache control processing delay time D, and the memory access delay time E Is set to P [i] = M [i] − (V [i] × C) − ((i−1) × E) −D. At this time, if the difference between the timing P [i] and the timing P [i−1] at which the i−1th prefetch processing is executed is not equal to or greater than the cache control processing delay time D, the timing correction unit 117 performs the timing P [i]. -1] is corrected by the processing device at a timing earlier than the cache control processing delay time D- (timing P [i] -timing P [i-1]).

  Note that the timing correction unit 117 may set the timing for executing the prefetch process based only on the average of the timings indicated by the access statistical information 116. In this case, specifically, the timing correction unit 117 sets the timing P [i] to P [i] = M [i] − ((i−1) × E) −D. Further, the timing correction unit 117 may set the timing for executing the prefetch process based on other statistics (for example, the minimum value, the intermediate value, and the maximum value) of the timing indicated by the access statistical information 116.

  Next, a phase for executing the cache control scenario 107 will be described.

  FIG. 7 is a flowchart showing the operation of the cache control unit 109.

  When the execution of the sub-core 102 is started, the cache control unit 109 waits by polling until the execution start notification of the periodic task 103 from the synchronization unit 106 on the main core 101 side is written in the inter-core shared memory (Step S110). S101). When the cache control unit 109 detects the execution start notification, the cache control unit 109 resets the counter value to the clock counter 108 and starts counting up again from 0 (step S102). Next, the cache control unit 109 reads one entry from the beginning of the cache control scenario 107, and holds the prefetch timing value in the internal register (step S103). After that, the cache control unit 109 reads the counter value from the clock counter 108 (step S104), and compares it with the held prefetch timing value (step S105). While the counter value is smaller than the prefetch timing value, the cache control unit 109 checks the shared memory for an asynchronous process start notification from the synchronization unit 106 (step S106), and if not, compares the counter value after reading the counter value again. This process (steps S104 and S105) is repeated. If there is an asynchronous process start notification, the cache control unit 109 suspends the counter (step S107), waits for the asynchronous process to end (step S108), and displays the counter stopped after receiving the notification. The process is resumed (step S109), and the process returns to the counter reading process (step S104).

  When the counter value read from the clock counter 108 exceeds the prefetch timing, the cache control unit 109 reads the data at the address specified at the prefetch location as the prefetch process (step S110). As a result, if the data does not exist on the shared cache 110, the data is loaded from the RAM 111 to the shared cache 110 by the memory controller 112. After performing the prefetch process, the cache control unit 109 determines whether or not the previously processed entry is the last entry of the cache control scenario 107 (step S111). Step S103 and subsequent steps are repeated. If all entries have been processed, the cache control unit 109 returns to before the execution start notification waiting for the periodic task 103 (step S101) and prepares for the start of the next period. The cache control processing delay time used as a parameter by the timing correction unit 117 is a loop in which the prefetch is performed after the prefetch timing and the counter value are compared, and then the next entry is read and the counter value is compared again. It is calculated as the time required for a series of processing until returning.

  As described above, the cache control unit 109 performs prefetch processing on the address indicated by the cache control scenario 107 by the processing device at the timing indicated by the cache control scenario 107 generated by the timing correction unit 117.

  Hereinafter, the effect which this embodiment has will be described.

  Prefetching a memory cache is meaningless if the timing is delayed, and if it is too early, there is a risk of disturbing normal cache behavior, so it is important to consider these characteristics. According to the present embodiment, the timing correction unit 117 performs the timing correction considering the performance improvement with respect to the statistically obtained timing, so that the timing correction unit 117 is appropriate without delaying the periodic processing on the main core 101 side. Since prefetching is performed at the timing, occurrence of a cache miss with respect to the shared cache 110 is suppressed on the main core 101 side, and the execution performance of the periodic processing can be improved.

  As described above, in the present embodiment, the cache control device 100 collects the access trace information 114 in which the address causing the cache miss is recorded along with the elapsed time from the cycle start time in the periodic processing. Then, the cache control device 100 generates access statistical information 116 obtained by extracting a cache miss address that is common or frequently used in each cycle from the access trace information 114, and determines an appropriate prefetch timing to solve this. A cache control scenario 107 is generated. At this time, the cache control apparatus 100 increases the accuracy of the prefetch timing by sequentially applying the correction for the performance improvement due to the change from the cache miss to the cache hit due to the prefetch to the subsequent prefetch timing.

  In the present embodiment, the cache control device 100 is specified at a predetermined timing starting from the cycle start time using the cache control scenario 107 corresponding to the cycle processing in parallel with the execution of the cycle processing. A cache control unit 109 is provided, which preloads addresses to load data to be accessed from periodic processing onto the cache in advance. The cache control unit 109 starts execution of the cache control scenario 107 when notified of the start of the periodic processing from the task that executes the periodic processing or the synchronization unit 106 incorporated in the OS 104, so that an appropriate timing can be set for each cycle. Prefetch with.

  Further, in the present embodiment, the cache control device 100 uses a multi-core processor, performs periodic processing in the main core 101, executes the cache control unit 109 in the sub-core 102, and sets the address specified at a predetermined timing. By accessing, data accessed from the periodic processing of the main core 101 is loaded on the shared cache 110 between the cores in advance.

  Furthermore, in the present embodiment, when a high-priority asynchronous process that takes away the right to execute a periodic process is executed, the synchronization unit 106 notifies the start and end of the asynchronous process. The cache control unit 109 that has received the notification is characterized by temporarily suspending the execution of the cache control scenario 107 while the asynchronous process is being executed.

  As described above, according to the present embodiment, prefetching is performed at an appropriate timing so that the data accessed every cycle always becomes a cache hit in a large-scale periodic process exceeding the range covered by the cache. It becomes possible. In the present embodiment, access statistical information 116 that analyzes the cache miss occurrence location common to each cycle of the periodic processing is created from the access trace information 114 that is monitored and accumulated by monitoring the memory access behavior, and the prefetch timing is based on this. The cache control describes the appropriate timing in the cycle by sequentially applying the correction of the timing for the performance improvement due to the cache fetch to the cache hit as a result of the prefetch when determining the cache. By generating a scenario 107 and performing prefetching based on the scenario 107, it is possible to suppress cache misses and improve execution performance.

Embodiment 2. FIG.
In the present embodiment, differences from the first embodiment will be mainly described.

  The configuration of the cache control apparatus 100 according to the present embodiment is the same as that of the first embodiment shown in FIG.

  FIG. 8 is a table showing an example of information defining a synchronization event.

  This information arbitrarily defines an event (at least one synchronous event that occurs at a fixed timing in each of the periodic processing cycles 1 to N) that always occurs at a fixed timing each time in relation to the progress of the periodic operation. Registered in the synchronization unit 106. As a synchronous event, for example, a transition between specific tasks, a specific system call such as a semaphore operation or ioctl, or a checkpoint trace API (Application / Program / Interface) arbitrarily inserted at a passing point of a task is used. Can be used. In the example of FIG. 8, the synchronization events are defined in the order of occurrence together with the event IDs for identifying these synchronization events.

  The operation when the synchronization unit 106 detects a synchronization event from the information of the dispatcher 105 differs depending on whether the cache control scenario 107 is generated or the cache control scenario 107 is executed.

  First, in the phase of generating the cache control scenario 107, when detecting the synchronization event, the synchronization unit 106 determines in advance a specific memory area in which the cache is invalidated (the address of the RAM 111 is excluded from the cache target). The event ID of the synchronization event is written to the synchronization address). In the memory access monitoring unit 113, the time when the start time of the periodic processing is set to 0, the target address that caused the cache miss, and any one of the synchronization addresses in which the event ID of the synchronization event is written, Furthermore, if it is a synchronous address, a set with the data (event ID) written in the address is recorded as the access trace information 114.

  FIG. 9 is a table showing an example of the access trace information 114.

  In the example of FIG. 9, the address (synchronization address) for writing the event ID is set to 0xFF000000. In the example of FIG. 9, as in the example of FIG. 3, the timing when a cache miss and a synchronization event occur is in the “time (millisecond)” column, and the address and synchronization address where the cache miss occurs are in the “miss occurrence location” column. Is recorded. Furthermore, the event ID written in the synchronous address when the synchronous event occurs is recorded in the “write data” column. In the access trace information 114 shown in FIG. 9, as in the first embodiment shown in FIG. 3, for example, it is recorded that a cache miss for the address 0x00800010 occurs at a timing of 20380 nanoseconds in a certain cycle. ing. In addition, it is recorded that an event ID of 0x00000001 is written to an address of 0xFF000000 at a timing of 80247 nanoseconds in a certain cycle. That is, it is recorded that the synchronization event for acquiring the semaphore 1 shown in FIG. 8 occurs at a timing of 80247 nanoseconds in a certain cycle. In addition, it is recorded that an event ID of 0x00000002 is written to an address of 0xFF000000 at a timing of 129526 nanoseconds in a certain cycle. That is, it is recorded that a synchronous event for calling ioctl that controls the device 3 shown in FIG. 8 occurs at a timing of 129526 nanoseconds in a certain cycle.

  Similarly to the first embodiment, the timing correction unit 117 generates a cache control scenario 107 indicating the set timing and the address indicated by the access statistical information 116 generated by the cache control analysis unit 115 by the processing device. Synchronization information indicating prefetch processing to be executed before a synchronization event occurs is generated by the processing device. At this time, the timing correction unit 117 writes the timing and address for executing the prefetch processing in the same format as that recorded in the cache control scenario 107, and the synchronization unit 106 writes the synchronization event at the synchronization address at the timing when the synchronization event occurs. Are recorded in the cache control scenario 107. Thereby, the timing correction unit 117 generates synchronization information as a part of the cache control scenario 107.

  FIG. 10 is a table showing an example of the cache control scenario 107.

  In the example of FIG. 10, the timing for executing the prefetch process and the timing for generating the synchronization event are in the “prefetch timing / synchronization timing” column, and the address for executing the prefetch process and the event ID of the synchronization event are “prefetch location / checkpoint”. Recorded in the column. “Number” represents the order in which prefetch processing is performed and the order in which synchronization events occur. In the cache control scenario 107 in FIG. 10, as in the first embodiment, for example, when the clock counter 108 counts 755180 (corresponding to 75518 nanoseconds), the prefetch process is executed for the address 0x00800EE0. It is shown. Further, for example, it is indicated that an event ID of 0x00000001 is written to an address of 0xFF000000 at the timing when the clock counter 108 counts 800080 (corresponding to 8000000 nanoseconds). That is, it is shown that a synchronization event corresponding to an event ID of 0x00000001 occurs at the timing when the clock counter 108 counts 800080 (corresponding to 8000000 nanoseconds). In the present embodiment, the timing at which the synchronization event occurs is used as a checkpoint. In the example of FIG. 10, the fourth and tenth entries are checkpoints. In the present embodiment, since the cache control scenario 107 includes two types of entries, prefetch and checkpoint, a “type” column is also provided for identifying these.

  The checkpoint synchronization timing uses an average elapsed time calculated by statistical processing similar to that of the cache control analysis unit 115. However, since synchronization events indicating checkpoints need to occur in an order determined in each cycle, the threshold of the number of times must be N, which is the same as the number of cycles targeted for statistics. Since the access trace information 114 includes the memory access overhead due to the acquisition of the synchronization event, the prefetch time for the [i] th cache miss is “average elapsed time− (standard deviation × range correction value)”. − ((I−1 + number of occurrences of synchronization event) × memory access delay time) −cache control processing delay time ”. The reason for subtracting “synchronous event occurrence count” × “memory access delay time” is that when the cache control scenario 107 is executed, the synchronization unit 106 does not write the event ID to the synchronous address, [i−1] This is because memory accesses corresponding to the number of checkpoints until the prefetch are not generated.

  On the other hand, in the phase in which the cache control scenario 107 is executed, when the synchronization unit 106 detects a synchronization event, the synchronization unit 106 manages the execution phase number managed inside the synchronization unit 106 and counted up in response to the occurrence of the synchronization event. The sub-core 102 is notified through the shared memory or the like.

  FIG. 11 is a flowchart showing the operation of the cache control unit 109.

  Comparing the flowchart of FIG. 11 with the flowchart of FIG. 6, in this embodiment, the process of phase synchronization 1 (step S201) and phase synchronization 2 (step S202) is added due to the addition of the checkpoint synchronization process. Has been.

  FIG. 12 is a flowchart showing details of the phase synchronization 1.

  The cache control unit 109 first checks the type of the entry read from the cache control scenario 107 to identify whether it is a checkpoint or prefetch timing (step S211). The scenario phase number managed in step 1 is incremented by one (step S212). Next, the cache control unit 109 refers to the inter-core shared memory, acquires the execution phase number notified from the synchronization unit 106 of the main core 101 (step S213), and compares it with the scenario phase number (step S214). At this time, if the scenario phase number is larger than the execution phase number, execution of the scenario has preceded, so the cache control unit 109 polls the inter-core shared memory until the numbers match (steps S213 and S214). If the execution phase number is greater than or equal to the scenario phase number, the cache control unit 109 sets the value of the synchronization timing set in the checkpoint entry in the clock counter 108 (step S215). From this, if the periodic processing of the main core 101 reaches the check point between the checkpoint synchronization timing of the cache control scenario 107 and the prefetch timing immediately before, the actual operation of the main core 101 and the scenario of the subcore 102 are detected. Will coincide with each other. As described above, the cache control unit 109 works to fill the delay time as much as possible if the actual operation is preceded.

  FIG. 13 is a flowchart showing details of the phase synchronization 2.

  The cache control unit 109 first refers to the inter-core shared memory, acquires the execution phase number notified from the synchronization unit 106 of the main core 101 (step S221), and compares it with the scenario phase number managed internally Is performed (step S222). If the scenario phase number is smaller than the execution phase number, the actual operation precedes the scenario execution, so the entry of the cache control scenario 107 is forcibly advanced to the next entry of the checkpoint (step S223). Further, the cache control unit 109 sets the value of the synchronization timing set in the checkpoint entry in the clock counter 108 (step S224). If the scenario phase number is greater than or equal to the execution phase number, the process exits without doing anything here. If the scenario execution is preceded, the timing is corrected in the next processing of phase synchronization 1 (step S201), and therefore, this need not be considered here.

  As described above, when a synchronization event occurs, the cache control unit 109 executes the prefetch process after the next based on the timing at which the synchronization event has occurred and the synchronization information generated by the timing correction unit 117. Is adjusted by the processing device.

  Hereinafter, the effect which this embodiment has will be described.

  According to the present embodiment, by accumulating timing shifts due to subtle fluctuations in the cache hit rate, the problem that a shift occurs between actual operation and scenario execution as periodic processing progresses, By finely correcting the scenario execution position and timing in accordance with the checkpoint timing notified from the synchronization unit 106, it is possible to suppress the occurrence of deviation and maintain high accuracy of the prefetch timing until the latter half of the cycle processing cycle. It becomes possible.

  As described above, in the present embodiment, the cache control apparatus 100 provides the synchronization unit 106 in the OS 104 and refers to information on the dispatcher 105 that manages execution contexts such as tasks, interrupt handlers, and system calls. Then, the cache control unit 109 is notified of the point in time when the specific execution context is switched as a checkpoint. The cache control scenario 107 further includes information on checkpoints, and by comparing the information with the checkpoints, the execution position or timing of the cache control scenario 107 is corrected according to the actual progress of the periodic process, and The deviation from the scenario is suppressed and the prefetch timing accuracy is kept high.

  As described above, according to the present embodiment, the actual behavior and the timing of the cache control scenario 107 are obtained by synchronizing at the check point at the cycle start time, the execution context switching time, etc., the entrance and exit of asynchronous processing, and the like. It is possible to prevent the processing from proceeding with the deviation.

Embodiment 3 FIG.
In the present embodiment, differences from the first embodiment will be mainly described.

  FIG. 14 is a block diagram showing a configuration of the cache control apparatus 100 according to the present embodiment.

  In FIG. 14, the cache control apparatus 100 includes a scenario selection unit 118 and an execution mode reference unit 119 in the sub-core 102 in addition to the same components as those in the first embodiment.

  In the present embodiment, it is assumed that there are a plurality of types of periodic processing. The type of the periodic process is represented as an execution mode 120. The execution mode 120 is a variable that is referred to by the periodic task 103 at the time of execution, and is a variable related to determination of specific processing, control, and calculation contents. In addition, the execution mode 120 is arranged at a position that can be referred to from the sub-core 102 side by a method such as memory sharing.

  The timing correction unit 117 generates an individual cache control scenario 107 according to the execution mode 120.

  The scenario selection unit 118 selects the cache control scenario 107 generated by the timing correction unit 117 according to the execution mode 120 (switches a plurality of cache control scenarios 107). Specifically, the scenario selection unit 118 acquires the execution mode 120 that is data managed on the main core 101 side via the execution mode reference unit 119 in accordance with a request from the cache control unit 109, and the execution mode. A cache control scenario 107 corresponding to 120 is selected.

  The cache control unit 109 executes prefetch processing for the address indicated by the cache control scenario 107 at the timing indicated by the cache control scenario 107 selected by the scenario selection unit 118. That is, the cache control unit 109 executes the same cache control process as in the first embodiment in accordance with the cache control scenario 107 selected by the scenario selection unit 118.

  In the present embodiment, in the phase of generating the cache control scenario 107, the cache control apparatus 100 performs the acquisition from the access trace information 114 to the generation of the cache control scenario 107 a plurality of times for each execution mode 120. Each cache control scenario 107 is generated. In addition, the cache control device 100 holds a correspondence table between the execution mode 120 and the cache control scenario 107 in the storage device as an internal data structure of the scenario selection unit 118.

  FIG. 15 is a flowchart showing the operation of the cache control unit 109.

  A processing request (step S301) from the cache control unit 109 to the scenario selection unit 118 is made after a counter reset (step S102) as shown in FIG. Therefore, even if the execution of the scenario selection unit 118 or the execution mode reference unit 119 called ahead takes some time, the prefetch timing described in the cache control scenario 107 is not affected.

  In the phase of executing the cache control scenario 107, when the scenario selection unit 118 is called from the cache control unit 109, the scenario selection unit 118 performs the periodic processing currently being executed on the main core 101 side with respect to the execution mode reference unit 119. Queries the execution mode 120. The execution mode reference unit 119 acquires the execution mode 120 held as a variable on the main core 101 side via the shared memory, and passes it to the scenario selection unit 118. At this time, if the processing content of the periodic processing is determined by a combination of a plurality of variables, each of the possible combinations can be recognized as a different execution mode 120, and a cache control scenario 107 corresponding to the execution mode 120 can be determined in advance. Have it ready. The scenario selection unit 118 that has acquired the execution mode 120 passes a pointer indicating the first entry of the scenario corresponding to the execution mode 120 to the cache control unit 109.

  Hereinafter, the effect which this embodiment has will be described.

  According to the present embodiment, the application range of the cache control method using the cache control scenario 107 can be expanded, so that it is possible to expect an improvement in processing performance in more periodic processes.

  As described above, in the present embodiment, the cache control device 100 prepares a plurality of cache control scenarios 107 corresponding to the execution mode 120 when the content of the periodic processing changes according to the execution mode 120. The execution mode reference unit 119 refers to the execution mode 120 as appropriate, and the scenario selection unit 118 switches the cache control scenario 107 according to the result.

  As described above, according to the present embodiment, when the contents of the periodic processing are different corresponding to the plurality of execution modes 120, the cache control scenario 107 is prepared for each execution mode 120, and the execution mode By switching the cache control scenario 107 when 120 changes, the cache control method using the cache control scenario 107 can be applied to various periodic processes.

  As mentioned above, although embodiment of this invention was described, you may implement combining 2 or more embodiment among these. Alternatively, one of these embodiments may be partially implemented. Or you may implement combining two or more embodiment among these partially.

  100 cache controller, 101 main core, 102 sub core, 103 periodic task, 104 OS, 105 dispatcher, 106 synchronization unit, 107 cache control scenario, 108 clock counter, 109 cache control unit, 110 shared cache, 111 RAM, 112 memory controller , 113 Memory access monitoring unit, 114 Access trace information, 115 Cache control analysis unit, 116 Access statistical information, 117 Timing correction unit, 118 Scenario selection unit, 119 Execution mode reference unit, 120 Execution mode, 121 LCD, 122 Keyboard, 123 Mouse, 124 FDD, 125 CDD, 126 printer, 131 CPU, 132 bus, 133 ROM, 135 communication board, 140 HDD, 143 programs, 144 files.

Claims (9)

A delay indicating a cache control processing delay time that is a time for prefetch processing for pre-reading data from the main memory to the cache memory, and a memory access delay time that is a time for accessing the main memory when a cache miss occurs A storage device for preliminarily storing time information and access trace information indicating the timing and address at which a cache miss occurs for each cache miss occurring in a plurality of cycles of periodic processing executed at fixed intervals; and data processing And a processing device for performing
From the access trace information stored in the storage device, a cache miss that occurs at the same address with a timing difference within a predetermined range in a predetermined number of cycles or more among the plurality of cycles is extracted as a cache miss set by the processing device. For each extracted cache miss set, the processing device calculates the statistics of the timing at which a cache miss has occurred, and provides access statistics information indicating the calculated timing statistics and the address at which the cache miss has occurred. Cache control analysis unit generated by
For each cache miss set extracted by the cache control analysis unit, the cache control indicated by the timing statistics indicated by the access statistical information generated by the cache control analysis unit and the delay time information stored in the storage device Based on the processing delay time and the memory access delay time, the processing device sets the timing for executing the prefetch processing, and the processing device generates a cache control scenario indicating the set timing and the address indicated by the access statistical information. A cache control apparatus comprising: a cache control scenario generation unit.   The cache control scenario generation unit is the access statistical information generated by the cache control analysis unit, and is a timing statistic indicated together with an address at which i (i is an integer satisfying i> 1) the prefetch process is performed, The cache control processing delay time indicated by the delay time information stored in the storage device and the memory access delay time indicated by the delay time information stored in the storage device are multiplied by i−1. The cache control device according to claim 1, wherein timing for executing the prefetch process is set.   The cache control scenario generator generates a cache control process delay in which a difference between a timing at which the i th prefetch process is executed and a timing at which the i−1 th prefetch process is executed is indicated by delay time information stored in the storage device 3. The cache control device according to claim 2, wherein the timing is set so as to be equal to or longer than the time. The cache control analysis unit calculates the average and standard deviation of the timing at which the cache miss occurs as the statistics of the timing at which the cache miss occurs for each extracted cache miss set, and calculates the access statistics information. Generate access statistics that show the average and standard deviation of the timing and the address where the cache miss occurred,
For each cache miss set extracted by the cache control analysis unit, the cache control scenario generation unit generates an average M [i of timings indicated together with the address A [i] in the access statistical information generated by the cache control analysis unit. ], The standard deviation V [i], the predetermined correction value C, the cache control processing delay time D and the memory access delay time E indicated by the delay time information stored in the storage device, and the i th prefetch processing The timing P [i] for executing the operation is set to P [i] = M [i] − (V [i] × C) − ((i−1) × E) −D. 4. The cache control device according to 2 or 3. The periodic process includes at least one synchronization event that occurs at a constant timing in each of the plurality of periods,
The cache control scenario generation unit further generates synchronization information indicating a context between a timing at which a synchronization event occurs and a timing at which a prefetch process is executed, by the processing device,
The cache control device further includes:
When the prefetch processing is executed by the processing device for the address indicated by the cache control scenario at the timing indicated by the cache control scenario generated by the cache control scenario generation unit, and the synchronization event occurs, And a cache control unit configured to adjust a timing for executing a prefetch process from the next time onward based on timing at which an event occurs and synchronization information generated by the cache control scenario generation unit. Item 5. The cache control device according to any one of Items 1 to 4. The cache control device further includes:
When a synchronization event occurs, it has a synchronization unit that writes data to a fixed address,
The cache control scenario generation unit is configured to record a synchronization event in the same format as that for recording the set timing and the address indicated by the access statistical information generated by the cache control analysis unit in the cache control scenario. 6. The cache control device according to claim 5, wherein the synchronization information is generated as a part of the cache control scenario by recording data written by the synchronization unit at the timing in the cache control scenario. . There are multiple types of periodic processing,
The cache control scenario generation unit generates an individual cache control scenario according to the type of periodic processing,
The cache control device further includes:
A scenario selection unit that selects a cache control scenario generated by the cache control scenario generation unit according to the type of periodic processing,
7. The cache control unit according to claim 1, wherein the cache control unit executes prefetch processing for an address indicated by the cache control scenario at a timing indicated by the cache control scenario selected by the scenario selection unit. The cache control device according to any one of the above. Cache control processing delay time, which is a time for prefetch processing in which data is read from the main memory to the cache memory in advance, and memory access delay time, which is the time for accessing the main memory when a cache miss occurs Delay time information indicating, and access trace information indicating the timing and address at which a cache miss occurs for each cache miss occurring in a plurality of cycles of periodic processing executed at regular intervals,
The processor extracts from the access trace information stored in the storage device, as a cache miss set, cache misses that occur at the same address due to a timing difference within a predetermined range within a predetermined number of cycles among the plurality of cycles. Then, for each extracted cache miss set, calculate the statistics of the timing when the cache miss occurred, and generate access statistics information indicating the calculated timing statistics and the address where the cache miss occurred,
A cache control processing delay time and a memory indicated by the timing statistics indicated by the generated access statistical information and delay time information stored in the storage device for each of the extracted cache miss sets. A cache control method characterized by setting a timing for executing prefetch processing from an access delay time, and generating a cache control scenario indicating the set timing and an address indicated by the access statistical information. A delay indicating a cache control processing delay time that is a time for prefetch processing for pre-reading data from the main memory to the cache memory, and a memory access delay time that is a time for accessing the main memory when a cache miss occurs A storage device for preliminarily storing time information and access trace information indicating the timing and address at which a cache miss occurs for each cache miss occurring in a plurality of cycles of periodic processing executed at fixed intervals; and data processing A cache control program executed by a computer comprising a processing device for performing
From the access trace information stored in the storage device, a cache miss that occurs at the same address with a timing difference within a predetermined range in a predetermined number of cycles or more among the plurality of cycles is extracted as a cache miss set by the processing device. For each extracted cache miss set, the processing device calculates the statistics of the timing at which a cache miss has occurred, and provides access statistics information indicating the calculated timing statistics and the address at which the cache miss has occurred. Cache control analysis processing generated by
For each cache miss set extracted by the cache control analysis process, the cache control indicated by the timing statistic indicated by the access statistical information generated by the cache control analysis process and the delay time information stored in the storage device Based on the processing delay time and the memory access delay time, the processing device sets the timing for executing the prefetch processing, and the processing device generates a cache control scenario indicating the set timing and the address indicated by the access statistical information. A cache control program that causes a computer to execute cache control scenario generation processing.

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