CN115576872B - Access detection method and device for multi-level cache - Google Patents
Access detection method and device for multi-level cache Download PDFInfo
- Publication number
- CN115576872B CN115576872B CN202211442535.5A CN202211442535A CN115576872B CN 115576872 B CN115576872 B CN 115576872B CN 202211442535 A CN202211442535 A CN 202211442535A CN 115576872 B CN115576872 B CN 115576872B
- Authority
- CN
- China
- Prior art keywords
- cache
- level
- hit
- data
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The application relates to the technical field of computers, and provides a method and a device for access detection of a multi-level cache. The method comprises the following steps: according to the priority sequence of each level of cache, the access requests of any thread are sequentially sent to each level of cache from high to low, and the cache data hit results of the current cache receiving the access requests to the access requests are recorded during each sending; according to the hit results of the cache data of each level of cache, obtaining hit result statistical data corresponding to the access request; according to the hit result statistical data of each access request of the thread, determining the cache data hit rate corresponding to the cache of the thread at each level, and determining the access efficiency of the thread at each level according to the cache data hit rate. The access detection method for the multi-level cache, provided by the embodiment of the application, can accurately detect the access efficiency of any thread to each level of cache.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for detecting access to a multi-level cache.
Background
In many-core systems, such as multi-core GPU and multi-core CPU systems, both CPU and GPU have a multi-level cache structure, each level of cache has different priorities, each level of cache is also divided into an instruction cache and a data cache according to needs, and a thread of any core can perform read-write operation on the multi-level cache to reduce the situation that cache data cannot be obtained. Specifically, when a thread reads an instruction or reads and writes data, the caches at different levels are sequentially accessed according to the sequence of the priority levels from high to low so as to read the cache data. In the process that any thread accesses the multiple levels of caches, the access efficiency of each level of cache is crucial to the efficiency of analyzing software and hardware, and therefore how to accurately detect the access efficiency of any thread to each level of cache is a problem which needs to be solved urgently at present.
Disclosure of Invention
The present application is directed to solving at least one of the technical problems occurring in the related art. Therefore, the access detection method for the multi-level caches can accurately detect the access efficiency of any thread to each level of cache.
The application also provides an access detection device of the multi-level cache.
The application also provides an electronic device.
The application also provides a computer readable storage medium.
The method for detecting access of the multi-level cache according to the embodiment of the first aspect of the application is applied to a processor and comprises the following steps:
according to the priority sequence of each level of cache, sequentially sending the access request of any thread from high to low to each level of cache, and recording the cache data hit result of the current cache receiving the access request to the access request during each sending;
according to the cache data hit results of all levels of caches, obtaining hit result statistical data corresponding to the access request;
according to the hit result statistical data of each access request of the thread, determining the cache data hit rate corresponding to each level of cache of the thread, and determining the access efficiency of the thread in each level of cache according to the cache data hit rate.
According to an embodiment of the present application, further comprising:
and determining that the cache data hit result is that cache data corresponding to the access request exists in the current cache, and stopping sending the access request to a next-level cache.
According to an embodiment of the present application, the obtaining of hit statistical data corresponding to the access request according to the cache data hit of each level of cache includes:
according to the cache data hit result of any level of cache, obtaining a hit tag corresponding to any level of cache;
generating feedback information according to the hit tag corresponding to the any level of cache and the delayed data of the access request processed by the any level of cache;
and acquiring hit result statistical data corresponding to the access request according to the feedback information of each level of cache.
According to one embodiment of the present application, the hit tag of any level of cache includes a priority of the cache and tag information corresponding to the cache data hit.
According to an embodiment of the present application, generating feedback information according to the hit tag corresponding to the any level cache and the latency data of the access request processed by the any level cache includes:
generating target information according to the hit tag corresponding to the any level of cache and the delayed data of the access request processed by the any level of cache;
and binding the target information with the access request to generate the feedback information.
According to an embodiment of the present application, the obtaining of hit statistical data corresponding to the access request according to the cache data hit of each level of cache includes:
and synchronizing the cache data hit results of the caches of all levels from low to high level to the first-level cache of the caches of all levels step by step according to the priority sequence of the caches of all levels so as to obtain the hit result statistical data from the first-level cache.
According to an embodiment of the present application, obtaining the hit statistics from the level one cache includes:
acquiring feedback information of each level of cache from the first level of cache;
and combining the feedback information of each level of cache according to the priority of each level of cache to generate the hit result statistical data.
According to an embodiment of the present application, determining a cache data hit rate corresponding to a cache of the thread at each level according to hit result statistical data of each access request of the thread includes:
according to the statistical data of the hit results, obtaining the hit results of the cache data corresponding to any target cache in each level of cache;
and determining the cache data hit rate of the thread in the target cache according to the number of cache data hit results corresponding to the target cache and the number of cache data corresponding to the access request in the cache data hit results corresponding to the target cache.
The access detection device for the multi-level cache according to the embodiment of the second aspect of the application comprises:
the hit result recording module is used for sequentially sending the access request of any thread from high to low to the caches of all levels according to the priority sequence of the caches of all levels, and recording the hit result of the cache data of the current cache receiving the access request to the access request during each sending;
the hit result counting module is used for acquiring hit result statistical data corresponding to the access request according to the cache data hit results of all levels of caches;
and the access efficiency detection module is used for determining the cache data hit rate corresponding to the cache of the thread at each level according to the hit result statistical data of each access request of the thread so as to determine the access efficiency of the thread at each level according to the cache data hit rate.
The electronic device according to the third aspect of the present application includes a processor and a memory storing a computer program, where the processor implements the access detection method of the multi-level cache according to any of the above embodiments when executing the computer program.
The computer-readable storage medium according to the fourth aspect of the present application stores thereon a computer program, which when executed by a processor implements the access detection method for a multi-level cache according to any of the embodiments described above.
The computer program product according to an embodiment of the fifth aspect of the application comprises: the computer program, when executed by a processor, implements a method for access detection of a multi-level cache as described in any of the embodiments above.
One or more technical solutions in the embodiments of the present application have at least one of the following technical effects:
the access request of any thread is sent to each level of cache from high to low in sequence, the hit result of cache data of the access request by the current cache receiving the access request is recorded, the hit result of each cache data is counted, the hit result statistical data corresponding to the access request is obtained, the access efficiency of the thread in each level of cache is determined according to the hit result statistical data of each access request of the thread, the cache data hit rate of each level of cache can be counted through each hit result statistical data, the access efficiency of the thread in each level of cache is accurately determined by using the cache data hit rate, and the accuracy of detecting the access efficiency of any thread to each level of cache can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the present application or prior art, the drawings used in the embodiments or the description of the prior art are briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of an access detection method for a multi-level cache according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an access detection apparatus for a multi-level cache according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the access detection method and apparatus for multi-level cache according to the embodiments of the present application will be described and explained in detail through several specific embodiments.
In one embodiment, an access detection method for a multi-level cache is provided, which is applied to a processor and used for detecting the access efficiency of any thread in the multi-level cache. As shown in fig. 1, the method for detecting access to a multi-level cache according to this embodiment includes:
102, obtaining hit result statistical data corresponding to the access request according to the cache data hit results of all levels of caches;
and 103, determining the access efficiency of the thread in each level of cache according to the hit result statistical data of each access request of the thread.
The access request of any thread is sent to all levels of caches from high to low in sequence, the hit result of the cache data of the access request of the current cache receiving the access request is recorded, the hit result of each cache data is counted, the hit result statistical data corresponding to the access request is obtained, the access efficiency of the thread in all levels of caches is determined according to the hit result statistical data of each access request of the thread, the cache data hit rate of each level of cache can be counted through each hit result statistical data, the access efficiency of the thread in all levels of cache is accurately determined by using the cache data hit rate, and the accuracy of detecting the access efficiency of any thread to all levels of caches can be improved.
In an embodiment, a first-Level Cache (L1-Cache) is usually designed inside each processor core, a next computation group composed of multiple cores shares the same second-Level Cache (L2-Cache), and multiple computation groups also share the same Last-Level Cache (LLC). Each individual processor core has its own Performance monitoring Module, such as a PPM (Performance Monitor Module) Module, for monitoring the processing result of the access request by the cache.
When an execution thread of a certain thread of a processor reads an instruction, namely an access request for obtaining cache data is generated, the cache of each level is sequentially accessed according to the priority sequence of the cache of each level. The first-level cache is accessed first, then the second-level cache is accessed, and finally the last-level cache is accessed until the access of the caches at all levels is completed. When any level of cache is accessed, if cache data corresponding to the access request exist in the level of cache, a cache data hit result of the cache data is generated on the level of cache; and if the cache data corresponding to the access request does not exist in the cache of the level, generating a cache data hit result without the cache data on the cache of the level. Taking accessing the first-level cache as an example, if cache data required by the access request exists in the first-level cache, generating a cache data hit result with the cache data on the first-level cache; otherwise, generating a cache data hit result without cache data.
When the cache data corresponding to the access request is searched from the caches of the respective levels, if the caches of the respective levels need to be traversed each time, the efficiency of obtaining the cache data is affected. Therefore, in an embodiment, the access request of any thread is sequentially sent to the caches at different levels from high to low, and after the access request is sent to the current cache each time and the cache data hit result of the access request for the current cache is recorded, the cache data hit result is detected. If the cache data hit result is that cache data corresponding to the access request does not exist in the current cache, forwarding the access request to a next-level cache; if the cache data hit result indicates that cache data corresponding to the access request exists in the current cache, the cache data hit in the current cache is indicated, and at this time, the sending of the access request to the next-level cache is stopped.
Illustratively, the access request req0 is first sent to the first-level cache, if the cache data cannot be hit in the first-level cache, the access request req0 is taken as a request req1, and the request req1 is sent to the next-level cache, i.e., the second-level cache, and if the cache data is hit in the first-level cache, the sending of the access request to the next-level cache is stopped. If the access request is not received by a certain level of cache, the returned cache data hit result is empty. If the caches in all levels comprise a first-level cache, a second-level cache and a last-level cache, and the first-level cache is hit, the second-level cache and the last-level cache do not receive the access request, and the cache data hit results returned by the second-level cache and the last-level cache are empty, so that the follow-up hit result statistics is not influenced.
When the cache data hit result is determined that the cache data corresponding to the access request exists in the current cache, the access request is stopped being sent to the next-level cache, so that traversing of all levels of caches is not needed every time, and the obtaining efficiency of the cache data is prevented from being influenced.
In an embodiment, after the cache data hit result of each level of cache is obtained, the cache hit result of each level of cache may be fed back to the performance monitoring module of the processor. In order to make statistics on the access efficiency of the cache more convenient and accurate, in an embodiment, after the cache data hit result of any one level of cache is obtained, the hit tag corresponding to the level of cache may be determined according to the cache data hit result. If the cache data hit result is that cache data corresponding to the access request exists, the corresponding hit tag is 0; if the cache data hit result indicates that no cache data corresponding to the access request exists, the corresponding hit tag is 1. Therefore, when the cache data hit result is obtained, only the tag with less data quantity needs to be generated, the whole cache data hit result does not need to be transmitted, the data transmission quantity is reduced, and the data transmission efficiency is improved.
In order to enable the fast determination of the attribution of the obtained hit tag, in an embodiment, the hit tag of any level of cache includes the priority of the cache and tag information corresponding to the cache data hit result. If there is cache data corresponding to the access request in the second level cache, its corresponding hit tag includes the second level cache and tag information 0 to indicate that the second level cache is a hit.
Meanwhile, in order to better detect the access efficiency, when the cache receives an access request, timing is started to count the time for the cache to process the access request. The time spent by the cache from the time the cache receives the access request to the time the cache completes processing the access request is the delay data for processing the access request. After obtaining the hit tag obtained after processing the access request by a certain level of cache and processing the delay data of the access request, the hit tag and the delay data can be combined, and the feedback information of the level of cache can be obtained.
In order to enable the fast determination of the attribution of the feedback information subsequently, so as to accurately count the hit efficiency of each level of cache of the thread, in an embodiment, the target information may be generated according to the hit tag corresponding to any level of cache and the delay data of the access request processed by any level of cache, and the target information is bound with the access request, for example, the target information is combined with the source address in the access request, so as to generate the feedback information including the target information and the source address. Therefore, the feedback information can be determined to which thread the feedback information corresponds to according to the source address, and the condition that cache hits at different levels of a certain thread cannot be accurately counted due to the fact that the feedback information corresponding to the thread cannot be confirmed when a plurality of threads are executed is avoided.
After the feedback information of the cache of the level is obtained, the feedback information of the cache of each level can be fed back to a performance monitoring module of the processor, so that the obtained feedback information of the cache of each level is sorted and counted, and hit result statistical data corresponding to the access request is obtained. The hit statistics include hit tags for the access request at each level of the cache.
The feedback information of each level of cache is fed back to the performance monitoring module of the processor, or the feedback information of each level of cache is directly fed back to the performance monitoring module through respective interfaces. However, this approach requires adding a plurality of interfaces to the performance monitoring module, resulting in an increase in the number of interfaces and an increase in the size of the performance monitoring module, resulting in a possibility of an excessive area of the processor. Therefore, in an embodiment, the obtaining hit result statistics data corresponding to the access request according to the cache data hit results of the caches at different levels includes:
and synchronizing the cache data hit results of the caches of all levels from low to high level to the first-level cache of the caches of all levels step by step according to the priority sequence of the caches of all levels so as to obtain the hit result statistical data from the first-level cache.
In an embodiment, the feedback information of the first-level cache is rsp0, the feedback information of the second-level cache is rsp1, and the feedback information of the last-level cache is rsp2, if the hit tag of the access request req0 in the first-level cache is 1, the access request is sent to the second-level cache as a request req1, and meanwhile, the first-level cache generates the feedback information rsp0; if the hit tag of the access request req1 in the second-level cache is 1, sending the access request as a request req2 to the last-level cache, and simultaneously generating feedback information rsp1 by the second-level cache; if the hit tag of the access request req2 in the last level cache is 0 or 1, the last level cache generates the feedback information rsp2. And then transmitting the feedback information rsp2 from the last-level cache to a second-level cache, then transmitting the feedback information rsp1 and the feedback information rsp2 in the second-level cache from the second-level cache to a first-level cache, and feeding back the feedback information rsp0, the feedback information rsp1 and the feedback information rsp2 to a performance monitoring module by the first-level cache so as to perform sorting statistics on the obtained feedback information of each-level cache and obtain hit result statistical data corresponding to the access request.
Therefore, the number of interfaces of the performance monitoring module does not need to be increased in a step-by-step uploading mode, the increase of the area of the processor can be avoided, and meanwhile, due to the fact that the feedback information comprises the delay data, the finally obtained hit result statistical data can be more accurate in the statistics of the total delay in the step-by-step upward transmission mode of the feedback information.
In an embodiment, after the feedback information of each level of cache is obtained from the first level of cache, in order to make the formed hit result statistical data more convenient to view, the feedback information of each level of cache can be combined according to the priority of each level of cache to generate the hit result statistical data.
Illustratively, the feedback information of the first-level cache includes tag information 1, and the feedback information of the last-level cache includes tag information 0, so that the hit statistical data may include (1,1,0), which facilitates statistics and reduces the possibility of error of the statistical result.
In an embodiment, after the hit result statistical data of each access request in the thread is obtained through the above embodiments, the cache data hit results corresponding to any one target cache in each level of cache may be obtained according to the hit result statistical data, so as to determine the cache data hit rate of the thread in the target cache according to the number of the cache data hit results corresponding to the target cache and the number of cache data hit results corresponding to the target cache, where the cache data hit results are the number of cache data corresponding to the access request.
In an embodiment, the performance monitoring module may support statistics of up to 29 64-bit counters for each thread, and may perform statistics on cache data hits in the hit statistical data after obtaining the hit statistical data. If the thread includes request 1, request 2, and request 3, the hit statistics for request 1 include (1,1,0), the hit statistics for request 2 include (1,0), and the hit statistics for request 3 include (0). At this time, the number of access requests received by the first-level cache is counted to be 3 through a counter, and the corresponding cache data hit result is two misses, namely one hit; the number of the access requests received by the second-level cache is 2, and the corresponding cache data hit result is one miss and one hit; the number of access requests received by the last-level cache is 1, and the corresponding cache data hit result is a hit. At this time, the cache data hit rate of the thread in the first-level cache is determined to be 1/3, the cache data hit rate in the first-level cache is determined to be 1/2, and the cache data hit rate in the first-level cache is determined to be 1. After the cache data hit rate of each level of cache is obtained, the cache data hit rate of each level of cache is combined with the delay data, and then the access efficiency of the thread to a certain level of cache can be obtained. And if the hit rate of the first-level cache data is determined to be 1/3 according to the hit result statistical data of each access request of the thread, and meanwhile, the time length of the delayed data is greater than the preset time length, the access efficiency of the thread to the first-level cache is judged to be low. The specific access efficiency is determined by taking the data hit rate and the delay data obtained when the thread accesses a certain level of cache as a data set, searching the preset data set which is the same as the data set in a data table in which the mapping relation between the data set and each preset efficiency is recorded, and taking the preset efficiency corresponding to the preset data set as the access efficiency of the thread accessing the level of cache.
The following describes the access detection device for a multi-level cache provided in the present application, and the access detection device for a multi-level cache described below and the access detection method for a multi-level cache described above may be referred to in correspondence.
In one embodiment, as shown in fig. 2, there is provided an access detection apparatus for a multi-level cache, including:
the hit result recording module 210 is configured to sequentially send an access request of any thread to each level of cache from high to low according to the priority ranking of each level of cache, and record a cache data hit result of a current cache receiving the access request on the access request every time the access request is sent;
a hit result counting module 220, configured to obtain hit result statistical data corresponding to the access request according to the cache data hit result of each level of cache;
the access efficiency detection module 230 is configured to determine, according to the hit result statistical data of each access request of the thread, a cache data hit rate corresponding to the thread at each level of cache, so as to determine the access efficiency of the thread at each level of cache according to the cache data hit rate.
The access request of any thread is sent to all levels of caches from high to low in sequence, the hit result of the cache data of the access request of the current cache receiving the access request is recorded, the hit result of each cache data is counted, the hit result statistical data corresponding to the access request is obtained, the access efficiency of the thread in all levels of caches is determined according to the hit result statistical data of each access request of the thread, the cache data hit rate of each level of cache can be counted through each hit result statistical data, the access efficiency of the thread in all levels of cache is accurately determined by using the cache data hit rate, and the accuracy of detecting the access efficiency of any thread to all levels of caches can be improved.
In one embodiment, the hit recording module 210 is further configured to:
and determining that the cache data hit result is that cache data corresponding to the access request exists in the current cache, and stopping sending the access request to a next-level cache.
In one embodiment, the hit statistics module 220 is specifically configured to:
according to the cache data hit result of any level of cache, obtaining a hit tag corresponding to any level of cache;
generating feedback information according to the hit tag corresponding to the any level of cache and the delayed data of the access request processed by the any level of cache;
and according to the feedback information of each level of cache, obtaining the hit result statistical data corresponding to the access request.
In one embodiment, the hit tag of any level of cache includes a priority of the cache and tag information corresponding to the cache data hit.
In one embodiment, the hit statistics module 220 is specifically configured to:
generating target information according to the hit tag corresponding to the any level cache and the delayed data of the access request processed by the any level cache;
and binding the target information with the access request to generate the feedback information.
In one embodiment, the hit statistics module 220 is specifically configured to:
and according to the priority sequence of each level of cache, synchronizing the cache data hit results of each level of cache from low to high to the first level of cache in each level of cache step by step so as to obtain the hit result statistical data from the first level of cache.
In one embodiment, the hit statistics module 220 is specifically configured to:
acquiring feedback information of each level of cache from the first level of cache;
and combining the feedback information of the caches of all levels according to the priorities of the caches of all levels to generate the hit result statistical data.
In an embodiment, the access efficiency detecting module 230 is specifically configured to:
according to the statistical data of the hit results, obtaining the hit results of the cache data corresponding to any target cache in each level of cache;
and determining the cache data hit rate of the thread in the target cache according to the number of cache data hit results corresponding to the target cache and the number of cache data corresponding to the access request in the cache data hit results corresponding to the target cache.
Fig. 3 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 3: a processor (processor) 810, a Communication Interface 820, a memory 830 and a Communication bus 840, wherein the processor 810, the Communication Interface 820 and the memory 830 communicate with each other via the Communication bus 840. The processor 810 may invoke computer programs in the memory 830 to perform access detection methods for multi-level caches, including, for example:
according to the priority sequence of each level of cache, sequentially sending the access request of any thread from high to low to each level of cache, and recording the cache data hit result of the current cache receiving the access request to the access request during each sending;
according to the cache data hit results of all levels of caches, obtaining hit result statistical data corresponding to the access request;
according to the hit result statistical data of each access request of the thread, determining the cache data hit rate corresponding to each level of cache of the thread, and determining the access efficiency of the thread in each level of cache according to the cache data hit rate.
In addition, the logic instructions in the memory 830 may be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, an embodiment of the present application further provides a storage medium, where the storage medium includes a computer program, where the computer program may be stored on a non-transitory computer-readable storage medium, and when the computer program is executed by a processor, the computer is capable of performing the access detection method for a multi-level cache provided in the foregoing embodiments, for example, including:
according to the priority sequence of each level of cache, sequentially sending the access request of any thread to each level of cache from high to low, and recording the cache data hit result of the current cache receiving the access request to the access request during each sending;
according to the cache data hit results of all levels of caches, obtaining hit result statistical data corresponding to the access request;
according to the hit result statistical data of each access request of the thread, determining the cache data hit rate corresponding to each level of cache of the thread, and determining the access efficiency of the thread in each level of cache according to the cache data hit rate.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (11)
1. An access detection method for a multi-level cache, applied to a processor, includes:
according to the priority sequence of each level of cache, sequentially sending the access request of any thread from high to low to each level of cache, and recording the cache data hit result of the current cache receiving the access request to the access request during each sending;
according to the cache data hit results of all levels of caches, obtaining hit result statistical data corresponding to the access request;
according to the hit result statistical data of each access request of the thread, determining the cache data hit rate corresponding to each level of cache of the thread, and determining the access efficiency of the thread in each level of cache according to the cache data hit rate.
2. The method of claim 1, further comprising:
and determining that the cache data hit result is that cache data corresponding to the access request exists in the current cache, and stopping sending the access request to a next-level cache.
3. The method according to claim 1, wherein the obtaining hit statistical data corresponding to the access request according to the cache data hit of each level of cache comprises:
according to the cache data hit result of any level of cache, obtaining a hit tag corresponding to any level of cache;
generating feedback information according to the hit tag corresponding to the any level of cache and the delayed data of the access request processed by the any level of cache;
and according to the feedback information of each level of cache, obtaining the hit result statistical data corresponding to the access request.
4. The method according to claim 3, wherein the hit tag of any cache level comprises a priority of the cache and tag information corresponding to the cache data hit result.
5. The method according to claim 4, wherein generating feedback information according to the hit tag corresponding to the any level cache and the delay data of the access request processed by the any level cache comprises:
generating target information according to the hit tag corresponding to the any level of cache and the delayed data of the access request processed by the any level of cache;
and binding the target information with the access request to generate the feedback information.
6. The method according to claim 3 or 4, wherein the obtaining hit statistical data corresponding to the access request according to the cache data hit of each level of cache comprises:
and according to the priority sequence of each level of cache, synchronizing the cache data hit results of each level of cache from low to high to the first level of cache in each level of cache step by step so as to obtain the hit result statistical data from the first level of cache.
7. The method according to claim 6, wherein obtaining the hit statistics from the first level cache comprises:
acquiring feedback information of each level of cache from the first level of cache;
and combining the feedback information of the caches of all levels according to the priorities of the caches of all levels to generate the hit result statistical data.
8. The method according to claim 1, wherein determining a cache data hit rate of the thread corresponding to each level of cache according to hit statistical data of each access request of the thread comprises:
according to the statistical data of the hit results, obtaining the hit results of the cache data corresponding to any target cache in each level of cache;
and determining the cache data hit rate of the thread in the target cache according to the number of cache data hit results corresponding to the target cache and the number of cache data corresponding to the access request in the cache data hit results corresponding to the target cache.
9. An access detection apparatus for a multi-level cache, comprising:
the hit result recording module is used for sequentially sending the access request of any thread from high to low to the caches of all levels according to the priority sequence of the caches of all levels, and recording the hit result of the cache data of the current cache receiving the access request to the access request during each sending;
the hit result counting module is used for acquiring hit result statistical data corresponding to the access request according to the cache data hit results of all levels of caches;
and the access efficiency detection module is used for determining the cache data hit rate corresponding to the cache of the thread at each level according to the hit result statistical data of each access request of the thread so as to determine the access efficiency of the thread at each level according to the cache data hit rate.
10. An electronic device comprising a processor and a memory storing a computer program, wherein the processor implements the method for access detection of a multi-level cache according to any one of claims 1 to 8 when executing the computer program.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a method for access detection of a multi-level cache according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211442535.5A CN115576872B (en) | 2022-11-18 | 2022-11-18 | Access detection method and device for multi-level cache |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211442535.5A CN115576872B (en) | 2022-11-18 | 2022-11-18 | Access detection method and device for multi-level cache |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115576872A CN115576872A (en) | 2023-01-06 |
| CN115576872B true CN115576872B (en) | 2023-03-24 |
Family
ID=84589075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211442535.5A Active CN115576872B (en) | 2022-11-18 | 2022-11-18 | Access detection method and device for multi-level cache |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115576872B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116166575B (en) * | 2023-02-03 | 2024-01-23 | 摩尔线程智能科技(北京)有限责任公司 | Method, device, equipment, medium and program product for configuring access segment length |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373456A (en) * | 2015-11-19 | 2016-03-02 | 英业达科技有限公司 | Memory testing method for reducing cache hit rate |
| CN112148665A (en) * | 2019-06-28 | 2020-12-29 | 深圳市中兴微电子技术有限公司 | Cache allocation method and device |
| CN113094392A (en) * | 2020-01-09 | 2021-07-09 | 北京沃东天骏信息技术有限公司 | Data caching method and device |
| CN113434440A (en) * | 2021-08-27 | 2021-09-24 | 广东省新一代通信与网络创新研究院 | Method and system for reducing memory access delay |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6627629B2 (en) * | 2016-04-14 | 2020-01-08 | 富士通株式会社 | Arithmetic processing device and method of controlling arithmetic processing device |
| JP7041353B2 (en) * | 2018-06-06 | 2022-03-24 | 富士通株式会社 | Arithmetic processing unit and control method of arithmetic processing unit |
-
2022
- 2022-11-18 CN CN202211442535.5A patent/CN115576872B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373456A (en) * | 2015-11-19 | 2016-03-02 | 英业达科技有限公司 | Memory testing method for reducing cache hit rate |
| CN112148665A (en) * | 2019-06-28 | 2020-12-29 | 深圳市中兴微电子技术有限公司 | Cache allocation method and device |
| CN113094392A (en) * | 2020-01-09 | 2021-07-09 | 北京沃东天骏信息技术有限公司 | Data caching method and device |
| CN113434440A (en) * | 2021-08-27 | 2021-09-24 | 广东省新一代通信与网络创新研究院 | Method and system for reducing memory access delay |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115576872A (en) | 2023-01-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20120095728A1 (en) | Data processing apparatus, performance evaluation/analysis apparatus, and performance evaluation/analysis system and method | |
| US10025504B2 (en) | Information processing method, information processing apparatus and non-transitory computer readable medium | |
| US11068266B2 (en) | Handling an input/output store instruction | |
| US10515078B2 (en) | Database management apparatus, database management method, and storage medium | |
| US20140188829A1 (en) | Technologies for providing deferred error records to an error handler | |
| CN115576872B (en) | Access detection method and device for multi-level cache | |
| JP2021524966A (en) | How to verify access to Level 2 cache for multi-core interconnects | |
| CN110910249B (en) | Data processing method and device, node equipment and storage medium | |
| US7962692B2 (en) | Method and system for managing performance data | |
| CN109246234B (en) | Image file downloading method and device, electronic equipment and storage medium | |
| CN109542341B (en) | Read-write IO monitoring method, device, terminal and computer readable storage medium | |
| CN110750498B (en) | Object access method, device and storage medium | |
| KR101748441B1 (en) | Apparatus and Method for detecting false sharing | |
| EP3691765B1 (en) | Method and system for game data processing, server and computer readable storage medium | |
| US8910125B2 (en) | Monitoring software performance | |
| CN105183398B (en) | A kind of storage device, electronic equipment and data processing method | |
| CN114063923A (en) | Data reading method and device, processor and electronic equipment | |
| CN114091384A (en) | Data processing circuit, artificial intelligence chip, data processing method and device | |
| CN104750693B (en) | A kind of implementation method got ready and device | |
| CN108763291B (en) | Data management method and device and electronic equipment | |
| CN112447279A (en) | Task processing method and device, electronic equipment and storage medium | |
| US20220350536A1 (en) | Abort handling by host controller for storage device | |
| CN116560949B (en) | Method, system, equipment and storage medium for realizing data acquisition and reception | |
| US20230333757A1 (en) | Operational feature activation/disabling | |
| CN116483843A (en) | Data processing method, device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |