JP2010212286A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To most principally microfabricate an element by forming a channel region of a nonvolatile element on the slope of the surface of a semiconductor substrate. <P>SOLUTION: A nonvolatile semiconductor storage device includes: a semiconductor substrate having an element forming region 13 segmented by an element isolation region and having a surface formed so that the surface continuously repeats unevenness; a tunnel insulating film 14 formed in the element forming region; floating gates 15 formed via the tunnel insulating film 14 so as to continue to recess and concave portions adjacent in the element forming region and a slope between the recess and concave portions via the tunnel insulating film; an inter-gate insulating film 16 formed on the floating gate; a control gate 11 formed on the inter-gate insulating film; and a diffusion layer 17 formed in the recess portion so as to be adjacent to the floating gate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device such as an EEPROM, and more particularly to a structure of a memory cell of a NAND flash memory.

  Memory cells such as EEPROM usually have a MISFET structure in which a charge storage layer and a control gate are stacked on a semiconductor substrate. This memory cell stores data in a nonvolatile manner by a difference in threshold value between a state where charges are injected into the charge storage layer and a state where charges are discharged. Charge injection and emission are performed by a tunnel current flowing through a tunnel insulating film between the charge storage layer and the substrate channel. The so-called NAND type EEPROM (NAND flash memory), in which a NAND cell unit is configured by connecting multiple memory cells in series in the EEPROM, has fewer select transistors than the NOR type EEPROM (NOR flash memory). That's it. Therefore, NAND flash memory can be more dense than NOR flash memory.

  The erase operation in the NAND flash memory is performed by passing a tunnel current through a tunnel insulating film between the charge storage layer and the substrate channel, and releasing the electronic charge stored in the charge storage layer in advance. In NAND flash memory, in order to increase the number of memory cells to be erased per unit time, erasing is simultaneously performed on a plurality of memory cells. That is, by applying a positive voltage of 10 V or more, for example, 20 V, to the semiconductor well region where the plurality of memory cells are formed, electrons are extracted from the charge storage layers of the plurality of memory cells to the semiconductor well region. On the other hand, writing is performed by injecting electrons into the charge storage layer. Specifically, the channel potential is kept at 0V, and writing is performed by applying a positive voltage of about 18V to 20V to the gate electrode of the memory cell having a charge / discharge capacity smaller than that of the semiconductor well region. As a result, the power can be reduced and the writing operation speed can be increased as compared with the case where the semiconductor well region is charged / discharged.

  Incidentally, in a nonvolatile semiconductor memory device such as a NAND flash memory, the increase in capacity has been achieved so far by miniaturizing memory cells. However, in the conventional memory cell structure, when the memory cell is miniaturized, the channel region is also miniaturized. As a result, problems such as so-called S value deterioration due to the short channel effect and punch-through occur.

  Patent Document 1 discloses a method for manufacturing a transistor in which a trench is formed in a substrate, and a gate pattern is formed on the substrate so that an inclined portion of the trench becomes a part of a channel. Patent Document 2 discloses a method for manufacturing a transistor in which a groove is formed in a silicon substrate and a gate electrode is formed on the slope of the groove.

JP 2006-128613 A JP 2007-220734 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can easily increase the capacity of a memory cell and suppress the short channel effect. is there.

  The nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness, and tunnel insulation formed on the element formation region A film, a floating gate formed through the tunnel insulating film so as to continue over the adjacent concave portion and convex portion of the element formation region, and the slope between them, and formed on the floating gate And a control gate formed on the inter-gate insulating film, and a source / drain diffusion layer formed in the recess so as to be adjacent to the floating gate. .

  The nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness, and tunnel insulation formed on the element formation region A film, a floating gate formed through the tunnel insulating film so as to continue over the adjacent concave portion and convex portion of the element formation region, and the slope between them, and formed on the floating gate An inter-gate insulating film, a control gate formed on the inter-gate insulating film, and a source / drain diffusion layer formed in each of the concave portion and the convex portion so as to be adjacent to the floating gate. It is characterized by that.

  The nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness, and tunnel insulation formed on the element formation region A charge trapping film formed through the tunnel insulating film so as to continue over the film, the recesses adjacent to each other in the element formation region, the protrusions, and the slopes therebetween, and the charge trapping layer A block insulating film formed on the block insulating film, a control gate formed on the block insulating film, and a source / drain diffusion layer formed in the recess so as to be adjacent to the charge trapping film. To do.

  The nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness, and tunnel insulation formed on the element formation region A charge trapping film formed through the tunnel insulating film so as to continue over the film, the recesses adjacent to each other in the element formation region, the protrusions, and the slopes therebetween, and the charge trapping layer A block insulating film formed on the block insulating film, a control gate formed on the block insulating film, and a source / drain diffusion layer formed on each of the concave portion and the convex portion so as to be adjacent to the charge trapping film. It is characterized by having.

  The nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness, and tunnel insulation formed on the element formation region A charge trapping film formed through the tunnel insulating film so as to continue over the film, the recesses adjacent to each other in the element formation region, the protrusions, and the slopes therebetween, and the charge trapping layer And a control gate formed on the block insulating film, wherein a film thickness in a portion on the concave portion of the element forming region is increased compared to a portion on the convex portion of the element forming region. And a source / drain diffusion layer formed in the recess so as to be adjacent to the charge trapping film.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of easily increasing the capacity of a memory cell and suppressing the short channel effect.

1 is a plan view of a memory cell array of a NAND flash memory according to a first embodiment. Sectional drawing which shows the element structure along the AA line in FIG. Sectional drawing of the memory cell array of the NAND flash memory of 2nd Embodiment. Sectional drawing which shows the first process of the manufacturing method of the NAND flash memory which concerns on 1st, 2nd embodiment. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. FIG. 11 is a cross-sectional view showing a step following FIG. 10. Sectional drawing which shows the process following FIG. Sectional drawing which shows the process following FIG. Sectional drawing of the memory cell array of the NAND flash memory of 3rd Embodiment. Sectional drawing of the memory cell array of the NAND flash memory of 4th Embodiment. Sectional drawing of the memory cell array of the NAND flash memory of 5th Embodiment. Sectional drawing which shows the first process of the manufacturing method of the NAND flash memory which concerns on 3rd, 4th, 5th embodiment. FIG. 18 is a cross-sectional view showing a step that follows FIG. 17. FIG. 19 is a cross-sectional view showing a step following FIG. 18. FIG. 20 is a cross-sectional view showing a step following FIG. 19. FIG. 21 is a cross-sectional view showing a step following FIG. 20. FIG. 22 is a cross-sectional view showing a step that follows FIG. 21. FIG. 23 is a cross-sectional view showing a step that follows FIG. 22. FIG. 24 is a cross-sectional view showing a step that follows FIG. 23. FIG. 25 is a cross-sectional view showing a step following FIG. 24. FIG. 26 is a cross-sectional view showing a step following FIG. 25.

  The present invention will be described below with reference to the drawings. In the description of various embodiments, the corresponding portions are denoted by the same reference numerals and redundant description is avoided.

(First embodiment)
FIG. 1 is a plan view of a memory cell array when the nonvolatile semiconductor memory device of the present invention is implemented in a NAND flash memory having a floating gate type (FG) type memory cell transistor. In FIG. 1, a plurality of control gates 11 are formed extending in parallel to each other in the word line (WL) direction, and further partitioned by trench type element isolation regions (STI) 12 in the bit line (BL) direction. The plurality of element forming regions 13 are formed to extend in parallel to each other and in a direction crossing the word line direction. In each of the plurality of element formation regions 13, memory cell transistors made of nonvolatile transistors are formed at positions intersecting with the control gate 11. These memory cell transistors are connected in series in the bit line direction to form a NAND cell unit. Note that an actual NAND cell unit has selection transistors connected to one end side and the other end side of a series circuit composed of a plurality of memory cell transistors connected in series, but this selection transistor is not shown in FIG. Omitted.

  FIG. 2 is a cross-sectional view showing the element structure along the line AA in FIG. 1, and shows a state in which a plurality of memory cell transistors constituting the NAND cell unit are cut in the bit line direction. On the silicon semiconductor substrate, for example, a p-type element formation region 13 defined by the element isolation region 12 shown in FIG. 1 is formed. As shown in FIG. 2, the element formation region 13 is formed so that the surface repeats unevenness continuously and has an inclined surface between adjacent recesses.

Then, a floating gate 15 is formed through a tunnel insulating film 14 made of, for example, a silicon oxide film so as to continue over the adjacent concave portions and convex portions of the element forming region 13 and the slope between them. Yes. That is, the floating gate 15 is formed so as to cover the rounded corners of the element forming region 13 having an uneven shape. The upper surface of the floating gate 15 is parallel to the main plane of the silicon semiconductor substrate. Further, an inter-gate insulating film 16 is formed on each floating gate 15, and a control gate 11 is formed on the inter-gate insulating film 16. The lower surface of the control gate 11 is also parallel to the main plane of the silicon semiconductor substrate. The floating gate 15 and the control gate 11 are made of, for example, polysilicon, and each control gate 11 functions as a word line. Also, so as to be adjacent to the floating gate 15, each recess of the element formation regions 13 are formed n ⁺ -type diffusion layer 17.

  A general NAND flash memory has a structure in which memory cell transistors are arranged in series on a flat semiconductor substrate. However, in the NAND flash memory of the present embodiment, the memory cell transistors are arranged so that the channel region is located in the region of the slope of the element formation region 13 having a periodic uneven shape. The diffusion layer 17 formed in each recess of the element formation region 13 constitutes one of the source / drain diffusion layers of each memory cell transistor. The other of the source / drain diffusion layers of each memory cell transistor is constituted by an inversion layer generated on each convex portion of the element formation region 13 by the fringe electric field of the adjacent control gate 11.

  This is because the distance from the lower surface of the control gate 11 to each convex portion of the element forming region 13 is close to the distance from the lower surface of the control gate 11 to each concave portion of the element forming region 13. In order to operate the memory cell transistor, a voltage is applied to the control gate 11. At this time, since each convex portion of the element forming region 13 has a strong electric field from the control gate 11, an inversion layer is formed on each convex portion of the element forming region 13. On the other hand, since the electric field from the control gate 11 is weak in each recess of the element formation region 13, no inversion layer is formed in each recess of the element formation region 13. Therefore, a diffusion layer 17 is formed in each recess of the element formation region 13.

  Thus, by arranging the channel region of the memory cell transistor on the slope region of the element formation region having a periodic uneven shape, the channel length can be made longer than the processing dimension of the control gate 11, and as a result. The short channel effect can be suppressed. For example, when the (001) plane of the silicon semiconductor substrate is etched by anisotropic etching and the (111) plane is selected as the side facet (small plane), the processing dimensions of the control gate 11 (in FIG. 2) L), the effective channel length is about 1.73L.

  Here, if a deep diffusion layer is formed in both the concave and convex portions of the element formation region 13, the effect of extending the effective channel length cannot be utilized. For example, if the bottom of the diffusion layer formed on each convex portion of the element formation region 13 is lower than the upper surface of the diffusion layer 17, the distance between these diffusion layers becomes the processing dimension L of the control gate 11. is there. Therefore, it is better to form an inversion layer by a fringe electric field generated by applying a bias to the control gate without forming a diffusion layer on the convex portion as in this embodiment.

  Furthermore, in the NAND flash memory according to the present embodiment, the floating gate 15 is formed so as to cover the rounded corners of the element forming region 13 having the uneven shape. As a result, when a control voltage is applied to the control gate 11, electric lines of force concentrate on the corners of the element formation region 13, so that the writing characteristics are remarkably improved as compared with the conventional case.

  As described above, in the NAND flash memory according to the present embodiment, the channel region of the memory cell transistor is arranged on the slope region of the element formation region having a periodic uneven shape, thereby avoiding the short channel effect and simultaneously writing and erasing. The characteristics can be improved. Further, the diffusion layer 17 which is the source / drain diffusion layer of the memory cell transistor is formed only in each concave portion of the element forming region 13 and is not formed in each convex portion of the element forming region 13. As a result, it is possible to avoid punch-through and short channel effects that occur when the diffusion layers are formed on both the concave and convex portions of the element formation region 13.

(Second Embodiment)
FIG. 3 is a cross-sectional view of a memory cell array when the nonvolatile semiconductor memory device of the present invention is implemented in a NAND flash memory having floating gate (FG) type memory cell transistors, and is a plan view of FIG. The element structure along the AA line is shown.

The NAND flash memory of this embodiment is different from that of the first embodiment shown in FIG. 2 in that an n ⁺ type diffusion layer 18 is formed on each convex portion of the element formation region 13.

That is, in the NAND flash memory according to the second embodiment, n ⁺ -type diffusion layers 17 and 18 are formed in each concave portion and each convex portion of the element forming region 13 so as to be adjacent to the floating gate 15. One of the n ⁺ -type diffusion layers 17 and 18 constitutes one of the source / drain diffusion layers of the memory cell transistor, and the other constitutes the other of the source / drain diffusion layers.

Even in the NAND flash memory of this embodiment, the channel region of the memory cell transistor is arranged on the slope region of the element formation region having a periodic uneven shape, thereby improving the write / erase characteristics while avoiding the short channel effect. it can. In addition, since the n ⁺ -type diffusion layers 17 and 18 are formed in the concave portions and the convex portions of the element forming region 13, the cell current can be increased as compared with the case of the first embodiment.

Incidentally, from the viewpoint of avoiding the short channel effect, the bottom surface of the n ⁺ -type diffusion layer 18 is preferably higher than the top surface of the n ⁺ -type diffusion layer 17.

  Next, a method for manufacturing the NAND flash memory according to the first and second embodiments will be described with reference to FIGS. Each of FIG. 4A to FIG. 13A shows a cross section along the line AA in FIG. 1, and FIG. 4B shows a cross section along the line BB in FIG. In the actual NAND flash memory manufacturing process, it is necessary to make several types of transistors separately for the memory cell array portion and the peripheral circuit portion. However, the present invention is mainly effective for the memory cell transistor (memory cell array). Therefore, the description of the manufacturing process that is made separately will be omitted. In addition, the present invention is characterized by a so-called front end process which is a process for processing an element formation area (AA) and a control gate, and therefore also for a so-called back end process which is a process for forming a contact and wiring. Description is omitted.

  First, as shown in FIGS. 4A and 4B, a stripe-shaped etching pattern is formed on the silicon semiconductor substrate 20, and then anisotropically, for example, by wet etching using KOH (potassium hydroxide) or CDE. Etching is performed to process the surface of the substrate into irregularities. Subsequently, as shown in FIGS. 5A and 5B, a tunnel oxide film 14 made of a silicon oxide film is formed on the substrate 20 by, for example, a radical oxidation process. When this oxidation method is selected, an oxide film having the same film thickness is formed on the surface and side surfaces of the uneven portion of the substrate 20.

Next, as shown in FIGS. 6A and 6B, the polysilicon film 15a for floating gate is about 100 nm, the silicon nitride film (Pad-SiN) 21 is about 50 nm, and the silicon oxide film (SiO ₂ ) 22 is used. About 200 nm, a silicon nitride film (SiN) 23 about 50 nm, and a silicon oxide film (SiO ₂ ) 24 about 200 nm. The polysilicon film 15a is preferably formed so that the deposited film thickness is adjusted so that the upper surface of the polysilicon film 15a is substantially flat. Thereafter, an amorphous silicon film 25 is deposited to about 50 nm by LPCVD. Thereafter, a photoresist 26 is applied and lithography is performed to pattern the photoresist 26 in a stripe shape in a direction parallel to the extending direction of the element isolation region.

  Next, a sidewall processing process is performed. First, as shown in FIGS. 7A and 7B, after the amorphous silicon film 25 and the silicon oxide film 24 are processed by RIE, the remaining silicon oxide film 24 is slimmed to form the amorphous silicon film 27. Form on the side wall.

  Subsequently, after the silicon oxide film 24 is removed by wet processing, as shown in FIGS. 8A and 8B, the silicon nitride film 23, the silicon oxide film 22, and the silicon are used by using the amorphous silicon film 27 as a mask. The nitride film 21, the polysilicon film 15a, the tunnel oxide film 14, and the silicon semiconductor substrate 20 are etched in this order. Through the above process, a plurality of element formation regions 13 are formed in the silicon semiconductor substrate 20, and STI grooves 28 are formed between the element formation regions 13.

Thereafter, the trench 28 for STI is filled with a silicon oxide film (SiO ₂ ) 29 having a good filling property and polished by CMP. In this polishing, a silicon nitride film (Pad-SiN) 21 is used as a CMP stopper. Next, as shown in FIGS. 9A and 9B, the silicon oxide film 29 between the polysilicon films 15a in the BB cross section is etched and dropped, and then the silicon nitride film 21 is treated with a chemical solution such as phosphoric acid. Remove with.

Subsequently, as shown in FIGS. 10A and 10B, an IPD film (Inter Poly Dielectric) 30 is formed, and a polysilicon film 31 for a control gate is formed. Next, a sidewall processing process is performed as in the AA process. First, similarly to the AA process, the silicon nitride film (Pad-SiN) 32 is about 50 nm, the silicon oxide film (SiO ₂ ) 33 is about 200 nm, the silicon nitride film (SiN) 34 is about 50 nm, and the silicon oxide film (SiO ₂ ). 35 are sequentially formed to a thickness of about 200 nm. Thereafter, after depositing an amorphous silicon film 36 by about 50 nm by LPCVD, a photoresist 37 is applied, and lithography is performed to pattern the photoresist 37 in a stripe shape in a direction crossing the extending direction of the element isolation region. Here, as shown in the cross section of FIG. 10A, the center of the pattern of the photoresist 37 is formed so as to coincide with the center of each convex portion of the element forming region 13.

  Next, as shown in FIGS. 11A and 11B, after the amorphous silicon film 36 and the silicon oxide film 35 are processed by RIE, the remaining silicon oxide film 35 is slimmed. Thereafter, an amorphous silicon film 38 is formed on the sidewall of the silicon oxide film 35. As a result, the amorphous silicon film 38 is formed on the rounded corners of the element forming region 13 having an uneven shape. Here, unlike the side wall processing process in the AA process, the RIE processing is performed in a state where the silicon oxide film 35 which is a true material is left without being removed.

At this time, the polysilicon film 15a is formed in the region where the silicon oxide film 35 is left, as shown in FIGS. 12A and 12B, by adjusting the etching rate selection ratio of the RIE material. Etching is performed with a portion remaining. At the same time, the IPD film 30 and the polysilicon film 31 are separated for each memory cell transistor, and the intergate insulating film 16 and the control gate 11 are formed. Thereafter, ion implantation of the diffusion layer is performed using the silicon nitride film 32 and the polysilicon film 15a as a mask. As a result, ions do not reach each convex portion of the element forming region 13, so that the n ⁺ -type diffusion layer 17 is formed only in each concave portion of the element forming region 13.

At this time, by changing the acceleration voltage at the time of ion implantation or the film thickness of the polysilicon film 15a remaining on each convex portion of the element formation region 13, the NAND flash memory according to the second embodiment is changed. As described above, n ⁺ -type diffusion layers 17 and 18 (shown in FIG. 3) can be simultaneously formed in the concave portions and the convex portions of the element forming region 13. Further, the bottom of the n ⁺ -type diffusion layer 17 can be made higher than the upper surface of the n ⁺ -type diffusion layer 18. As a result, the cell current can be increased.

  Subsequently, as shown in FIGS. 13A and 13B, the silicon nitride film 32 and the polysilicon film 15a on each convex portion are removed by RIE, so that the polysilicon film 15a is separated into individual memory cell transistors. The floating gate 15 is formed separately for each. After this, floating gate type (FG) type memory cells in which the channel region is located in the slope region of the element formation region having a periodic uneven shape by depositing an interlayer insulating film, forming contacts and wiring. A NAND flash memory having a transistor is completed.

(Third embodiment)
FIG. 14 is a cross-sectional view showing the element structure of a memory cell array when the nonvolatile semiconductor memory device of the present invention is implemented in a NAND flash memory having a MONOS type memory cell transistor. The plan view of the memory cell array of the present embodiment is the same as FIG. 1, and FIG. 14 shows the element structure along the line AA in FIG.

  On the silicon semiconductor substrate, for example, a p-type element formation region 13 defined by the element isolation region 12 shown in FIG. 1 is formed. As shown in FIG. 14, the element formation region 13 is formed so that the surface continuously repeats unevenness and has a slope between adjacent concave portions. Then, a charge trapping film (charged) composed of, for example, a silicon nitride film is provided through the tunnel insulating film 14 so as to continue over the adjacent concave portions and convex portions of the element forming region 13 and the inclined surface therebetween. Trap film) 41 is formed.

That is, the charge trapping film 41 is formed so as to cover the rounded corners of the element forming region 13 having an uneven shape. Further, a block insulating film 42 having a uniform thickness is formed on each charge trapping film 41, and the control gate 11 is formed on the block insulating film 42. The block insulating film 42 is made of a high dielectric film such as Al ₂ O ₃ , and the control gate 11 is made of a conductive film such as polysilicon, and each control gate 11 functions as a word line. Further, an n ⁺ -type diffusion layer 17 is formed in each recess of the element formation region 13 so as to be adjacent to the charge trapping film 41.

  In the NAND flash memory according to the present embodiment, the memory cell transistors are arranged so that the channel region is located in the region of the slope of the element formation region 13 having a periodic uneven shape. The diffusion layer 17 formed in each recess of the element formation region 13 constitutes one of the source / drain diffusion layers of each memory cell transistor. The other of the source / drain diffusion layers of each memory cell transistor is constituted by an inversion layer generated on each convex portion of the element formation region 13 by the fringe electric field of the adjacent control gate 11.

  Thus, by arranging the channel region of the memory cell transistor on the slope region of the element formation region having a periodic uneven shape, the channel length can be made longer than the processing dimension of the control gate 11, and as a result. The short channel effect can be suppressed. Here, if a deep diffusion layer is formed in both the concave portion and the convex portion of the element forming region 13, the effect of extending the effective channel length cannot be utilized. Therefore, the diffusion layer is not formed in the convex portion as in the present embodiment. It is better to form the inversion layer by a fringe electric field generated by applying a bias to the control gate.

  Furthermore, in the NAND flash memory according to the present embodiment, the charge trapping film 41 is formed so as to cover the rounded corners of the element forming region 13 having an uneven shape. As a result, when a control voltage is applied to the control gate 11, electric lines of force concentrate on the corners of the element formation region 13, so that the writing characteristics are remarkably improved as compared with the conventional case.

  As described above, in the NAND flash memory according to the present embodiment, the channel region of the memory cell transistor is arranged on the slope region of the element formation region having a periodic uneven shape, thereby avoiding the short channel effect and simultaneously writing and erasing. The characteristics can be improved. Further, the diffusion layer 17 which is the source / drain diffusion layer of the memory cell transistor is formed only in each concave portion of the element forming region 13 and is not formed in each convex portion of the element forming region 13. As a result, it is possible to avoid punch-through and short channel effects that occur when the diffusion layers are formed on both the concave and convex portions of the element formation region 13.

  The block insulating film 42 is formed with a uniform film thickness. Here, if the upper surface of the block insulating film 42 is formed so as to be parallel to the main plane of the silicon substrate, the film thickness of the block insulating film 42 is thin at each convex portion of the element forming region 13 and thick at each concave portion. turn into. Then, in the vicinity of each recess in the element formation region 13, the electric field applied from the control gate 11 to the charge trapping film 41 becomes weak, and sufficient writing is not performed. Furthermore, since the charge trapping film 41 is usually an insulating film, electrons captured in the vicinity of each convex portion of the element formation region 13 do not move to the vicinity of each concave portion. As a result, a write failure or the like occurs.

  On the other hand, if the block insulating film 42 is formed to have a uniform thickness, the electric field applied from the control gate 11 to the charge trapping film 41 in the vicinity of each recess in the element formation region 13 will not be weakened. As a result, the reliability of the memory cell operation can be improved.

(Fourth embodiment)
FIG. 15 is a cross-sectional view of a memory cell array when the nonvolatile semiconductor memory device of the present invention is implemented in a NAND flash memory having a MONOS type memory cell transistor, and is taken along line AA in the plan view of FIG. The element structure along is shown.

The NAND flash memory of this embodiment is different from that of the third embodiment shown in FIG. 14 in that an n ⁺ -type diffusion layer 18 is formed on each convex portion of the element formation region 13.

Incidentally, as mentioned above, from the viewpoint of avoiding the short channel effect, the bottom surface of the n ⁺ -type diffusion layer 18 is preferably higher than the upper surface of the n ⁺ -type diffusion layer 17.

That is, in the NAND flash memory according to the fourth embodiment, the n ⁺ -type diffusion layers 17 and 18 are formed in the concave portions and the convex portions of the element forming region 13 so as to be adjacent to the charge trapping film 41. . One of the n ⁺ -type diffusion layers 17 and 18 constitutes one of the source / drain diffusion layers of the memory cell transistor, and the other constitutes the other of the source / drain diffusion layers.

Even in the NAND flash memory of this embodiment, the channel region of the memory cell transistor is arranged on the slope region of the element formation region having a periodic uneven shape, thereby improving the write / erase characteristics while avoiding the short channel effect. it can. In addition, since the n ⁺ -type diffusion layers 17 and 18 are formed in the concave portions and the convex portions of the element forming region 13, the cell current can be increased as compared with the case of the third embodiment.

(Fifth embodiment)
16 is a cross-sectional view of a memory cell array when the nonvolatile semiconductor memory device of the present invention is implemented in a NAND flash memory having a MONOS type memory cell transistor, and is taken along line AA in the plan view of FIG. The element structure along is shown.

Also in the present embodiment, the n ⁺ -type diffusion layer 17 is formed only in each recess of the element formation region 13. This diffusion layer 17 constitutes one of the source / drain diffusion layers of each memory cell transistor. The other of the source / drain diffusion layers of each memory cell transistor is constituted by an inversion layer generated on each convex portion of the element formation region 13 by the fringe electric field of the adjacent control gate 11.

  This is because the distance from the lower surface of the control gate 11 to each convex portion of the element forming region 13 is close to the distance from the lower surface of the control gate 11 to each concave portion of the element forming region 13. In order to operate the memory cell transistor, a voltage is applied to the control gate 11. At this time, since each convex portion of the element forming region 13 has a strong electric field from the control gate 11, an inversion layer is formed on each convex portion of the element forming region 13. On the other hand, since the electric field from the control gate 11 is weak in each recess in the element formation region 13, no inversion layer is formed in each recess in the element formation region 13. Therefore, a diffusion layer 17 is formed in each recess of the element formation region 13.

  In the NAND flash memory of the third embodiment shown in FIG. 14, the block insulating film 42 of each memory cell transistor has a uniform thickness. On the other hand, in the NAND flash memory according to the present embodiment, the block insulating film 42 of each memory cell transistor is continuously thicker in the portion on the concave portion than the portion on the convex portion of the element forming region 13. The film is modulated so that

  Even in the NAND flash memory of this embodiment, the channel region of the memory cell transistor is arranged on the slope region of the element formation region having a periodic uneven shape, thereby improving the write / erase characteristics while avoiding the short channel effect. it can. Moreover, in the NAND flash memory according to the present embodiment, the block insulating film 42 of the memory cell transistor is film-modulated so that the film thickness in the portion on the concave portion is larger than the portion on the convex portion in the element forming region 13. Therefore, the control gate 11 can be moved away from the charge trapping film 41 of the adjacent memory cell transistor, and inter-cell interference can be weakened. In addition, since the block insulating film 42 is locally thick, the Back Tunneling effect can be suppressed and the erasing characteristics can be improved.

  Note that the electric field applied from the control gate 11 to the charge trapping film 41 is weak in the vicinity of each recess in the element formation region 13. However, by reducing the thickness of the entire block insulating film 42, the electric field in the vicinity of each recess in the element formation region 13 can be increased.

  Next, a method for manufacturing a NAND flash memory according to the third, fourth, and fifth embodiments will be described with reference to FIGS. Each figure (a) of Drawing 17-Drawing 26 shows a section which met an AA line in Drawing 1, and each figure (b) shows a section along a BB line in Drawing 1. In the actual NAND flash memory manufacturing process, it is necessary to make several types of transistors separately for the memory cell array portion and the peripheral circuit portion. However, the present invention is mainly effective for the memory cell transistor (memory cell array). Therefore, the description of the manufacturing process that is made separately will be omitted. In addition, the present invention is characterized by a so-called front end process which is a process for processing an element formation area (AA) and a control gate, and therefore also for a so-called back end process which is a process for forming a contact and wiring. Description is omitted.

First, as shown in FIGS. 17A and 17B, after forming a striped etching pattern on the silicon semiconductor substrate 20, anisotropic etching is performed by wet etching using CDH or CDE, for example. The substrate surface is processed into an uneven shape. Subsequently, as shown in FIGS. 18A and 18B, a tunnel oxide film 14 made of a silicon oxide film is formed on the substrate 20 by about 4 nm by a radical oxidation process. When this oxidation method is selected, an oxide film having the same film thickness is formed on the surface and side surfaces of the uneven portion of the substrate 20. Subsequently, a silicon nitride film (SiN) 41a for charge trapping film is sequentially formed to a thickness of about 5 nm and a silicon oxide film (Pad-SiO ₂ ) 43 is sequentially formed to a thickness of about 5 nm, and then an amorphous silicon film 44 is deposited by LPCVD to a thickness of about 50 nm. To do. Note that if the upper surface of the amorphous silicon film 44 is planarized, a processing margin in a later process is improved.

Subsequently, as shown in FIGS. 19A and 19B, the silicon nitride film (Pad-SiN) 45 is about 70 nm, the silicon oxide film (SiO ₂ ) 46 is about 200 nm, and the silicon nitride film (SiN) 47 is formed. About 50 nm, a silicon oxide film (SiO ₂ ) 48 is sequentially formed to a thickness of about 200 nm, and then an amorphous silicon film 49 is deposited to a thickness of about 80 nm by LPCVD. Then, a photoresist 50 is applied, and lithography is performed to form the photoresist 50. Patterning is performed in a stripe shape in a direction parallel to the extending direction of the element isolation region.

  Next, a sidewall processing process is performed. First, as shown in FIGS. 20A and 20B, the amorphous silicon film 49 and the silicon oxide film 48 are processed by RIE. Thereafter, the remaining silicon oxide film 48 is slimmed to form an amorphous silicon film 51 on the side wall. Subsequently, after the silicon oxide film 48 is removed by wet processing, as shown in FIGS. 21A and 21B, the amorphous silicon film 51 is used as a mask, and the silicon nitride film 47, silicon oxide film 46, silicon The nitride film 45, the amorphous silicon film 44, the silicon oxide film 43, the silicon nitride film 41a, the tunnel oxide film 14, and the silicon semiconductor substrate 20 are etched in this order. Through the above steps, a plurality of element formation regions 13 are formed in the silicon semiconductor substrate 20, and STI grooves 52 are formed between the element formation regions 13.

After that, the STI trench 52 is filled with a silicon oxide film (SiO ₂ ) 53 having a good filling property and polished by CMP. During this polishing, a silicon nitride film (Pad-SiN) 45 is used as a CMP stopper.

Next, as shown in FIGS. 22A and 22B, the silicon oxide film 53 between the element formation regions 13 is etched and dropped. Thereafter, the silicon nitride film 45, the amorphous silicon film 44, and the silicon oxide film 43 are removed with a chemical solution such as phosphoric acid. Subsequently, a high dielectric film for the block insulating film, for example, an Al ₂ O ₃ film 54 is formed to a thickness of about 10 nm. Here, by selecting the film forming conditions of the Al ₂ O ₃ film 54, the block insulating film can be modulated as in the NAND flash memory of the fifth embodiment shown in FIG.

Thereafter, a sidewall processing process is performed in the same manner as the AA process. As shown in FIGS. 23A and 23B, the amorphous polysilicon film 55 is about 50 nm, the silicon nitride film (Pad-SiN) 56 is about 70 nm, the silicon oxide film (SiO ₂ ) 57 is about 150 nm, and silicon nitride. film (SiN) 58 to 50nm approximately, silicon oxide film (SiO ₂₎ 59 to 150nm approximately, successively formed. Thereafter, after depositing an amorphous silicon film 60 by about 80 nm by LPCVD, a photoresist 61 is applied, and lithography is performed to pattern the photoresist 61 in a stripe shape in a direction intersecting with the extending direction of the element isolation region. Here, as shown in the cross section of FIG. 23A, the center of the pattern of the photoresist 61 is formed so as to coincide with the center of each convex portion of the element forming region 13.

  Next, as shown in FIGS. 24A and 24B, after the amorphous silicon film 60 and the silicon oxide film 59 are processed by RIE, the remaining silicon oxide film 59 is slimmed. Thereafter, an amorphous silicon film 62 is formed on the side wall of the silicon oxide film 59. As a result, the amorphous silicon film 62 is formed on the rounded corners of the element forming region 13 having an uneven shape. Here, unlike the side wall processing process in the AA process, the RIE processing is performed in a state where the silicon oxide film 59 which is a true material is left without being removed.

At this time, by adjusting the etching rate selection ratio of the RIE material, as shown in FIGS. 25A and 25B, the Al ₂ 0 ₃ film is formed in the region where the silicon oxide film 59 is left. Etching is performed with a portion 54 remaining. At the same time, the amorphous polysilicon film 55 is separated for each memory cell transistor, and the control gate 11 is formed. Thereafter, ion implantation of the diffusion layer is performed using the silicon nitride films 56 and 41a as a mask.

As a result, ions do not reach each convex portion of the element forming region 13, so that the n ⁺ -type diffusion layer 17 is formed only in each concave portion of the element forming region 13. At this time, the NAND flash of the fourth embodiment is changed by changing the acceleration voltage at the time of ion implantation or the film thickness of the Al ₂ O ₃ film 54 remaining on each convex portion of the element formation region 13. Like the memory, n ⁺ -type diffusion layers 17 and 18 (shown in FIG. 15) can be simultaneously formed in each concave portion and each convex portion of the element formation region 13. Further, the diffusion depths of the n ⁺ -type diffusion layers 17 and 18 can be made different. When the n ⁺ -type diffusion layers 17 and 18 are formed, the bottom surface of the diffusion layer 18 is preferably higher than the upper surface of the diffusion layer 17 in order to avoid the short channel effect as described above. By forming both of the diffusion layers 17 and 18, the cell current can be increased.

Subsequently, as shown in FIGS. 26A and 26B, the silicon nitride film 56, the Al ₂ O ₃ film 54 on each convex portion, and the silicon nitride film 41a are removed by RIE, whereby Al ₂ 0. _The block insulating film 42 and the charge trapping film 41 are formed by separating the _three films 54 and the silicon nitride film 41a for each memory cell transistor. After this, a NAND flash having a MONOS type memory cell transistor in which the channel region is located in the slope region of the element forming region having a periodic uneven shape by depositing an interlayer insulating film, forming a contact and wiring. The memory is complete.

  As mentioned above, although this invention was demonstrated using embodiment, this invention is not limited to the said embodiment, In the implementation stage, it can change variously in the range which does not deviate from the summary. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects obtained is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 11 ... Control gate, 12 ... Element isolation region, 13 ... Element formation region, 14 ... Tunnel insulating film, 15 ... Floating gate, 16 ... Inter-gate insulating film, 17, 18 ... Diffusion layer, 41 ... Charge trapping film, 42 ... Block insulation film.

Claims (5)

A semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness;
A tunnel insulating film formed on the element formation region;
A floating gate formed through the tunnel insulating film so as to be continuous over the concave portion and the convex portion adjacent to each other in the element formation region and the slope between them;
An inter-gate insulating film formed on the floating gate;
A control gate formed on the inter-gate insulating film;
A non-volatile semiconductor memory device comprising: a source / drain diffusion layer formed in the recess so as to be adjacent to the floating gate. A semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness;
A tunnel insulating film formed on the element formation region;
A floating gate formed through the tunnel insulating film so as to be continuous over the concave portion and the convex portion adjacent to each other in the element formation region and the slope between them;
An inter-gate insulating film formed on the floating gate;
A control gate formed on the inter-gate insulating film;
A non-volatile semiconductor memory device comprising: a source / drain diffusion layer formed in each of the concave portion and the convex portion so as to be adjacent to the floating gate. A semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness;
A tunnel insulating film formed on the element formation region;
A charge trapping film formed through the tunnel insulating film so as to be continuous over the concave portion and the convex portion adjacent to each other in the element formation region and the slope between them;
A block insulating film formed on the charge trapping layer;
A control gate formed on the block insulating film;
A non-volatile semiconductor memory device comprising: a source / drain diffusion layer formed in the recess so as to be adjacent to the charge trapping film. A semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness;
A tunnel insulating film formed on the element formation region;
A charge trapping film formed through the tunnel insulating film so as to be continuous over the concave portion and the convex portion adjacent to each other in the element formation region and the slope between them;
A block insulating film formed on the charge trapping layer;
A control gate formed on the block insulating film;
A non-volatile semiconductor memory device comprising: a source / drain diffusion layer formed in each of the concave portion and the convex portion so as to be adjacent to the charge trapping film. A semiconductor substrate having an element formation region that is partitioned by an element isolation region and formed so that the surface continuously repeats unevenness;
A tunnel insulating film formed on the element formation region;
A charge trapping film formed through the tunnel insulating film so as to be continuous over the concave portion and the convex portion adjacent to each other in the element formation region and the slope between them;
A block insulating film formed on the charge trapping layer and having a greater thickness in a portion on the concave portion of the element forming region than on a portion on the convex portion of the element forming region;
A control gate formed on the block insulating film;
A non-volatile semiconductor memory device comprising: a source / drain diffusion layer formed in the recess so as to be adjacent to the charge trapping film.

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