JP2010211342A - Test pattern management device, test pattern management method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently generate a test pattern which enables an effective simulation. <P>SOLUTION: An initial probability setting file 13 shows the rate of each parameter value for each parameter item, and a test parameter generator 2 generates a plurality of types of test patterns according to a rate of each parameter value of the initial probability setting file 13, and makes a test bench 4 execute simulation by using a test pattern 3. A result file input part 14 inputs a result file 6 showing the result of simulation, and stores it in an execution log 7, and a failure history analyzing part 9 analyzes a failure factor history 8 showing the factor of a failure test pattern obtained from the execution log 7, and a probability setting file generator 10 generates a new probability setting file 1 by increasing the rate of the parameter value whose failure generation frequency is high, and the test pattern generator 2 generates a new test pattern 3 according to the probability setting file 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a logic verification method in an integrated circuit such as an LSI (Large Scale Integration).

In the LSI logic verification method for automatically generating a conventional test pattern, a verification person creates a probability setting file for test pattern generation with the subject of the verification person, automatically generates a test pattern according to the parameters of the probability setting file, LSI logic verification was executed.
Alternatively, a probability setting file is automatically generated at random, a test pattern is automatically generated according to the parameters of the probability setting file, and LSI logic verification is executed.
For example, in the technique described in Patent Document 1, a means for automatically generating an operation parameter necessary for generating a simulation pattern and a means for a person in charge of verification to set the operation parameter correspond.
A method for automatically generating a test pattern using a probability setting file is also disclosed in Patent Document 2.
In this way, by generating a large number of random test patterns using the parameters of the probability setting file and executing the simulation, various test patterns can be easily generated, and complicated test patterns that were not sufficient manually We have solved the problems such as the execution of condition tests and the prevention of test omissions that are likely to occur due to complex logic.

JP 2006-127109 A, page 4, paragraphs 17 to 22 JP-A-10-212410, page 4, paragraphs 10 to 12

In the conventional LSI logic verification method that automatically generates test patterns, the person in charge of the analysis analyzes the information of the detected defects, and manually adjusts the parameters of the probability setting file to generate events with many defects, and performs simulation. There is a problem that it takes time and labor.
In addition, when automatically generating a probability setting file randomly, it is difficult to control to generate many specific events, so it is necessary to generate more test patterns, which is not efficient. .

  The present invention has been made in view of these problems, and a main object of the present invention is to efficiently generate a test pattern that enables effective simulation without human intervention.

The test pattern management apparatus according to the present invention is:
A test pattern management device for managing test patterns used for simulation,
It acquires multiple types of parameter items, each of which takes multiple parameter values, acquires selection ratio information indicating the selection ratio of each parameter value for each parameter item, and sets the parameter value for each parameter item indicated in the acquired selection ratio information. According to the selection ratio, a test pattern generation unit that generates a plurality of test patterns by selecting a parameter value for each parameter item;
A simulation result information input unit for inputting simulation result information indicating a result of simulation using the test pattern generated by the test pattern generation unit;
And a selection ratio changing unit that analyzes the simulation result information input by the simulation result information input unit and changes a parameter value selection ratio in each parameter item of the selection ratio information.

  According to the present invention, since the selection ratio of parameter values is automatically changed based on the result of simulation, the selection ratio is changed so that parameter values with poor simulation results are concentrated and verified without human intervention. And efficient verification can be performed.

1 is a diagram illustrating a configuration example of an LSI logic verification system according to a first embodiment. FIG. 6 shows an example of an initial probability setting file according to the first embodiment. FIG. 3 shows an example of a test pattern according to the first embodiment. FIG. 6 shows an example of a result file according to the first embodiment. FIG. 4 is a diagram illustrating an example of an execution log according to the first embodiment. FIG. 6 is a diagram showing an example of a failure factor history according to the first embodiment. FIG. 3 is a flowchart showing an operation example of the test pattern management apparatus according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of an LSI logic verification system according to a second embodiment. FIG. 10 is a diagram illustrating an example of pattern generation summary information according to the second embodiment. FIG. 9 is a flowchart showing an operation example of the test pattern management apparatus according to the second embodiment. FIG. 3 is a diagram illustrating a hardware configuration example of a test pattern management apparatus according to the first and second embodiments.

Embodiment 1 FIG.
In this embodiment, by holding information on defects detected in the simulation, automatically generating probability setting files for generating many specific events such as events with many defects by analyzing information on defects, A configuration for efficiently improving the design quality will be described.

FIG. 1 is a diagram showing an example of the overall configuration of an LSI logic verification system according to the present embodiment.
The LSI logic verification system according to the present embodiment is roughly divided into a test pattern management apparatus 100, a test bench 4, and an LSI 5.
The LSI 5 is an integrated circuit to be verified.
The test bench 4 reads a test pattern and executes a simulation for logic verification of the LSI 5.
The test pattern management apparatus 100 manages test patterns used for simulation in the test bench 4.

In the test pattern management apparatus 100, the test pattern generator 2 generates a plurality of test patterns 3 according to the probability (selection ratio) for each parameter value indicated in the initial probability setting file 13 created in advance.
In addition, a plurality of new test patterns 3 are generated using the probability setting file 1 after the probability (selection ratio) of the parameter value is changed by a probability setting file generator 10 described later.
The test pattern generator 2 is an example of a test pattern generation unit.

The result file input unit 14 inputs a result file 6 (simulation result information) in which a result of simulation using the test pattern generator 2 is shown.
The result file 6 is output from the test bench 4 as a simulation result.
The result file input unit 14 stores the input result file 6 in the execution log 7.
Therefore, a result file 6 as a result of sequentially executing a plurality of test patterns is accumulated in the execution log 7.
The result file input unit 14 is an example of a simulation result information input unit.

  The defect factor history 8 is obtained by extracting the factor attribute of the simulation result NG among the simulation results accumulated in the execution log 7.

The defect history analysis unit 9 extracts the defect factor history 8 from the execution log 7 and analyzes the content of the extracted defect factor history 8.
The probability setting file generator 10 generates the probability setting file 1 for generating the test pattern 3 next in accordance with the information analyzed by the defect history analysis unit 9.
More specifically, the failure history analysis unit 9 analyzes parameter values that appear in the failure occurrence test pattern in which a failure has occurred in the simulation, extracts a combination of parameter values that appear frequently in the failure occurrence test pattern, The setting file generator 10 increases the probability (selection ratio) of each parameter value included in the extracted combination to generate a probability setting file 1 that is a new probability setting file.
The defect history analysis unit 9 and the probability setting file generator 10 are examples of a selection ratio changing unit.

The test bench 4 includes a CPU bus model 401 that executes a transaction for the LSI 5 to be verified, and a DRAM model 402 and an SRAM model 403 that are memories connected to the LSI 5.
There may be a plurality of CPU bus models 401 when there are a plurality of buses 550 to which the LSI 5 can be a target.
If there are devices connected to the LSI 5 other than DRAM and SRAM, the test bench 4 may have models corresponding to these devices.

  The LSI 5 to be verified receives a command from the CPU bus model 401 via the bus 550, and receives an internal block A501 that interfaces with the internal bus 506, an internal block B502 that interfaces the internal bus 506 with an external DRAM, The block 503 includes an internal block C503 that interfaces with the bus 506 and an external SRAM, and an internal block D504 and an internal block E505 of other LSI internal function blocks.

  Next, the operation until the test pattern management apparatus 100 generates the test pattern 3 according to the initial probability setting file 13 and generates the next probability setting file 1 based on the simulation result by the test bench 4 is shown in FIG. The description will be given with reference.

  First, the test pattern generator 2 reads the initial probability setting file 13 to generate a test pattern 3 (S701) (test pattern generation step), and outputs the generated test pattern to the test bench 4 (S702).

FIG. 2 shows an example of the initial probability setting file 13.
The initial probability setting file 13 includes a parameter identifier 1001, a parameter item 1002, a value combination list 1003 (selection ratio information) indicating possible values (parameter values) in each parameter item and a ratio (selection ratio) to be the value. ) Is described for the number of parameter items to be set.
An example of line numbers 130 and 140 will be described.
The parameter item “TARGET” can have parameter values “DRAM”, “SRAM”, “internal block D”, and “internal block E”, and the ratio of the parameter item “TARGET” to each parameter value is “DRAM”. "3", "SRAM" is 2, "Internal block D" is 4, and "Internal block E" is 1.
That is, in the parameter item “TARGET”, the probability that the parameter value “DRAM” is included in the test pattern (the probability of being selected as the parameter value of the test pattern) is calculated by 3 / (3 + 2 + 4 + 1) and is 3/10.
Similarly, the parameter value “SRAM” is calculated as 2/10, the parameter value “internal block D” is calculated as 4/10, and the parameter value “internal block E” is calculated as 1/10.
Based on this ratio value, the test pattern generator 2 obtains the ratio of each parameter value for the parameter item “TARGET”, selects each parameter value according to the ratio of each parameter value, and generates the specified number of test patterns 3 To do.
As described above, for other parameter items, the test pattern generator 2 selects a parameter value to be included in the test pattern according to the ratio for each parameter value in the initial probability setting file 13, and the test pattern 3 is generated.

FIG. 3 is an example of the test pattern 3.
Test pattern 3 includes a parameter setting instruction related to the test configuration exemplified by line numbers 530 to 600, an initial value setting instruction string exemplified by line numbers 620 to 700, and a CPU bus model exemplified by line numbers 720 to 790. A command sequence issued by 401, and a command for comparing the simulation result illustrated in line numbers 810 to 880 with an expected value.
The argument of each command is configured by a parameter value whose probability is specified in the probability setting file.

Next, the test bench 4 reads the test pattern 3 generated in this way.
Here, the test bench 4 determines the simulation configuration according to the parameters related to the configuration shown in the test pattern 3, sets initial values in the test bench 4 and the verification target LSI 5, and the CPU bus model 401 sets the test pattern 3. The indicated command is issued to the LSI 5 via the bus 550.
The LSI 5 performs a predetermined operation according to a command issued by the CPU bus model 401.
When the LSI 5 completes the operation, the test bench 4 executes the expected value comparison command shown in the test pattern 3 and compares the simulation result with the expected value.
Then, the test bench 4 outputs the result to the result file 6 when the simulation 404 is completed.

FIG. 4 shows an example of the result file 6.
The result file 6 indicates the test pattern name, the command number indicating the command number in the test pattern, command information indicating the parameter value information of the command, and whether the simulation result of the command is OK or NG. It is composed of a command result and a test result indicated as OK when all the command results are OK in the test pattern, and NG when including at least one NG. The result file 6 is stored and accumulated in the execution log 7.

In the test pattern management apparatus 100, the result file input unit 14 inputs the result file 6 (S703) (simulation result information input step).
As described above, the simulation is sequentially executed on the test bench 4 according to the test pattern 3 generated by the test pattern generator 2, and the result file 6 indicating the result of the simulation is sequentially input by the result file input unit 14 and accumulated in the execution log 7. To go.

FIG. 5 shows an example of the execution log 7.
The execution log 7 is composed of a test pattern name, a command number, command information indicating the parameter value information of the command, a simulation result of the command, and a test pattern result.

Next, the defect history analysis unit 9 extracts the defect factor history 8 from the execution log 7 (S704).
The failure factor history 8 is a total result of command information of a command whose command result is NG from the information accumulated in the execution log 7.

FIG. 6 shows an example of the failure factor history 8.
The defect history analysis unit 9 extracts each parameter value from the command information in which the command result of the execution log 7 is NG, and accumulates the number of cases.
For example, in FIG. 6, the number of NG cases in the 2-byte read for the internal block D is five.

Next, the failure history analysis unit 9 analyzes the total result shown in the failure factor history 8 and passes information on each parameter to the probability setting file generator 10 (S705) (selection ratio changing step).
For example, in FIG. 6, the target is “internal block D”, the read (R) / write (W) is “read (R)”, the size is “2 bytes”, the target is “SRAM”, and the target is “SRAM”. The number of cases where read / write is “read” and size is “2 bytes” continues.
The information that the defect history analysis unit 9 passes to the probability setting file generator 10 may be the order of NG or the ratio of NG.

Next, the probability setting file generator 10 generates the next probability setting file from the information received from the defect history analysis unit 9 and the initial probability setting file (S706) (selection ratio changing step).
For example, in the example of FIG. 6, since the NG ratio when the target is “internal block D” is high, it is determined that the quality of the internal block D is low, and the parameter value “internal” is set in the target parameter item in the previous probability setting file. The probability of the block D ″ is changed to be high.

Then, the test pattern generator 2 reads the updated probability setting file 1 and generates the next test pattern 3.
Then, verification of the verification target LSI 5 whose defect has been corrected is continued.

As described above, according to the present embodiment, it is possible to automatically analyze a defect history and generate a probability setting file that were previously performed manually.
Conventionally, when the probability setting file is automatically generated, the ratio of the parameter values has been randomly determined. According to the present embodiment, the probability setting file is analyzed by analyzing the defect history. Is automatically generated, it is possible to concentrate and verify particularly low-quality parts in the verification target, and to perform efficient verification.

Thus, in the present embodiment, the LSI logic verification method including the following means has been described.
(1) Means for automatically generating a probability setting file for automatic test pattern generation.
(2) Means for holding simulation result information.
(3) Means for analyzing the tendency of parameters set in the probability setting file at the time of occurrence of a defect from the information of the simulation result of (2) above.
(4) Means for automatically generating a probability setting file based on the parameter tendency information set in the probability setting file at the time of the occurrence of a failure in (3) above.

Embodiment 2. FIG.
In the first embodiment described above, a method has been described in which verification is continued while correcting defects in the verification target, and the quality of the verification target is efficiently improved. However, it may take time to correct the verification target. In this embodiment, a method for continuing verification without correcting the verification target and realizing shortening of the verification period will be described.

  The conventional LSI logic verification method that automatically generates test patterns automatically simulates a large number of test patterns generated with a single probability setting file. Since the simulation becomes NG, the analysis takes a lot of time, and there is a high possibility of overlooking defects in other events in the analysis, resulting in a problem that the development period is prolonged.

In this embodiment, in order to deal with such a problem, when a failure of an event occurs by analyzing the failure information of the simulation result, the same event is reproduced in the subsequent test patterns that have already been generated. Stop the test pattern simulation.
As a result, it is possible to omit the analysis due to the failure of the similar event, and to detect the failure of the other event at an early stage. The development period can be shortened by expediting the discovery of new defects.

FIG. 8 is a diagram showing an overall configuration example of the LSI logic verification system according to the present embodiment.
In addition to the configuration of FIG. 1 shown in the first embodiment, a test pattern filter 11 and pattern generation summary information 12 are added.
Elements other than the test pattern filter 11 and the pattern generation summary information 12 are the same as those shown in FIG.

  The pattern generation summary information 12 stores parameter information as a result of the test pattern generator 2 generating a test pattern.

The test pattern filter 11 cancels the next test pattern to be executed from the information on the failure factor history analyzed by the failure history analysis unit 9, and determines the test pattern to be executed next.
More specifically, in the present embodiment, the failure history analysis unit 9 analyzes parameter values that appear in the failure factor history 8, and combinations of parameter values that appear frequently in the failure factor history 8 are excluded combinations. The test pattern filter 11 includes a combination of parameter values that matches the exclusion target combination extracted by the defect history analysis unit 9 from the plurality of test patterns generated by the test pattern generator 2. The pattern is extracted, and the extracted test pattern is excluded from the simulation target.
The test pattern filter 11 is an example of a test pattern exclusion unit. In the present embodiment, the failure history analysis unit 9 is an example of a failure analysis unit.

FIG. 9 shows an example of the pattern generation summary information 12.
The pattern generation summary information 12 is information on the test pattern name, “target”, “read / write”, “size”, and “appearance (with / without combination)” of the CPU bus model 401.
“Appearance (with / without combination)” included in the pattern generation summary information 12 indicates whether or not there is another test pattern including the same parameter value combination.
For example, in the test pattern name: TP101 in FIG. 9, the command whose target is “internal block D”, read / write “read”, and size “2 bytes” appears “1 (with combination)”. This indicates that a command having the same combination as the parameter value combination of this command is included in another test pattern.
Note that the information of the failure factor history 8 analyzed by the failure history analysis unit 9 is as in the example shown in FIG. 6 as in the first embodiment.

  Next, an operation example of the test pattern management apparatus 100 according to the present embodiment will be described with reference to FIG.

  In FIG. 10, the processing of S1001 to S1004 is the same as S701 to S704 shown in FIG.

In S1005, the defect history analysis unit 9 analyzes parameter values that appear in the defect factor history 8, and extracts combinations of parameter values that appear frequently in the defect factor history 8 as exclusion target combinations (defect analysis step). .
Next, the test pattern filter 11 refers to the value of the item “appearance” of the pattern generation summary information 12, and whether or not the exclusion target combination specified by the defect history analysis unit 9 exists in another test pattern. If there is no exclusion target combination in other test patterns (NO in S1006), the process returns to S1002, and if there is an exclusion target combination (YES in S1006), the test pattern including the exclusion target combination Are extracted and excluded from the simulation target (S1007) (test pattern exclusion step).
The test patterns to be excluded from the simulation target are those that have not yet been used for the simulation among the test patterns generated by the test pattern generator 2.

In the example of FIG. 6, it is understood that there are many defects in the transaction analyzed by the defect history analysis unit 9 and in which the target is “internal block D”, the read / write is “read”, and the size is “2 bytes”. Yes.
The test pattern filter 11 searches the pattern generation summary information 12 for a test pattern in which the target is “internal block D”, the read / write is “read”, and the size is “2 bytes”.
When the test pattern to be executed next includes the transaction of the combination, the test pattern filter 11 instructs the test bench 4 not to execute the test pattern (or does not output the test pattern to the test bench 4). To the test pattern generator 2).
Further, for the next test pattern, a search is made as to whether or not the transaction includes a combination of “internal block D”, read / write “read”, and size “2 bytes”.
Then, a test pattern having no transaction with a combination with many defects is read into the test bench 4 and a simulation is performed.

  Conventionally, if a large number of test patterns with a combination of transactions with many defects are executed in large quantities, a large amount of NG occurs due to defects of the same factor, and there has been a problem that the analysis takes an enormous amount of time. In this embodiment, a test pattern having a combination of transactions with many defects is not executed, and a test pattern with no defects or a combination of transactions having a small number of combinations is executed to analyze NG due to defects of the same factor. Time can be omitted, and detection of an unknown defect can be accelerated by simulation using a test pattern of transactions with no defects or a small number of combinations.

As described above, the present embodiment has described the LSI logic verification method including the following means.
(1) Means for automatically generating a probability setting file for automatic test pattern generation.
(2) Means for holding parameter information of automatically generated test patterns.
(3) Means for holding simulation result information.
(4) Means for analyzing the tendency of parameters set in the probability setting file at the time of failure from the information of the simulation result.
(5) Means for determining whether to execute a test pattern to be executed next or later from the parameter information of the held test pattern in (2) and the information on the simulation result held in (3).
(6) (5) means for applying a filter so as not to execute the test pattern when it is determined that the test pattern is not executed by the means for determining whether or not to execute the test pattern.

Finally, a hardware configuration example of the test pattern management apparatus 100 shown in the first and second embodiments will be described.
FIG. 11 is a diagram illustrating an example of hardware resources of the test pattern management apparatus 100 illustrated in the first and second embodiments.
The configuration in FIG. 11 is merely an example of the hardware configuration of the test pattern management apparatus 100, and the hardware configuration of the test pattern management apparatus 100 is not limited to the configuration described in FIG. There may be.

11, the test pattern management apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, a processing unit, a microprocessor, a microcomputer, and a processor) that executes a program.
The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices.
Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card (registered trademark) read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
A communication board 915, a keyboard 902, a mouse 903, a scanner device 907, an FDD 904, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

  The communication board 915 is connected to the network. For example, the communication board 915 may be connected to a LAN (local area network), the Internet, a WAN (wide area network), a SAN (storage area network), or the like.

The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924.
The programs in the program group 923 are executed by the CPU 911 using the operating system 921 and the window system 922.

The RAM 914 temporarily stores at least part of the operating system 921 program and application programs to be executed by the CPU 911.
The RAM 914 stores various data necessary for processing by the CPU 911.

The ROM 913 stores a BIOS (Basic Input Output System) program, and the magnetic disk device 920 stores a boot program.
When the test pattern management apparatus 100 is activated, the BIOS program in the ROM 913 and the boot program in the magnetic disk device 920 are executed, and the operating system 921 is activated by the BIOS program and the boot program.

  The program group 923 stores programs that execute the functions described as “˜unit” and “˜generator” in the description of the first and second embodiments. The program is read and executed by the CPU 911.

In the file group 924, in the description of the first and second embodiments, “analysis of”, “extraction of”, “comparison of”, “change of”, “evaluation of”, “update of” ”,“ Setting of ”,“ registration of ”,“ selection of ”, etc., information, data, signal values, variable values, and parameters indicating the results of the processing are represented by“ ˜file ”or“ ˜ It is stored as each item of “Database”.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, and calculated. Used for CPU operations such as calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, operation, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
In addition, the arrows in the flowcharts described in the first and second embodiments mainly indicate input / output of data and signals, and the data and signal values are the RAM 914 memory, the FDD 904 flexible disk, the CDD 905 compact disk, and the magnetic field. Recording is performed on a recording medium such as a magnetic disk of the disk device 920, other optical disks, mini disks, DVDs, and the like. Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

  In addition, what is described as “to part” and “to generator” in the description of Embodiments 1 and 2 may be “to circuit”, “to device”, and “to device”. It may be “˜step”, “˜procedure”, “˜processing”. That is, what is described as “˜unit” and “˜generator” may be realized by firmware stored in the ROM 913. Alternatively, it may be implemented only by software, or only by hardware such as elements, devices, substrates, and wirings, by a combination of software and hardware, or by a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911. That is, the program causes the computer to function as “˜unit” and “˜generator” in the first and second embodiments. Alternatively, the procedures and methods of “˜unit” and “˜generator” of the first and second embodiments are executed by a computer.

  As described above, the test pattern management apparatus 100 shown in the first and second embodiments includes a CPU as a processing device, a memory as a storage device, a magnetic disk, a keyboard as an input device, a mouse, a communication board, and a display device as an output device, A computer including a communication board and the like, and as described above, functions indicated as “˜unit” and “˜generator” are realized by using these processing devices, storage devices, input devices, and output devices.

  1 probability setting file, 2 test pattern generator, 3 test pattern, 4 test bench, 5 LSI, 6 result file, 7 execution log, 8 failure factor history, 9 failure history analysis unit, 10 probability setting file generator, 11 test pattern filter , 12 pattern generation summary information, 13 initial probability setting file, 14 result file input unit, 100 test pattern management device.

Claims (12)

A test pattern management device for managing test patterns used for simulation,
It acquires multiple types of parameter items, each of which takes multiple parameter values, acquires selection ratio information indicating the selection ratio of each parameter value for each parameter item, and sets the parameter value for each parameter item indicated in the acquired selection ratio information. According to the selection ratio, a test pattern generation unit that generates a plurality of test patterns by selecting a parameter value for each parameter item;
A simulation result information input unit for inputting simulation result information indicating a result of simulation using the test pattern generated by the test pattern generation unit;
A test pattern management, comprising: a selection ratio changing section that analyzes the simulation result information input by the simulation result information input section and changes a parameter value selection ratio in each parameter item of the selection ratio information. apparatus. The simulation result information input unit
Enter the simulation result information indicating the failure test pattern where the failure occurred in the simulation.
The selection ratio changing unit
2. The test pattern according to claim 1, wherein a parameter value appearing in the failure occurrence test pattern indicated in the simulation result information is analyzed to change a parameter value selection ratio in each parameter item of the selection ratio information. Management device. The selection ratio changing unit
The test pattern management apparatus according to claim 2, wherein a combination of parameter values having a high appearance frequency in the failure occurrence test pattern is extracted, and a selection ratio of each parameter value included in the extracted combination is increased. The test pattern generation unit
The test pattern management apparatus according to claim 1, wherein a new test pattern is generated using the selection ratio information whose selection ratio has been changed by the selection ratio changing unit. A test pattern management device for managing test patterns used for simulation,
It acquires multiple types of parameter items, each of which takes multiple parameter values, acquires selection ratio information indicating the selection ratio of each parameter value for each parameter item, and sets the parameter value for each parameter item indicated in the acquired selection ratio information. According to the selection ratio, a test pattern generation unit that generates a plurality of test patterns by selecting a parameter value for each parameter item;
A simulation result information input unit for inputting simulation result information indicating a failure occurrence test pattern in which a failure has occurred in the simulation;
Analyzing the parameter values that appear in the defect occurrence test pattern, and extracting a specific parameter value combination as an exclusion target combination, and
From the plurality of test patterns generated by the test pattern generation unit, a test pattern including a combination of parameter values that matches the exclusion target combination extracted by the defect analysis unit is extracted, and the extracted test pattern A test pattern management apparatus comprising: a test pattern excluding unit that excludes a pattern from a simulation target. The defect analysis unit
The test pattern management apparatus according to claim 5, wherein a combination of parameter values having a high appearance frequency in the failure occurrence test pattern is extracted as an exclusion target combination. The test pattern exclusion unit
Extracting a test pattern including a combination of parameter values that matches the exclusion target combination from among the test patterns not yet used in the simulation among the plurality of test patterns generated by the test pattern generation unit. 7. The test pattern management apparatus according to claim 5, wherein the test pattern management apparatus is characterized in that: The test pattern generation unit
The test pattern management apparatus according to claim 1, wherein a test pattern used for logic verification simulation of an integrated circuit is generated. A test pattern management method in which a computer manages test patterns used for simulation,
Each of the parameter items indicated by the acquired selection ratio information is acquired by the computer indicating a plurality of types of parameter items each having a plurality of parameter values and indicating a selection ratio of each parameter value for each parameter item. A test pattern generating step for generating a plurality of test patterns by selecting a parameter value for each parameter item according to a parameter value selection ratio in
A simulation result information input step in which the computer inputs simulation result information indicating a result of simulation using the test pattern generated by the test pattern generation step;
The computer has a selection ratio changing step of analyzing the simulation result information input in the simulation result information input step and changing the selection ratio of the parameter value in each parameter item of the selection ratio information. Test pattern management method. A test pattern management method in which a computer manages test patterns used for simulation,
Each of the parameter items indicated by the acquired selection ratio information is acquired by the computer indicating a plurality of types of parameter items each having a plurality of parameter values and indicating a selection ratio of each parameter value for each parameter item. A test pattern generating step for generating a plurality of test patterns by selecting a parameter value for each parameter item according to a parameter value selection ratio in
A simulation result information input step in which the computer inputs simulation result information indicating a failure occurrence test pattern in which a failure has occurred in the simulation;
The computer analyzes a parameter value appearing in a failure occurrence test pattern, and extracts a combination of specific parameter values as an exclusion target combination,
The computer extracts a test pattern including a combination of parameter values that matches the exclusion target combination extracted by the defect analysis step from the plurality of test patterns generated by the test pattern generation step, A test pattern management method comprising: a test pattern exclusion step for excluding an extracted test pattern from a simulation target. To the computer that manages the test pattern used for simulation,
It acquires multiple types of parameter items, each of which takes multiple parameter values, acquires selection ratio information indicating the selection ratio of each parameter value for each parameter item, and sets the parameter value for each parameter item indicated in the acquired selection ratio information. A test pattern generation process for generating a plurality of test patterns by selecting a parameter value for each parameter item according to a selection ratio;
A simulation result information input process for inputting simulation result information indicating a result of a simulation using the test pattern generated by the test pattern generation process;
A program that analyzes the simulation result information input by the simulation result information input process, and executes a selection ratio changing process for changing a parameter value selection ratio in each parameter item of the selection ratio information. To the computer that manages the test pattern used for simulation,
It acquires multiple types of parameter items, each of which takes multiple parameter values, acquires selection ratio information indicating the selection ratio of each parameter value for each parameter item, and sets the parameter value for each parameter item indicated in the acquired selection ratio information. A test pattern generation process for generating a plurality of test patterns by selecting a parameter value for each parameter item according to a selection ratio;
A simulation result information input process for inputting simulation result information indicating a defect occurrence test pattern in which a defect has occurred in the simulation;
Analyzing the parameter values that appear in the defect occurrence test pattern, and extracting the combination of specific parameter values as the exclusion target combination,
From the plurality of test patterns generated by the test pattern generation process, a test pattern including a combination of parameter values that matches the exclusion target combination extracted by the defect analysis process is extracted, and the extracted test pattern And a test pattern exclusion process for excluding a pattern from a simulation target.