JP2010206578A - Input rail-to-rail differential amplification circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an input rail-to-rail differential amplification circuit of which the circuit configuration is simplified and which is capable of keeping input transconductance constant. <P>SOLUTION: The input rail-to-rail differential amplification circuit comprises: a level shifter for shifting the level of a rail-to-rail small amplitude differential signal upon receipt of the small amplitude differential signal via an MOS transistor of a first type; and a differential amplifier for receiving output of the level shifter and amplifying the output via an MOS transistor of a second type. The MOS transistor of the first type is a native MOS, thereby solving the problem. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit that receives and amplifies and outputs a rail-to-rail small amplitude differential signal.

  Conventionally, as disclosed in Non-Patent Document 1, an input rail-to-rail (Rail-to-Rail) in which a common-mode input voltage of a differential amplifier circuit is made to correspond from a negative power supply voltage (VSS) to a positive power supply voltage (VDD). -Rail) Differential amplifier circuit technology has been reported.

  However, in the input rail-to-rail differential amplifier circuit of Non-Patent Document 1, the common-mode input voltage level can correspond to the entire range (Rail-to-Rail) from VSS to VDD. There is a problem that (Gm) varies depending on the common-mode input voltage level. This is because the type of input differential pair that operates depends on the common-mode input voltage level.

  That is, when the common-mode input voltage is close to VSS, the transconductance (Gmp) of the PMOS receiving input differential pair is dominant, and when the common-mode input voltage is close to VDD, the transformer of the NMOS receiving input differential pair is dominant. This is because the conductance (Gmn) becomes dominant and the sum of Gmp and Gmn becomes the transconductance of the circuit when the common-mode input voltage is at an intermediate level between VDD and VSS.

  On the other hand, the circuit disclosed in Patent Document 1 is an NMOS / PMOS dual-type differential rail-to-rail input amplification stage, and the output is small with a voltage of about half the power supply voltage. It is an amplitude differential signal. In the circuit of Patent Document 1, a level shifter is provided in front of each input stage of the NMOS / PMOS in order to eliminate the dependency of the transconductance Gm on the input common-mode voltage level in a normal rail-to-rail circuit.

Patent Document 1 proposes to use a source follower circuit made of NMOS or PMOS as an input stage of a small amplitude differential signal that constitutes the level shifter.
However, in the level shifter using an NMOS or PMOS source follower proposed by Patent Document 1, when an NMOS is used in the input stage, when a common-mode input voltage less than the threshold voltage (Vth) is input, Both NMOS transistors are turned off, and there is a problem that signals cannot be transmitted to the differential amplifier circuit at the subsequent stage. When a PMOS is used for the input stage, when a common-mode input voltage between the positive power supply voltage (VDD) and (positive power supply voltage (VDD) −threshold voltage (Vth)) is input, Both PMOSs are turned off, and there is a problem that signals cannot be transmitted to the differential amplifier circuit at the subsequent stage.
That is, a signal in the voltage range of VSS to Vth and a voltage range of (VDD−Vth) to VDD cannot be input, and input rail-to-rail cannot be achieved.

JP 2002-344260 A

Babanezhad J.N .: 'A Rail-to-Rail CMOS Op Amp,' IEEE J. Solid-State Circuits, vol. Sc-23, pp. 1414-1417, 1988

  An object of the present invention is to provide an input rail-to-rail differential amplifier circuit that has a simple circuit configuration and can make the input transconductance constant.

  In order to solve the above problems, the present invention provides a level shifter for receiving a rail-to-rail small amplitude differential signal by a first type MOS transistor and shifting the level of the small amplitude differential signal; An input rail-to-rail differential amplifier circuit comprising: a differential amplifier for receiving and amplifying and outputting the output of the level shifter by a type MOS transistor; and wherein the first type MOS transistor is a native MOS I will provide a.

  According to the present invention, by using a native (depletion type) PMOS or native NMOS for the input stage of the level shifter, it is possible to completely support input rail-to-rail with a simple circuit configuration. Further, according to the present invention, the input transconductance (Gm) can be made constant by using only the NMOS or PMOS differential amplifier circuit.

1 is a circuit diagram showing an embodiment of an input rail-to-rail differential amplifier circuit according to the present invention. FIG. It is a circuit diagram which shows other one Embodiment of the input rail to rail differential amplifier circuit which concerns on this invention.

  An input rail-to-rail differential amplifier circuit according to the present invention will be described below in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a circuit diagram of an embodiment showing a configuration of an input rail-to-rail differential amplifier circuit of the present invention. An input rail-to-rail differential amplifier circuit 10 shown in FIG. 1 includes a PMOS receiving type level shifter (hereinafter also simply referred to as level shifter) 12, an NMOS receiving type differential amplifier circuit (hereinafter also simply referred to as differential amplification circuit) 14, and It is constituted by. In the following, the term “PMOS / NMOS” refers to an enhancement type PMOS / NMOS.

  The level shifter 12 receives a rail-to-rail small-amplitude differential input signal, level-shifts it, and outputs it to the differential amplifier circuit 14. The level shifter 12 includes a constant current source 16, PMOSs 24a, 24b, and 24c constituting a current mirror circuit, and two native (depletion type) PMOSs 20a and 20b that serve as switching elements that receive and detect differential input signals INN and INP. It is constituted by.

  The sources of the PMOSs 24a, 24b, and 24c are connected to a node connected to the high potential voltage VDD, and the gates are connected to the drain of the PMOS 24a. The drain of the PMOS 24a is connected to the ground (GND) through the constant current source 16. The sources of the native PMOSs 20a and 20b are connected to the drains of the PMOSs 24b and 24c, the drains are connected to the ground, and the differential input signals INN and INP are connected to the gates, respectively.

  Subsequently, the differential amplifier circuit 14 includes two PMOSs 26a and 26b constituting a current mirror circuit, two NMOSs 22a and 22b serving as switching elements that receive and detect the output signal of the level shifter 12, and a constant current source 18. It is configured.

  The sources of the PMOSs 26a and 26b are connected to a node connected to the high potential voltage VDD, and the gates are connected to the drain of the PMOS 26a. The drains of the NMOSs 22a and 22b are connected to the drains of the PMOSs 26a and 26b, the sources are connected to the ground via the constant current source 18, and the gates are connected to the sources of the PMOSs 20a and 20b constituting the level shifter 12, respectively. Yes.

  A single-ended output signal OUT is output from a node between the drain of the PMOS 26b and the drain of the NMOS 22b.

  In FIG. 1, the connection between the sources of the PMOSs 24a, 24b, 24c and the PMOSs 26a, 26b constituting the current mirror circuit and the high potential voltage VDD is omitted. The source of 26b may be directly connected to the high potential voltage, or circuits of various configurations may be connected between them if necessary.

  Next, the operation of the input rail-to-rail differential amplifier circuit 10 will be described.

  The input rail-to-rail differential amplifier circuit 10 receives small-amplitude differential input signals INP and INN, which are differential signals with a small amplitude Vid centered on the common-mode input voltage Vicm.

First, a case where two enhancement type PMOSs are used instead of the native PMOSs 20a and 20b in the input stage of the level shifter 12 will be described.
In the enhancement type PMOS, when the differential input signals INP and INN having a voltage in the range of VDD to (VDD−Vth) are input, the absolute value | Vgs | of the gate-source voltage Vgs is smaller than Vth. Become. For this reason, both PMOSs are turned off at the same time, and the L level / H level of the differential input signal cannot be detected, and a signal cannot be transmitted to the differential amplifier circuit 14 at the subsequent stage. Therefore, only a signal having a voltage in the range of 0V to (VDD−Vth) can be input, and a rail-to-rail signal cannot be input.

Next, the case of the present invention, that is, the case where a native PMOS (depletion type PMOS) is used as the PMOS 20a, 20b of the input stage of the level shifter 12 will be described.
The native PMOS, for example, has a threshold voltage Vth ≧ 0 V, and is turned on even when the gate-source voltage Vgs (= gate voltage Vg−source voltage Vs) ≧ 0 V.
Since the differential input signals INP and INN of the level shifter 12 are rail-to-rail, when the common-mode input voltage Vicm is close to VDD, the gate voltage Vg ≧ the source voltage Vs may be satisfied. That is, in the case of the native PMOS receiving type, Vth ≧ 0V, so that even if Vgs ≧ 0V, for example, the differential input signal INP or the L level of the INN = VDD, the native PMOSs 20a and 20b are turned on.

  Here, the differential input signals INP and INN are centered on the common-mode input voltage Vicm, and when one is at the H level, the other is at the L level. Therefore, the native PMOS of the input stage on the side where the L level is input to the gate is The H level is turned on more strongly than the native PMOS of the input stage on the side to which the H level is inputted (on resistance is lowered as the power is turned on more strongly), and the flowing current Id is also increased. Therefore, for the sake of convenience, in the following description, the native PMOS of the input stage to which the L level is input (the more strongly turned on) is expressed as ON, and the native PMOS of the input stage to which the other H level is input is expressed as OFF. . The NMOS of the input stage of the differential amplifier circuit 14 is also expressed in the same way.

  That is, in the level shifter 12, even when the L level is input at a voltage level close to VDD as the differential input signals INP and INN, one of the native PMOSs 20a and 20b is turned on and the other is turned off. A signal can be transmitted to the differential amplifier circuit 14.

  For example, when the L level is input to the differential input signal INP of the level shifter 12 and the H level is input to the differential input signal INN, the native PMOS 20a is turned off and the native PMOS 20b is turned on. When the native PMOS 20a is turned off, the source of the native PMOS 20a becomes H level, and the gate input of the NMOS 22a of the differential amplifier circuit 14 becomes H level. When the native PMOS 20b is turned on, the source of the native PMOS 20b becomes L level, and the gate input of the NMOS 22b of the differential amplifier circuit 14 becomes L level.

The differential amplifier circuit 14 detects the minute output potential difference between the differential output signals output from the level shifter 12, that is, the signals after the differential input signals INP and INN are level-shifted, by the NMOSs 22a and 22b in the input stage. Is amplified and output.
As in the above example, the gate input signal of the NMOS 22a is high potential (H level) (the differential input signal INN is H level), and the gate input signal of the NMOS 22b is low potential (L level) (the differential input signal INP is L). Level), the NMOS 22a is turned on and the NMOS 22b is turned off. At this time, the drain of the NMOS 22a becomes L level, the drain of the NMOS 22b becomes H level, and the single-ended output signal OUT output from the node between the drain of the PMOS 26b and the drain of the NMOS 22b becomes H level.

  When the differential input signal INP is at the H level and the differential input signal INN is at the L level, the operations of the level shifter 12 and the differential amplifier circuit 14 are the same, the native PMOS 20a is on, the native PMOS 20b is off, and the NMOS 22a The gate input signal is L level, the gate input signal of the NMOS 22b is H level, and the single end output signal OUT is L level.

The differential output signal of the level shifter 12 input to the differential amplifier circuit 14 is shifted in level compared to the differential input signals INP and INN, and can be amplified by the differential amplifier circuit 14 that is an NMOS receiving type. That is, the differential output signal of the level shifter 12 is output in a range where one of the NMOSs 22a and 22b is turned on and the other is turned off. The voltage of the differential output signal of the level shifter 12 is within the allowable range of the input voltage of the NMOS receiving type differential amplifier circuit 14, and the differential amplifier circuit 14 amplifies and outputs the rail-to-rail differential input signals INP and INN. be able to.
Further, since the differential amplifier circuit 14 is an NMOS receiving type differential amplifier circuit, that is, it is not both NMOS and PMOS receiving, the transconductance (Gm) is constant, and the output waveform of the single-ended output signal OUT is Output without distortion.

  Further, in the present invention, like the input rail-to-rail differential amplifier circuit 50 shown in FIG. 2, the MOS that receives the differential input signals INP and INN of the level shifter 52 is a native NMOS, and the differential amplifier circuit 54 is a PMOS receiving type. It can also be. Since the operation of the input rail-to-rail differential amplifier circuit 50 is the same as that of the input rail-to-rail differential amplifier circuit 10, repeated description thereof is omitted.

  In the present invention, the first and second type MOS transistors are PMOS and NMOS. When one is PMOS, the other is NMOS, and when one is NMOS, the other is PMOS. .

  As described above, the input rail-to-rail differential amplifier circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications can be made without departing from the scope of the present invention. May be performed.

10, 50 Input rail-to-rail differential amplifier circuit 12, 52 Level shifter 14, 54 Differential amplifier circuit 16, 18 Constant current source 20 Native PMOS
22 NMOS
24, 26 PMOS

Claims (1)

A level shifter that receives a rail-to-rail small-amplitude differential signal and shifts the level of the small-amplitude differential signal by a first-type MOS transistor;
A differential amplifier that receives and amplifies and outputs the output of the level shifter by a second type MOS transistor;
An input rail-to-rail differential amplifier circuit, wherein the first type MOS transistor is a native MOS.

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