JP2010206354A - Reference frequency generator and reference frequency generation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent timing of output signals from varying rapidly on output switching at current and spare sides in redundant reference frequency generation systems. <P>SOLUTION: In a current-side reference frequency generator 51, a 1PPS signal generated by a GPS receiver 21a of an own apparatus is supplied to a PLL circuit 22a. In a spare-side reference frequency generator 52, a 1 Hz signal output from a PLL circuit 22a of the current-side reference frequency generator 51 is supplied to a PLL circuit 22b via a first transmission path. The 1 Hz signal input to the spare side is returned to the current side via a second transmission path having the amount of delay equal to that of the first transmission path. The current-side reference frequency generator 51 outputs a signal for correction, based on a time difference between a 1 Hz signal from the PLL circuit 22a of an own apparatus and a 1 Hz signal output to the spare side for returning. A spare-side reference frequency generator 52 adjusts the phase of the output signal of the PLL circuit 22b, based on the signal for correction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention mainly relates to a reference frequency generator capable of realizing redundancy by constructing a duplex system.

  Conventionally, for example, in a terrestrial digital broadcasting system and a mobile communication system, a reference frequency generator is used to supply a reference frequency signal common to all transmitting stations and base stations. In these systems, if the supply of the reference frequency signal is interrupted for some reason, such as a failure of the reference frequency generator, service cannot be provided. For this reason, in each transmitting station and base station, in order to reduce the influence of the occurrence of failure, it has been conventionally practiced to duplicate the reference frequency generator and operate it in two systems, an active system and a standby system.

  Patent Document 1 discloses a dual system type reference frequency signal generator. The dual system type reference frequency signal generator disclosed in Patent Document 1 includes two reference frequency signal generation means. Each reference frequency signal generation means can generate a 10 MHz reference frequency signal by performing phase control based on the positioning 1PPS signal extracted from the GPS positioning signal. In the dual system type reference frequency signal generator, the reference frequency signal generating means selected for output is used as the active side, and the reference frequency signal generating means not selected for output is operated as the backup side. Each reference frequency signal generation means includes reference 1PPS signal generation means for dividing a 10 MHz reference frequency signal to generate a reference 1PPS signal. The working reference frequency signal generating means generates a 10 MHz reference frequency signal based on the positioning 1PPS signal, and the backup reference frequency signal generating means is 10 MHz based on the reference 1PPS signal generated by the working side. Generate a signal.

  Patent Document 1 assumes that a dual system type reference frequency signal generator that has a simple structure and hardly causes a phase shift of the reference frequency signal at the time of switching can be provided by the above configuration.

JP 2008-35111 A

  However, in the configuration of Patent Document 1 described above, the output phase of the reference frequency signal on the standby side has a delay (transmission line delay) caused by the cable connecting the active side and the standby side, compared to the active side. Accordingly, when the output is switched from the active to the standby, it is inevitable that a phase shift corresponding to the transmission delay of the connection line occurs in the output signal, and a rapid variation in timing occurs. Such discontinuity of the reference frequency signal causes a transmission signal abnormality in the transmitting station or the base station.

  The present invention has been made in view of the above circumstances, and its purpose is to output the timing and frequency of the output signal even when the output is switched between the reference frequency generator on the active side and the reference frequency generator on the standby side. It is in providing the structure which can suppress the rapid fluctuation | variation of.

Means and effects for solving the problems

  The problems to be solved by the present invention are as described above. Next, means for solving the problems and the effects thereof will be described.

  According to a first aspect of the present invention, a reference frequency generation system having the following configuration is provided. That is, the reference frequency generation system is configured by connecting a first reference frequency generation device and a second reference frequency generation device. The first reference frequency generator is operable as a working side. The second reference frequency generator can operate as a spare side. When the second reference frequency generator operates as a spare side, the synchronization circuit of the second reference frequency generator locks to a timing signal output from the synchronization circuit of the first reference frequency generator, and the second reference frequency generator The phase of the reference frequency signal output from the frequency generator is adjusted so as to correct a transmission delay caused by a connection line between the first reference frequency generator and the second reference frequency generator.

  As a result, the phase of the reference frequency signal on the standby side is adjusted in consideration of the transmission delay of the connection line, and the reference frequency signal having the same phase can be output on the active side and the backup side. Therefore, it is possible to prevent the output signal timing from abruptly changing when the output is switched between the active side and the standby side.

  According to a second aspect of the present invention, there is provided the following configuration in a reference frequency generator that can be used as a working side in a redundant system. That is, the reference frequency generator includes a synchronization circuit, a signal output unit, a return signal input unit, and a correction signal output unit. The synchronization circuit can output a signal having a predetermined frequency. The signal output unit can output a synchronization circuit output signal, which is a signal output from the synchronization circuit, to a user side device. The return signal input unit inputs a return signal from the reference frequency generator on the other side via the user side device. The correction signal output unit outputs a correction signal based on a signal delay amount that is a delay amount of the return signal with respect to the synchronous circuit output signal to the reference frequency generator on the other side.

  As a result, the signal output from the synchronization circuit of the own device can be supplied to the backup side, and the correction signal based on the delay amount of the return signal can be transmitted to the backup side. Therefore, as a reference frequency generator on the standby side, it synchronizes with the signal from the synchronization circuit on the working side, adjusts the phase of the reference frequency signal in consideration of the transmission delay, and matches the phase with the working side. A signal can be output.

  According to a third aspect of the present invention, there is provided the following configuration in a reference frequency generator that can be used as a backup side in a redundant system. That is, the reference frequency generator includes a synchronization circuit, a signal input unit, a switching unit, a return signal output unit, a correction signal input unit, and a phase adjustment unit. The synchronization circuit can output a signal having a predetermined frequency. The signal input unit inputs a signal output from the synchronization circuit of the reference frequency generating device on the working side as an output signal of the counterpart synchronization circuit via the user device. The switching unit normally locks the synchronization circuit of the own device to the output signal of the other party's synchronization circuit, and when the own device is switched to the active side, the synchronization circuit of the own device becomes the reference signal of the own device. Lock it. The return signal output unit outputs the partner-side synchronization circuit output signal input from the signal input unit to a user-side device. A correction signal output from the reference frequency generator on the working side is input to the correction signal input unit. The phase adjustment unit adjusts the phase of the output signal of the synchronization circuit of the own device based on the correction signal input from the correction signal input unit.

  As a result, when operating as a spare side, the own synchronization circuit can be locked to the synchronization circuit output signal of the active side reference frequency generator. Further, the phase of the signal output from the own device can be automatically adjusted in consideration of the transmission delay when the reference signal is transmitted from the active side to the standby side without requiring complicated adjustment work. Therefore, the phase of the waveform output by the own device can be made to exactly match the phase of the waveform output by the reference frequency generator on the active side, so that the phase of the output waveform when the own device is switched to the active side can be adjusted. Rapid fluctuation can be suppressed.

  According to a fourth aspect of the present invention, there is provided the following configuration in a reference frequency generator that can operate at least as either a working side or a standby side in a redundant system. That is, the reference frequency generator includes a synchronization circuit, a signal output unit, a signal input unit, a switching unit, a return signal output unit, a return signal input unit, a correction signal output unit, and a correction signal input. And a phase adjustment unit. The synchronization circuit can output a signal having a predetermined frequency. The signal output unit outputs a synchronization circuit output signal, which is a signal output from the synchronization circuit, to the user side device. The signal input unit receives the synchronization circuit output signal of the counterpart reference frequency generator as the counterpart synchronization circuit output signal via the user device. The switching unit locks the synchronization circuit to a reference signal when the own device operates as a working side, and locks the synchronization circuit to the output signal from the other side when the own device operates as a backup side. Let The return signal output unit outputs the counterpart side synchronization circuit output signal input from the signal input unit to the user side device. The return signal input unit receives a signal from the return signal output unit of the reference frequency generator on the other side as a return signal via the user side device when the own device operates as the active side. The correction signal output unit sends a correction signal based on a signal delay amount, which is a delay amount of the return signal with respect to the synchronous circuit output signal, to the reference frequency generator on the other side when the own device operates as the active side. Output. The correction signal input unit receives the correction signal when the own apparatus operates as a spare side. The phase adjustment unit adjusts the phase of the output signal of the synchronization circuit of the own device based on the correction signal input from the correction signal input unit when the own device operates as a backup side.

  As a result, the synchronization circuit of the reference frequency generator on the standby side is locked to the signal output from the synchronization circuit of the reference frequency generator on the active side. In addition, the phase of the signal output by the reference frequency generator on the standby side is automatically adjusted in consideration of the transmission delay when transmitting the output signal of the synchronization circuit from the active side to the standby side without requiring complicated adjustment work. Can be adjusted. Therefore, the phase of the waveform output from the standby-side reference frequency generator can be made to exactly match the phase of the waveform output from the active-side reference frequency generator, so that it occurs when switching between the active side and the backup side. Abrupt fluctuations in the phase of the output waveform can be suppressed.

  In the reference frequency generation device, when the own apparatus operates as a backup side, the phase adjustment unit advances the phase of the output signal of the synchronization circuit by a time corresponding to half of the signal delay amount. It is preferable that

  As a result, when the output signal of the synchronization circuit is exchanged between two reference frequency generators using two transmission paths with uniform delay amounts, the active side and the standby side can be easily processed. The phase of the output signal can be matched.

  According to a fifth aspect of the present invention, there is provided a reference frequency generation system including at least two reference frequency generation devices.

  As a result, it is possible to provide a reference frequency generation system that can reduce maintenance costs and reduce phase fluctuations when switching between the active side and the standby side.

  The reference frequency generation system preferably has the following configuration. That is, the signal output unit of the reference frequency generator on one side and the signal input unit of the reference frequency generator on the other side are connected by a first transmission path including a delay of the user side device. The return signal input unit of the reference frequency generator on one side and the return signal output unit of the reference frequency generator on the other side are connected by a second transmission path including a delay of the user side device. The transmission delay of the first transmission path matches the transmission delay of the second transmission path.

  As a result, the phase of the output signal can be matched between the active side and the standby side by simple control, and the configuration of the reference frequency generation system can be simplified.

1 is a block diagram showing an electrical configuration of a reference frequency generation system according to an embodiment of the present invention. The block diagram which shows the detailed structure of a 1st reference frequency generator. The block diagram which shows the detailed structure of a 2nd reference frequency generator. The block diagram which shows the structure of the reference frequency generator of a modification.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an electrical configuration of a reference frequency generation system 60 according to an embodiment of the present invention. FIG. 2 is a block diagram showing a detailed configuration of the first reference frequency generator 51. FIG. 3 is a block diagram showing a detailed configuration of the second reference frequency generator 52.

  A reference frequency generation system 60 shown in FIG. 1 includes two reference frequency generation devices 51 and 52 having the same configuration. In the reference frequency generating system 60 of the present embodiment, the first reference frequency generating device 51 is normally set to operate as the active side, and the second reference frequency generating device 52 is set to operate as the standby side (standby side). Yes. On the other hand, when a failure occurs in the first reference frequency generator 51, the second reference frequency generator 52 is switched to operate as the active side.

  The reference frequency generation device 51 includes a first output terminal 11a capable of outputting a 10 MHz signal to the user side device 70 and a second output terminal 12a capable of outputting a 1 Hz signal. Similarly, the reference frequency generation device 52 includes a first output terminal 11b that can output a 10 MHz signal to the user-side device 70, and a second output terminal 12b that can output a 1 Hz signal. FIG. 1 shows an example in which only a 1 Hz signal output from the second output terminals 12a and 12b is input to the user side device 70 via a cable. However, depending on the circumstances, the user side device 70 is shown. Of course, both a 10 MHz signal and a 1 Hz signal may be input, or only a 10 MHz signal may be input.

  The user-side device 70 is configured as, for example, a terrestrial digital broadcast or a mobile communication base station. The user side device 70 performs various processes using a signal from the reference frequency generation device operating as the active side of the two reference frequency generation devices 51 and 52, and provides a communication service. The reference frequency generators 51 and 52 are, for example, a reference frequency synchronized with 1 second of Coordinated Universal Time (UTC) or 1 second of GPS (GNSS) reference time in accordance with a reference determined by the user side device 70 (user system). Output a signal.

  Next, detailed configurations of the reference frequency generation device 51 and the reference frequency generation system 60 will be described. Since the two reference frequency generators 51 and 52 have the same configuration as described above, only the configuration of the reference frequency generator 51 will be described as a representative unless otherwise specified. The description of the configuration is omitted. In the drawing, the first reference frequency generator 51 side configuration uses a symbol with “a” at the end of the number, and the corresponding configuration on the second reference frequency generator 52 side is the same. A symbol with “b” at the end of the number is used.

  The reference frequency generator 51 includes a GPS receiver 21a, a phase lock loop circuit (PLL circuit, synchronous circuit) 22a, a phase adjustment signal output circuit 23a, a signal switcher (switching unit, supply signal switching unit) 26a, A setting storage unit 27a, and a delay calculator (phase adjustment unit) 28a.

  A GPS antenna 61 installed outside the reference frequency generator 51 is electrically connected to the GPS receiver 21a. The GPS receiver 21a performs positioning calculation based on the positioning signal received by the GPS antenna 61, and generates a pulse signal (1PPS signal, reference signal) once per second based on the positioning calculation. This pulse signal is appropriately calibrated in the GPS receiver 21a so as to be accurately synchronized with 1 second of Coordinated Universal Time (UTC).

  As shown in FIG. 2, the signal switch 26a is disposed between the GPS receiver 21a and a phase comparator 31a (FIG. 2) that is an input stage of the PLL circuit 22a. The signal switch 26a is configured to supply the 1PPS signal from the GPS receiver 21a to the phase comparator 31a as a reference timing signal when the reference frequency generator 51 operates as the active side.

  The PLL circuit 22a is configured to generate 10 MHz and 1 Hz signals that are PLL-locked to the reference timing signal, and to change the phase of the waveform of the signal as appropriate. As shown in a detailed block diagram in FIG. 2, the PLL circuit 22a includes a phase comparator 31a, a loop filter 32a, a voltage control oscillator 33a, an N frequency divider 34a, and a delay generator 35a. ing.

  The phase comparator 31a has a phase difference between the reference timing signal and the phase comparison signal obtained by dividing the signal output from the voltage controlled oscillator 33a by the N divider 34a and delaying it by the delay generator 35a. Is detected. Then, the phase comparator 31a generates a signal (phase difference signal) indicating the detected phase difference and outputs the signal to the loop filter 32a.

  The loop filter 32a is configured by a low-pass filter or the like, and generates a control voltage signal by averaging the voltage level of the phase difference signal over time. The control voltage signal generated by the loop filter 32a is input to the voltage controlled oscillator 33a.

  The voltage controlled oscillator 33a is configured as a rubidium oscillator, for example, and outputs a signal having a frequency that changes in accordance with the control voltage signal input from the loop filter 32a. In the present embodiment, when the PLL circuit 22a is locked to the 1PPS signal (reference signal, reference timing signal) from the GPS receiver 21a, the frequency of the output signal of the voltage controlled oscillator 33a is controlled to be 10 MHz. The signal waveform output from the voltage controlled oscillator 33a is output to the first output terminal 11a. The output signal of the voltage controlled oscillator 33a is also input to the N frequency divider 34a.

  The N divider 34a divides the 10 MHz signal input from the voltage controlled oscillator 33a to generate a 1 Hz signal. Therefore, the frequency division ratio of the N frequency divider 34a is 1 / 10,000,000 (N = 10000000). The 1 Hz signal output from the N frequency divider 34a is output to the second output terminal 12a and also output to the delay generator 35a.

  The delay generator 35a generates a signal having a delay with respect to the signal input from the N frequency divider 34a, and outputs the signal to the phase comparator 31a as a phase comparison signal. The delay time (delay amount) of the output signal of the delay generator 35a with respect to the signal input from the N frequency divider 34a can be appropriately changed based on a control signal from a delay calculator 28a described later.

  As the delay generator 35a, various configurations can be adopted. For example, the shift amount can be changed by using a shift register, a delay line, or the like as the delay generator 35a and selecting one of a plurality of outputs with different delay amounts by a selector. When the waveform input to the delay generator 35a is an analog wave such as a sine wave or a sawtooth wave, a comparator is adopted as the delay generator 35a, and the delay amount is changed by changing the threshold value of the comparator. You can also. Furthermore, instead of realizing the delay by hardware as described above, the delay can also be realized by software.

  Here, in the state where the PLL circuit 22a is locked to the reference timing signal (for example, 1PPS signal from the GPS receiver 21a), the delay amount of the delay generator 35a is increased by the control of the delay calculator 28a. Think. In this case, since the phase comparison signal output from the delay generator 35a and input to the phase comparator 31a is delayed by that amount, a phase shift occurs with respect to the reference timing signal. Thereby, since the phase difference signal output from the phase comparator 31a changes, the control voltage signal input to the voltage controlled oscillator 33a via the loop filter 32a changes. Accordingly, the voltage controlled oscillator 33a operates so as to return the phase shift to zero by advancing the phase of oscillation so as to cancel out the delay increase by the delay generator 35a, and thereby the PLL lock to the reference timing signal. Will continue. As described above, the phase of the output waveform of the voltage controlled oscillator 33a can be advanced by increasing the delay amount of the delay generator 35a.

  Therefore, the phase of the 10 MHz signal and the 1 Hz signal output from the reference frequency generator 51 can be appropriately adjusted by the control of the delay generator 35a. Since the loop filter 32a of the PLL circuit 22a has a large time constant, the operation for returning the phase shift to zero as described above is performed gradually over time.

  As shown in FIG. 1, the reference frequency generator 51 includes a timing signal output terminal (signal output unit) 81a and a timing signal input terminal (signal input unit) 82a. The reference frequency generator 51 can output a 1 Hz signal (PLL output signal, synchronous circuit output signal) generated by its own PLL circuit 22a via a timing signal output terminal 81a. Further, the reference frequency generator 51 sends a 1 Hz signal generated by the PLL circuit 22b of the counterpart reference frequency generator 52 from the timing signal input terminal 82a to the counterpart 1 Hz signal (the counterpart PLL output signal, the counterpart synchronization circuit). Output signal).

  Furthermore, the reference frequency generator 51 includes a return signal output terminal (return signal output unit) 83a and a return signal input terminal (return signal input unit) 84a. The return signal output terminal 83a is configured to output a 1 Hz signal (partner side 1 Hz signal, partner side synchronization circuit output signal) input from the timing signal input terminal 82a as a return 1 Hz signal. The return signal input terminal 84a is configured to receive a return 1 Hz signal (return signal) output from the reference frequency generating device 52 on the counterpart side.

  In the reference frequency generation system 60, as shown in FIG. 1, the timing signal output terminal 81 a of the first reference frequency generation device 51 and the user side device 70 are connected by the first cable 101. Further, the user side device 70 and the timing signal input terminal 82 b of the second reference frequency generating device 52 are connected by a second cable 102. Further, the return signal output terminal 83 b of the second reference frequency generator 52 and the user side device 70 are connected by the third cable 103. Further, the user side device 70 and the return signal input terminal 84 a of the first reference frequency generation device 51 are connected by the fourth cable 104.

  Similarly to the above, the timing signal output terminal 81 b of the second reference frequency generation device 52 and the user side device 70 are connected by the fifth cable 105. Further, the user side device 70 and the timing signal input terminal 82 a of the first reference frequency generator 51 are connected by a sixth cable 106. Further, the return signal output terminal 83 a of the first reference frequency generation device 51 and the user side device 70 are connected by a seventh cable 107. Further, the user side device 70 and the return signal input terminal 84 b of the second reference frequency generator 52 are connected by an eighth cable 108.

  The reference frequency generator 51 further includes a control output terminal (correction signal output unit) 91a and a control input terminal (correction signal input unit) 92b. The reference frequency generator 51 is configured to output information for phase control of the waveform (phase control information, correction signal) to the control output terminal 91a when operating as the active side. . Further, when the reference frequency generator 51 is operating as a backup side, the reference frequency generator 51 is configured to output 10 MHz and 1 Hz signals output from the PLL circuit 22a of the own device based on the phase control information input from the control input terminal 92a. The phase can be adjusted.

  In the reference frequency generation system 60 of the present embodiment, the control output terminal 91a of the reference frequency generation device 51 on one side and the control input terminal 92b of the reference frequency generation device 52 on the other side are appropriate signal lines. It is connected. In addition, the control input terminal 92a of the reference frequency generator 51 on one side and the control output terminal 91b of the reference frequency generator 52 on the other side are connected by an appropriate signal line.

  With the above configuration, the reference frequency generator (upper reference frequency generator 51 in FIG. 1) operating as the active side among the reference frequency generators 51 and 52 is a 1 PPS signal (reference) output from the GPS receiver 21a. Signal) is supplied to the PLL circuit 22a as a reference timing signal, and the PLL circuit 22a outputs a 1 Hz signal to the output terminal 12a and the timing signal output terminal 81a. The 1 Hz signal is transmitted from the first cable 101, the delay 1 of the user side device 70, and the second cable 102 as a reference frequency generator operating as a backup side (the lower reference frequency generator of FIG. 1). 52) is input to the timing signal input terminal 82b.

  The GPS receiver 21b also operates in the reference frequency generator 52 on the standby side, and generates a 1PPS signal (reference signal) based on the positioning signal received from the GPS antenna 62. However, when the reference frequency generator 52 operates as a spare side, the signal switch 26b is not the 1PPS signal from its own GPS receiver 21b, but the working side 1 Hz signal (not shown) input from the timing signal input terminal 82b. The other side 1 Hz signal) is switched to be supplied to the PLL circuit 22b as a reference timing signal. Therefore, in the reference frequency generating device 52 operating as the standby side, the PLL circuit 22b is not the 1PPS signal of the GPS receiver 21b of its own device, but the working side 1 Hz signal input from the working side reference frequency generating device 51. Will lock in.

  The working-side 1 Hz signal input from the timing signal input terminal 82b in the standby-side reference frequency generator 52 is supplied to the PLL circuit 22b as described above and is output to the return signal output terminal 83b. The working-side 1 Hz signal output to the return signal output terminal 83b is input to the working-side reference frequency generator 51 via the third cable 103, the delay 3 of the user-side device 70, and the fourth cable 104. The signal is returned to the terminal 84a and input as a 1 Hz signal (return signal).

  The phase adjustment signal output circuit 23a included in the reference frequency generator 51 is a transmission path including the first cable 101, the delay 1 of the user side device 70, and the second cable 102 when the own device is operating as the active side. And the control information (phase control information) based on the transmission delay is output from the control output terminal 91a to the reference frequency generator 52 on the other side. As shown in FIG. 2, the phase adjustment signal output circuit 23a includes a delay amount measuring device 41a, a divider 42a, and a low-pass filter 43a.

  The delay amount measuring device 41a receives a 1 Hz signal output from its own PLL circuit 22a. When the reference frequency generator 51 operates as the active side, the return 1 Hz signal input from the return signal input terminal 84a is input to the delay amount measuring device 41a. With this configuration, the delay amount measuring device 41a in the reference frequency generator 51 on the working side measures the delay time of the return 1 Hz signal with respect to the reference timing signal (that is, the 1 Hz signal generated by the own PLL circuit 22a). In the following description, this delay time may be referred to as “signal delay amount”.

  Thus, there are two paths (that is, a path including the first cable 101, the delay 1 of the user side device 70, and the second cable 102, the third cable 103, the delay 3 of the user side device 70, and the fourth cable). The delay time generated when the 1 Hz signal reciprocates between the reference frequency generators 51 and 52 through the path 104) can be obtained.

  The first cable 101 and the fourth cable 104 have the same delay amount, and similarly, the second cable 102 and the third cable 103 have the same delay amount. In addition, the user side device 70 is designed so that the delay amounts of the two delays 1 and 3 coincide with each other. Therefore, the path consisting of the first cable 101, the delay 1 of the user side device 70, and the second cable 102, and the path consisting of the third cable 103, the delay 3 of the user side device 70, and the fourth cable 104 are the delay amount. The sum of is consistent with each other. The delay amount measuring device 41a outputs a signal corresponding to the obtained delay time to the divider 42a.

  The divider 42a divides the delay time (signal delay amount) input from the delay amount measuring device 41a by 2, and outputs a signal corresponding to the obtained value to the low-pass filter 43a. Here, since the two paths connecting the reference frequency generators 51 and 52 have the same amount of delay as described above, by dividing by 2 as described above, the delay time for one way of the path is obtained. can get. That is, in the divider 42a, the reference frequency generator 51 on the active side passes from the reference frequency generator 52 on the standby side via the path formed by the first cable 101, the delay 1 of the user side device 70, and the second cable 102. A delay that occurs when a 1 Hz signal is transmitted can be obtained. In the following description, the transmission delay based on one of the paths may be simply referred to as “path delay”.

  The low-pass filter 43a removes short-term jitter caused by external noise or environmental changes from the signal input from the divider 42a, and outputs it to the control output terminal 91a provided in the reference frequency generator 51. The phase control information output to the control output terminal 91a in this way is input to the control input terminal 92b in the reference frequency generator 52 on the counterpart side through the signal line.

  The delay calculator 28a is for adjusting the phase of the waveform output from the PLL circuit 22a to the user device 70. In the reference frequency generation device 51 operating as the active side, the delay calculator 28a applies only the delay corresponding to the delay parameter stored in the setting storage unit 27a to the delay generator 35 (see FIG. Set to 2). On the other hand, in the reference frequency generation device 52 operating as the backup side, the delay calculator 28b includes the path delay included in the phase control information input from the control input terminal 92b and the delay parameter of the setting storage unit 27b. In consideration of the above, an appropriate delay amount is set in the delay generator 35b. As described above, in the reference frequency generator 52 on the standby side, an output waveform having the same phase as that of the reference frequency generator 51 can be obtained.

  Specifically, the delay calculator 28b of the reference frequency generator 52 operating as the backup side analyzes the phase control information input from the reference frequency generator 51 on the active side via the control input terminal 92b, Get the path delay. Then, the delay parameters stored in advance in the setting storage unit 27b (specifically, the internal delay of the GPS receiver 21b, the transmission delay by the antenna cable connecting the GPS antenna 62 and the reference frequency generator 52, the reference frequency generation) The above-mentioned path delay is added to a delay time that comprehensively considers a transmission delay caused by a cable connecting the device 52 and the user-side device 70, and the obtained delay amount is set in the delay generator 35b.

  Consider a state in which the phase control information is not input from the reference frequency generator 51 on the active side to the reference frequency generator 52 operating as the backup side with the above configuration. In this case, the reference frequency generator 52 on the standby side assumes that the path delay is zero, and the delay calculator 28b sets only the delay amount corresponding to the delay parameter obtained from the setting storage unit 27b in the delay generator 35b. To do. As described above, in the reference frequency generator 52 operating as the backup side, the reference frequency generator 51 passes through the path including the first cable 101, the delay 1 of the user device 70, and the second cable 102. The 1 Hz signal input in this manner is supplied to the PLL circuit 22b as a reference timing signal. Accordingly, when the waveform phase is not adjusted as described above, the waveform phases of 10 MHz and 1 Hz output from the PLL circuit 22b in the reference frequency generator 52 on the standby side are compared with those on the working side in the above path. It will be delayed by the amount corresponding to the transmission delay.

  On the other hand, when the phase control information is input from the reference frequency generator 51, the delay calculator 28b controls the delay generator 35b so as to increase the delay amount corresponding to the cable delay. As a result, the phases of the 10 MHz and 1 Hz waveforms output from the standby-side reference frequency generator 52 are advanced so as to cancel the transmission delay of the path. Therefore, the phases of the output waveforms of 10 MHz and 1 Hz can be made uniform between the reference frequency generator 51 on the active side and the reference frequency generator 52 on the standby side. Thereby, when a failure occurs in the reference frequency generation device 51 and the reference frequency generation device 52 is switched to the active side, discontinuity (jump) of the waveform phase input to the user side device 70 can be prevented. Abnormal operation of the device 70 can be avoided.

  When the reference frequency generator 52 that has been operating as the backup side is switched to the active side as described above, the signal switch 26b of the reference frequency generator 52 uses the 1 Hz signal supplied from the reference frequency generator 51. Instead, switching is performed so that the 1PPS signal generated by the GPS receiver 21b of the own device is supplied to the PLL circuit 22b. However, in this embodiment, a loop filter having a long time constant is used as the loop filter 32b (FIG. 3) of the PLL circuit 22b. Therefore, at the moment when the operation is switched from the standby side to the working side, the output waveform of the PLL circuit 22b remains synchronized with the output waveform of the reference frequency generator 51 which was the working side until immediately before, and then gradually, The phase of the output waveform is matched with the timing based on the 1PPS signal of the GPS receiver 21b. Therefore, even in this sense, it can be said that a sudden phase fluctuation does not occur in the signal obtained by the user side device 70.

  Next, consider a case where a failure occurs in the first reference frequency generator 51 and the first reference frequency generator 51 recovers from the failure after the second reference frequency generator 52 is switched from the standby side to the active side. . In this case, the first reference frequency generation device 51 can be prepared as a backup side when the second reference frequency generation device 52 performs the operation performed by the second reference frequency generation device 52 until immediately before, and a failure occurs in the second reference frequency generation device 52. .

  The outline of this operation will be described. A 1 Hz signal output from the timing signal output terminal 81b of the reference frequency generator 52 on the working side is composed of the fifth cable 105, the delay 5 of the user side device 70, and the sixth cable 106. The signal is input to the timing signal input terminal 82a of the reference frequency generator 51 on the standby side via the path. Further, the return 1 Hz signal output from the return signal output terminal 83a of the reference frequency generator 51 on the standby side is sent to the active side via a path including the seventh cable 107, the delay 7 of the user side device, and the eighth cable 108. Are input to the return signal input terminal 84b of the reference frequency generator 52. The phase adjustment signal output circuit 23b in the reference frequency generator 52 on the working side measures the delay amount of the return 1 Hz signal with respect to the 1 Hz signal of the PLL circuit 22b of its own device, and sends phase control information based on this delay from the control output terminal 91b. Output. The standby-side reference frequency generator 51 adjusts the phase of the output signal of the PLL circuit 22a based on the phase control information input from the control input terminal 92a.

  As described above, the reference frequency generation system 60 of the present embodiment is configured by connecting the first reference frequency generation device 51 and the second reference frequency generation device 52. The first reference frequency generator 51 can operate as the working side. The second reference frequency generator 52 can operate as a spare side. When the second reference frequency generator 52 operates as a backup side, the PLL circuit 22b of the second reference frequency generator 52 is locked to the 1 Hz signal output from the PLL circuit 22a of the first reference frequency generator 51. When the second reference frequency generator 52 operates as a backup side, the phases of the reference frequency signals output from the second reference frequency generator 52 are the first reference frequency generator 51 and the second reference frequency generator 52. Is adjusted so as to correct a transmission delay caused by a connection line (a path including the first cable 101, the delay 1 of the user-side device 70, and the second cable 102).

  As a result, in consideration of the transmission delay of the connection line for supplying the signal of 1 Hz (the path formed by the first cable 101, the delay 1 of the user side device 70, and the second cable 102), the reference output on the backup side By adjusting the phase of the frequency signal, it is possible to output a reference frequency signal having the same phase on the active side and the backup side. Therefore, it is possible to prevent the output signal timing from abruptly changing when the output is switched between the active side and the standby side.

  The reference frequency generators 51 and 52 of the present embodiment are configured to be operable by switching between the active side and the standby side in the redundant system. Each reference frequency generator (for example, the first reference frequency generator 51) includes a PLL circuit 22a, a timing signal output terminal 81a, a timing signal input terminal 82a, a signal switch 26a, and a return signal output terminal 83a. A return signal input terminal 84a, a control output terminal 91a, a control input terminal 92a, and a delay calculator 28a. The PLL circuit 22a can output signals of 10 MHz and 1 Hz. The timing signal output terminal 81 a outputs a 1 Hz signal that is a signal output from the PLL circuit 22 a to the user-side device 70. The timing signal input terminal 82 a receives the 1 Hz signal of the counterpart reference frequency generator 52 as the counterpart 1 Hz signal via the user side device 70. The signal switch 26a locks the PLL circuit 22a to the 1PPS signal generated by the GPS receiver 21a when the own device operates as the active side, and the PLL circuit 22a when the own device operates as the backup side. Lock to the counterpart 1 Hz signal.

  Further, the return signal output terminal 83 a outputs the counterpart 1 Hz signal input from the timing signal input terminal 82 a to the user side device 70. When the own apparatus operates as the active side, the signal from the return signal output terminal 83b of the reference frequency generation device 52 on the counterpart side is input to the return signal input terminal 84a as a return 1 Hz signal via the user side device 70. . The control output terminal 91a generates a correction signal based on a signal delay amount that is a delay amount of the return 1 Hz signal with respect to the 1 Hz signal output from the PLL circuit 22a when the own device operates as the active side. Output to the device 52. The correction signal is input to the control input terminal 92a when the own apparatus operates as a spare side. The delay calculator 28a adjusts the phase of the output signal of the PLL circuit 22a of the own device based on the correction signal input from the control output terminal 91a when the own device operates as a backup side.

  As a result, the PLL circuit 22b of the reference frequency generator 52 on the standby side is locked to the 1 Hz signal generated by the PLL circuit 22a of the reference frequency generator 51 on the active side. Further, the phase of the output signal of the reference frequency generator 52 on the standby side can be adjusted in consideration of a transmission delay when a 1 Hz signal is transmitted from the active side to the backup side without requiring complicated adjustment work. it can. Therefore, the phase of the output waveform of the reference frequency generator 52 on the standby side can be exactly matched to the phase of the output waveform of the reference frequency generator 51 on the active side, and output generated when switching between the active side and the standby side Abrupt fluctuations (phase jumps) in the waveform phase can be suppressed.

  In the reference frequency generator 51 of the present embodiment, when the own apparatus operates as a backup side, the delay calculator 28a corresponds to the phase of the output signal of the PLL circuit 22a corresponding to half of the signal delay amount. The state is advanced by time.

  As a result, when the 1-Hz signal is exchanged between the reference frequency generation device 51 and the reference frequency generation device 52 using two paths having the same total delay amount, the active side can be connected with the active side by a simple process. The phase of the output signal can be matched on the spare side.

  The reference frequency generation system 60 of the present embodiment includes two reference frequency generation devices 51 and 52 having the above-described configuration.

  Accordingly, it is possible to provide the reference frequency generation system 60 that can suppress a sudden phase change (phase jump) that occurs when switching between the active side and the standby side.

  In the reference frequency generation system 60 of the present embodiment, the timing signal output terminal 81a of the reference frequency generation device 51 and the timing signal input terminal 82b of the reference frequency generation device 52 are connected to the first cable 101 and the user side device 70. Are connected by a first transmission path consisting of a delay 1 and a second cable 102. In addition, the return signal input terminal 84a of the reference frequency generator 51 and the return signal output terminal 83b of the reference frequency generator 52 are the second transmission including the third cable 103, the delay 3 of the user side device, and the fourth cable 104. Connected by route. And the transmission delay of the 1st transmission path and the transmission delay of the 2nd transmission path are in agreement.

  Accordingly, the phase of the output waveform of the standby-side reference frequency generator 52 can be matched with the phase of the output waveform of the active-side reference frequency generator 51 with a simple configuration.

  The preferred embodiment of the present invention has been described above, but the above configuration can be modified as follows, for example. In the following, in order to simplify the description, there is a case where the possibility of deformation is described by paying attention to only one of the two reference frequency generators 51 and 52, but the two reference frequency generators may be described. Of course, the modification can be applied to both 51 and 52.

  The timing signal output terminal 81a and the timing signal input terminal 82b (timing signal output terminal 81b and timing signal input terminal 82a) may be connected by a conductor other than a cable. For example, in a form in which two reference frequency generators are mounted on a single printed circuit board, a wiring pattern with a uniform delay amount is formed on the circuit board, and this circuit board is electrically connected to a connector included in the user side device 70. Can be changed as follows.

  The frequency of the voltage controlled oscillator 33a is not limited to 10 MHz, and another frequency may be used according to the signal frequency requested by the user.

  In the above embodiment, the signal input from the N frequency divider 34a to the delay generator 35a is branched in the PLL loop, and is output to the second output terminal 12a. However, instead of this, a signal that is input from the delay generator 35a to the phase comparator 31a in the PLL loop may be branched and output to the second output terminal 12a. Further, the delay generator 35a is disposed between the voltage controlled oscillator 33a and the N divider 34a in the PLL loop, and a signal input from the voltage controlled oscillator 33a to the delay generator is branched to the first output terminal 11a. It may be configured to output. The delay generator may be disposed between the signal switch 26a and the phase comparator 31a, or may be disposed between the phase comparator 31a and the loop filter 32a.

  Further, for example, a delay generator may be further arranged between the PLL loop and the second output terminal 12a so that the phase of the 10 MHz signal and the 1 Hz signal can be individually changed.

  Instead of the GPS receiver 21a, a radio wave receiver in another global positioning system may be adopted as a reference signal supply source. Moreover, it is not limited to using the radio receiver of such a global positioning system, As long as it can supply the calibrated accurate timing signal, a suitable apparatus can be employ | adopted. Furthermore, the reference signal supply source is not limited to being incorporated in the reference frequency generator 51, but can be changed to a configuration in which a signal from an external timing supply source is input and supplied to the PLL circuit 22a. Further, instead of the 1PPS signal, for example, a signal such as PP2S can be changed to a configuration in which the signal is input to the synchronization circuit as a reference signal.

  In the PLL circuit 22a, a PID (PI) controller can be used instead of the loop filter 32a. Further, a digitally controlled oscillator (DCO) can be used instead of the voltage controlled oscillator 33a (VCO). Furthermore, as long as the configuration can synchronize with the supplied reference signal, a synchronization circuit (for example, a DLL circuit) other than the PLL circuit 22a can be used.

  The low-pass filter 43a can be omitted if 1 Hz jitter due to external noise or environmental changes is not a problem. Further, the low-pass filter 43a can be changed to another filter according to the stability of the 1 Hz signal.

  The phase control information output from the control output terminal 91a may be an analog amount or digital data. In the case of digital data, for example, if it is configured to communicate with the outside by serial communication, phase control information may be included in a part thereof. For example, when transmitting the GPS reception information in an appropriate format such as the NMEA format, it may be possible to transmit the phase control information together.

  When the reference frequency generator 51 operates as the active side, the delay amount obtained by the delay amount measuring device 41a may be output as it is from the control output terminal 91a to the reference frequency generator 52 on the other side. In this case, a process of dividing by 2 and a filter process are performed on the side of the reference frequency generator 52 that has received it.

  For example, the reference frequency generator 51 may be configured to operate only on the active side. That is, even if the reference frequency generator 51 returns from the failure after the reference frequency generator 51 has failed and the reference frequency generator 52 is switched to the active side, the reference frequency generator 51 operates as a backup side. You may comprise so that it may not. In this case, the signal line indicated by the broken line in FIG. 1 (the signal line connecting the control output terminal 91b of the reference frequency generator 51 and the control input terminal 92a of the reference frequency generator 52) becomes unnecessary.

  Moreover, it can also be configured like a reference frequency generator 51x of a modification of FIG. The PLL circuit 22ax included in the reference frequency generator 51x is configured to include two phase comparators as input stages. Of these, the first phase comparator 37a compares the phase of the 1PPS signal obtained from the GPS receiver 21a with the output of the delay generator 35a. The second phase comparator 38a compares the phase of the 1 Hz signal obtained from the timing signal input terminal 82a with the output of the delay generator 35a. One of the outputs of the two phase comparators 37a and 38a is selected by the signal switch 26a and input to the loop filter 32a. In this configuration, the signal switch 26a locks the PLL circuit 22a to the 1PPS signal from the GPS receiver 21a when the reference frequency generator 51x operates as the active side, and the PLL circuit when the reference frequency generator 51x operates as the backup side. 22a is locked to the counterpart 1 Hz signal obtained from the working side. Even with the configuration of the above modification, the same effects as those of the above-described embodiment (FIG. 2) can be exhibited.

22a, 22b PLL circuit (synchronous circuit)
26a, 26b Signal switcher (switching unit)
28a, 28b Delay calculator (phase adjustment unit)
51, 52 Reference frequency generator 60 Reference frequency generator system 81a, 81b Timing signal output terminal (signal output unit)
82a, 82b Timing signal input terminal (signal input section)
83a, 83b Return signal output terminal (return signal output unit)
84a, 84b Return signal input terminal (return signal input section)
91a, 91b Control output terminal (correction signal output unit)
92a, 92b Control input terminal (correction signal input section)

Claims (7)

A first reference frequency generator operable as a working side;
A second reference frequency generator operable as a spare side;
In the reference frequency generation system connected to
When the second reference frequency generator operates as a standby side, the synchronization circuit of the second reference frequency generator locks to the synchronization circuit output signal output by the synchronization circuit of the first reference frequency generator, The phase of the reference frequency signal output from the second reference frequency generator is adjusted so as to correct a transmission delay caused by a connection line between the first reference frequency generator and the second reference frequency generator. Reference frequency generation system. In a reference frequency generator that can be used as a working side in a redundant system,
A synchronization circuit capable of outputting a signal of a predetermined frequency;
A signal output unit capable of outputting a synchronization circuit output signal, which is a signal output from the synchronization circuit, to the user side device;
A return signal input unit for inputting a return signal from the reference frequency generator on the other side via the user side device;
A correction signal output unit for outputting a correction signal based on a signal delay amount that is a delay amount of the return signal with respect to the synchronization circuit output signal to a reference frequency generator on the other side;
A reference frequency generator comprising: In a reference frequency generator that can be used as a backup side in a redundant system,
A synchronization circuit capable of outputting a signal of a predetermined frequency;
A signal input unit for inputting a signal output from the synchronization circuit of the reference frequency generation device on the working side as a partner-side synchronization circuit output signal via the user-side device;
Usually, the synchronization circuit of the own machine is locked to the output signal of the other party synchronization circuit, and when the own machine is switched to the active side, the switching unit that locks the synchronization circuit of the own machine to the reference signal of the own machine; ,
A return signal output unit for outputting the counterpart side synchronization circuit output signal input from the signal input unit to a user side device;
A correction signal input unit to which a correction signal output from the active reference frequency generator is input;
Based on the correction signal input from the correction signal input unit, a phase adjustment unit that adjusts the phase of the output signal of the synchronization circuit of the own device;
A reference frequency generator comprising: In a reference frequency generator operable at least as either a working side or a standby side in a redundant system,
A synchronization circuit capable of outputting a signal of a predetermined frequency;
A signal output unit that outputs a synchronization circuit output signal, which is a signal output from the synchronization circuit, to the user side device;
A signal input unit in which a synchronization circuit output signal of a counterpart reference frequency generator is input as a counterpart synchronization circuit output signal via the user device;
When the own machine operates as the active side, the synchronizing circuit is locked to the reference signal, and when the own machine operates as the backup side, the switching unit that locks the synchronizing circuit to the counterpart side synchronizing circuit output signal;
A return signal output unit for outputting the counterpart side synchronization circuit output signal input from the signal input unit to the user side device;
When the own device operates as the active side, a return signal input unit in which a signal from the return signal output unit of the reference frequency generator on the other side is input as a return signal through the user side device;
A correction signal output for outputting a correction signal based on a signal delay amount, which is a delay amount of the return signal with respect to the synchronous circuit output signal, to the reference frequency generator on the other side when the own device operates as the active side And
A correction signal input unit to which the correction signal is input when the own apparatus operates as a spare side;
A phase adjustment unit that adjusts the phase of the output signal of the synchronization circuit of the own device based on the correction signal input from the correction signal input unit when the own device operates as a standby side;
A reference frequency generator comprising: The reference frequency generator according to claim 4, wherein
When the own apparatus operates as a spare side, the phase adjustment unit sets the phase of the output signal of the synchronization circuit to a state advanced by a time corresponding to half of the signal delay amount. Generator.   A reference frequency generation system comprising at least two reference frequency generation apparatuses according to claim 4 or 5. The reference frequency generation system according to claim 6, wherein
The signal output unit of the reference frequency generator on one side and the signal input unit of the reference frequency generator on the other side are connected by a first transmission path including a delay of the user side device,
The return signal input unit of the reference frequency generator on one side and the return signal output unit of the reference frequency generator on the other side are connected by a second transmission path including a delay of the user side device,
A reference frequency generation system, wherein a transmission delay of the first transmission path and a transmission delay of the second transmission path coincide with each other.

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