JP2010204071A - Test circuit and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test circuit and a test method for executing a plurality of different tests as one continuous test in a burn-in test. <P>SOLUTION: The test circuit for performing the burn-in test of a semiconductor integrated circuit includes: a plurality of test control circuits for controlling the execution of the plurality of the different tests corresponding to a plurality of test modes; and a test order control circuit for controlling the plurality of the test control circuits so as to continuously execute the plurality of the different tests corresponding to the plurality of the test modes by switching the plurality of the test modes. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test circuit and a test method for performing a burn-in test of a semiconductor integrated circuit.

  In recent years, with the integration and speeding up of semiconductor integrated circuits, various tests have been performed to find initial defects of semiconductor integrated circuits and defects in manufacturing processes. As one of these tests, there is a burn-in test in which deterioration of a semiconductor integrated circuit is accelerated by temperature and voltage to remove initial defects in advance.

  When performing a burn-in test, a test pattern is usually generated by a logic BIST (Bist In Self-Test) controller which is a random number generation circuit for logic tests. This test pattern is input to a scan circuit using a scan flip-flop. The scan circuit operates in a shift mode when a test pattern is input, and operates a logic test target circuit connected to the scan circuit.

In such a conventional burn-in test, a burn-in test pattern capable of increasing the activation rate is set in a short time, and signals used for executing necessary burn-in test items are written in advance in individual semiconductor circuits. Etc. have been made.
JP 2002-257905 A JP 2001-344999 A

  The test pattern supplied from the logic BIST controller to the scan flip circuit is a test pattern for performing a logic test. Therefore, in the conventional burn-in test, a test different from the logic test such as a macro test for operating a memory or a function test for testing a logic function of a semiconductor integrated circuit cannot be performed as one continuous test.

  Therefore, an object of the present invention is to provide a test circuit and a test method capable of performing a plurality of different tests as one continuous test in the burn-in test.

  In order to solve the above problems, a test circuit for performing a burn-in test on a semiconductor integrated circuit, comprising a plurality of test control circuits for controlling execution of a plurality of different tests corresponding to a plurality of test modes, and the plurality of test modes. A test sequence control circuit that controls the plurality of test control circuits so as to continuously execute the plurality of different tests corresponding to the plurality of test modes by switching.

  In the burn-in test, a plurality of different tests can be performed as one continuous test.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  In the present embodiment, a plurality of test control circuits that control the execution of tests corresponding to a plurality of test modes, and the start of tests by each test control circuit are controlled so that tests in the plurality of test modes are continuously executed. The test sequence control circuit receives an enable signal for notifying the end of the test from the test control circuit, and causes the test control circuit corresponding to the next test mode to execute the test.

  The present embodiment is preferably applied to a dynamic burn-in test in which a dynamic signal is input to each input terminal to operate a semiconductor integrated circuit among the burn-in tests.

  FIG. 1 is a conceptual diagram of the test circuit of this embodiment.

  The test circuit 100 of the present embodiment includes a test order control circuit 200, test control circuits 300, 400, and 500, a logic test unit 600, a function test unit 700, and a macro test unit 800.

  The test order control circuit 200 controls the test control circuits 300, 400, and 500 to execute a logic test executed by the logic test unit 600, a function test executed by the function test unit 700, and a macro test unit 800. Perform macro tests continuously. The test order control circuit 200 of the present embodiment has a counter to be described later, and instructs the test control circuit that executes a test in a test mode corresponding to the counter value to start the test.

  The test control circuit 300 is a test control circuit corresponding to a logic test mode for performing a logic test, and controls the execution of the logic test. The test control circuit 400 is a test control circuit corresponding to a macro test mode for performing a macro test, and controls execution of the macro test. The test control circuit 500 is a test control circuit corresponding to a function test mode for performing a function test, and controls the execution of the function test.

  The logic test unit 600 receives a command from the test order control circuit 200 and starts a logic test. The function test unit 700 starts a function test in response to an instruction from the test order control circuit 200. The macro test unit 800 starts a macro test in response to an instruction from the test order control circuit 200.

  The outline of the operation of the test circuit 100 of this embodiment will be described below with reference to FIG. FIG. 2 is a flowchart for explaining the outline of the operation of the test circuit of this embodiment.

  First, a reset signal is input to the test circuit 100, and the test by the test circuit 100 is initialized (step S21).

  Next, the test circuit 100 determines whether or not the counter value of the test order control circuit 200 is a value corresponding to the logic test mode (step S22).

  In step S22, when the counter value is a value corresponding to the logic test mode, the test order control circuit 200 instructs the logic test unit 600 to start a logic test and outputs an operation clock signal to the test control circuit 300. To do. The logic test unit 600 performs a logic test until a counter value of a later-described counter included in the test control circuit 300 reaches a maximum value. When the counter value reaches the maximum value, the test control circuit 300 outputs a logic test end notification to the test order control circuit 200 (step S23).

  Upon receiving this notification, the test sequence control circuit 200 advances the counter value of the counter in the test sequence control circuit 200 by one (step S24). Then, the test circuit 100 returns to the process of step S22.

  When the determination of step S22 is performed for the second time, the counter value of the test order control circuit 200 is advanced by one in step S24, so the counter value of the test order control circuit 200 is not a value corresponding to the logic test mode. Therefore, the test circuit 100 determines whether or not the counter value of the test order control circuit 200 is a value corresponding to the macro test mode (step S25).

  In step S25, if the counter value corresponds to the macro test mode, the test order control circuit 200 instructs the macro test unit 800 to start a macro test and outputs an operation clock signal to the test control circuit 400. The macro test unit 800 performs a macro test until a counter value of a counter described later included in the test control circuit 400 reaches a maximum value. When the counter value reaches the maximum value, the test control circuit 400 outputs a macro test end notification to the test order control circuit 200 (step S26).

  Upon receiving this notification, the test sequence control circuit 200 advances the counter value of the counter in the test sequence control circuit 200 by one (step S24). Then, the test circuit 100 returns to the process of step S22.

  When the determination of step S22 is performed for the third time, the counter value of the test order control circuit 200 is advanced by one in steps S22 and S24, so the counter value of the test order control circuit 200 is a value corresponding to the logic test mode. is not. Further, the counter value of the test order control circuit 200 is not a value corresponding to the macro test mode.

  Accordingly, in the test circuit 100, the test order control circuit 200 instructs the function test unit 700 to start a function test, and outputs an operation clock signal to the test control circuit 500. The function test unit 700 performs a function test until a counter value of a counter, which will be described later, included in the test control circuit 500 reaches a maximum value. When the counter value reaches the maximum value, the test control circuit 500 outputs a function test end notification to the test order control circuit 200 (step S27).

  Upon receiving this notification, the test sequence control circuit 200 advances the counter value in the test sequence control circuit 200 by one. At this time, the counter value of the test order control circuit 200 may return to the minimum value.

  In the present embodiment, a plurality of test modes can be executed as a series of tests as described above.

  Details of the test circuit 100 of this embodiment will be described below.

  FIG. 3 is a diagram illustrating an example of a test circuit according to the present embodiment.

  The test circuit 100 of the present embodiment includes a test order control circuit 200, test control circuits 300, 400, and 500, a logic test unit 600, a function test unit 700, and a memory test unit 800.

  The test circuit 100 includes a TM terminal to which a test mode signal for switching between a system operation state and a test operation state is supplied, a CLK terminal to which a clock signal is supplied from the outside, and a RESET terminal to which a reset signal is supplied from the outside. , RESULT1 terminal for notifying the test execution result. A signal supplied from the TM terminal is supplied to the test order control circuit 200 and the clock control circuits 620, 630, and 750. The clock signal supplied from the CLK terminal is supplied to the test order control circuit 200. The reset signal supplied from the RESET terminal is supplied to the test order control circuit 200 and the test control circuits 300, 400, and 500.

  The logic test unit 600 includes a logic BIST controller 610, clock control circuits 620 and 630, an AND circuit 635, a scan circuit 640, and a test target circuit 650.

  When the logic test is started, the logic BIST controller 610 generates a test pattern and supplies the test pattern to the scan circuit 640. The scan circuit 640 repeats the shift operation based on the test pattern, and performs a scan test of the test target circuit 650. The clock control circuit 620 supplies an operation clock signal for operating the logic BIST controller 610 based on a logic test start instruction from the test order control circuit 200. When this operation clock signal is supplied, the logic BIST controller 610 generates a test pattern and supplies it to the scan circuit 640. The clock control circuit 630 supplies an operation clock signal for the scan circuit 640 to the scan circuit 640. The clock control circuit 630 also supplies an operation clock signal to the memories 810 and 820 to be subjected to the macro test. The AND circuit 635 outputs a signal that instructs the scan circuit 640 to start a logic test.

  The function test unit 700 includes a clock control circuit 750 and a function test target circuit 720. The clock control circuit 750 supplies an operation clock signal to the function test target circuit 720 based on a function test start instruction from the test order control circuit 200.

  The macro test unit 800 includes memories 810 and 820 which are macro test target circuits. An operation clock signal is supplied from the clock control circuit 630 to the memories 810 and 820 based on a macro test start instruction from the test order control circuit 200.

  The test sequence control circuit 200 has a TM terminal, a RESULT terminal, an LTEN terminal, an MTEN terminal, an FTEN terminal, a MODE terminal, an SMCNTL terminal, an LTCCLK terminal, an MTCCLK terminal, an FTCCLK terminal, an EN0 terminal, an EN1 terminal, and an EN2 terminal.

  A signal indicating the execution status of the test is output from the RESULT terminal. The signal output from the RESULT terminal is supplied to the outside of the test circuit 100 via the RESULT1 terminal. The LTEN terminal, the MTEN terminal, and the FTEN terminal supply control signals to the clock control circuits 750, 630, and 620.

  When the output of the LTEN terminal is at a high level (hereinafter, H level) and the output of the MTEN terminal and the LTEN terminal is at a low level (hereinafter, L level), the clock control circuit 620 performs a logic test on the logic BIST controller 610. A clock signal for instructing the start is supplied. An operation clock signal is supplied from the clock control circuit 630 to the scan circuit 640. Therefore, the H level signal output from the LTEN terminal is a signal for instructing the logic test unit 600 to start the logic test.

  When the output of the MTEN terminal is at the H level and the outputs of the LTEN terminal and the FTEN terminal are at the L level, an operation clock signal is supplied from the clock control circuit 630 to the memories 810 and 820. Therefore, the H level signal output from the MTEN terminal is a signal that instructs the macro test unit 800 to start the macro test.

  When the output of the FTEN terminal is at the H level and the outputs of the LTEN terminal and the MTEN terminal are at the L level, the operation clock signal is supplied from the clock control circuit 750 to the function test target circuit 720. Therefore, the H level signal output from the FTEN terminal is a signal that instructs the function test unit 700 to start the function test.

  The signal supplied from the SMCNTL terminal and the scan mode signal are supplied to the scan circuit 640 via the AND circuit 635.

  From the MODE terminal, a signal for selecting a memory to be subjected to the macro test is output to the test control circuit 400. Although the MODE terminal is shown as one terminal in FIG. 3, the MODE terminal may include a MODE0 terminal and a MODE1 terminal. The test control circuit 400 selects a memory to be a macro test target based on a signal from the MODE terminal.

  The LTCCLK terminal is connected to the CLK1 terminal of the test control circuit 300 and supplies an operation clock signal of the test control circuit 300. The MTCCLK terminal is connected to the CLK2 terminal of the test control circuit 400 and supplies an operation clock signal for the test control circuit 400. The FTCCLK terminal is connected to the CLK3 terminal of the test control circuit 500 and supplies an operation clock signal of the test control circuit 500.

  The EN0 terminal is connected to the NSFLAG1 terminal of the test control circuit 300, and an enable signal for notifying the end of the logic test is supplied from the test control circuit 300. The EN1 terminal is connected to the NSFLAG2 terminal of the test control circuit 400, and an enable signal for notifying the end of the macro test is supplied from the test control circuit 400. The EN2 terminal is connected to the NSFLAG3 terminal of the test control circuit 500, and an enable signal for notifying the end of the function test is supplied from the test control circuit 500.

  In the test sequence control circuit 200, when the enable signal is supplied to the EN0 terminal, the output of the MTEN terminal becomes the H level, the outputs of the LTEN terminal and the FTEN terminal become the L level, and the logic test ends. When the enable signal is supplied to the EN1 terminal, the output of the FTEN terminal becomes H level, the outputs of the LTEN terminal and the MTEN terminal become L level, and the macro test ends. When the enable signal is supplied to the EN2 terminal, the output of the LTEN terminal becomes H level, the outputs of the MTEN terminal and FTEN terminal become L level, and the function test is completed.

  A reset signal is input from the RESET terminal to the RESET1 terminal of the test control circuit 300, the RESET2 terminal of the test control circuit 400, and the RESET3 terminal of the test control circuit 500.

  FIG. 4 is a diagram showing a configuration for continuously operating a plurality of test modes in the test circuit of the present embodiment. In the description of FIG. 4, only differences from the test circuit 100 of FIG. 3 will be described.

  The test circuit 100A has an LBCLK terminal, an SM terminal, a CLOCK1 terminal, and a CLOCK2 terminal which are external terminals. An operation clock signal of the logic BIST controller 610 is supplied from the LBCLK terminal. The SM terminal is supplied to one input of the AND circuit 635. The output of the AND circuit 635 is connected to the scan circuit 640, and a control signal for operating the scan circuit 640 is supplied. The CLOCK 1 terminal is connected to the clock control circuit 630 and supplies an operation clock signal for the scan circuit 640 and an operation clock signal for the memories 810 and 820. The CLOCK2 terminal is connected to the clock control circuit 750, and an operation clock signal for the function test target circuit 720 is supplied thereto.

  In the test circuit 100A, the clock control circuit 620 includes an OR circuit 62 and an AND circuit 63. The output signal of the LTEN terminal is supplied to one input of the AND circuit 63, and the signal of the TM terminal is supplied to the other input of the AND circuit 63. A signal obtained by inverting the output of the AND circuit 63 is supplied to one input of the OR circuit 62, and a clock signal input from the LBCLK terminal is supplied to the other input of the OR circuit 62. The output of the OR circuit 62 is supplied to the logic BIST controller 610.

  The clock control circuit 630 includes OR circuits 63 and 64. The OR circuit 63 receives a signal output from the LTEN terminal, a signal output from the MTEN terminal, and a signal obtained by inverting the signal of the TM terminal. The output of the OR circuit 63 is inverted and supplied to one input of the OR circuit 64. The other input of the OR circuit 64 is supplied with a clock signal from the CLOCK1 terminal. The output of the OR circuit 64 is supplied as an operation clock signal to the scan circuit 640 and the memories 810 and 820.

  The clock control circuit 750 includes OR circuits 71 and 72. The FTEN signal is supplied to one input of the OR circuit 72, and a signal obtained by inverting the signal at the TM terminal is input to the other input. A clock signal is supplied from the CLOCK2 terminal to one input of the OR circuit 71, and a signal obtained by inverting the output of the OR circuit 72 is supplied to the other input. The output of the OR circuit 71 is supplied to the function test target circuit 720 as an operation clock signal.

  The test control circuit 400A of this embodiment has an M1, M2, MR1, and MR2 terminals in addition to the CLK2, RESET2, NSFLAG2, and MODET terminals. A signal for selecting the memory 810 as a test target is output from the M1 terminal. A signal instructing the start of the macro test for the memory 810 is output from the MR1 terminal. A signal for selecting the memory 820 as a test target is output from the M2 terminal. A signal instructing the start of the macro test for the memory 820 is output from the MR2 terminal. The MODET terminal may have a MODET0 terminal and a MODET1 terminal.

  Next, the test sequence control circuit 200 will be described with reference to FIG. FIG. 5 is a diagram for explaining the test order control circuit of the present embodiment.

  The test order control circuit 200 includes a test operation determination circuit 210, a counter 230, a NOR circuit 240, AND circuits 241, 242, 243, 244, and OR circuits 245, 246, 247, 248, 252, 253, 254.

  In the test order control circuit 200, the test mode associated with the counter value of the counter 230 is set in the test operation determination circuit 210, and the test mode is switched when the counter value of the counter 230 changes. In this embodiment, for example, the logic test mode may be set when the counter value of the counter 230 is 0, the macro test mode when the counter value is 1 or 2, and the function test mode when the counter value is 3. Although the counter 230 of this embodiment is a 2-bit counter, it is not limited to this. The counter of the test order control circuit 200 may be a counter whose maximum value can count the number of modes and the number of memories.

  In the test order control circuit 200, when the test mode is switched, the AND circuits 241 to 244 and the OR circuits 245 to 248 stop the output of the clock signal used in the test other than the test mode being executed. Therefore, in the present embodiment, when one test mode is executed, unnecessary clock signals that are not used are not generated, and it is possible to contribute to reduction of current consumption.

  The test operation determination circuit 210 has an EN0 terminal, an EN1 terminal, an EN2 terminal, a CLK4 terminal, a CL terminal, a MODEP0 terminal, a MODEP1 terminal, and a RESULT2 terminal.

  The ENP0 terminal is connected to the EN0 terminal of the test sequence control circuit 200, and an enable signal output from the NSFLAG1 terminal of the test control circuit 300 is input. The ENP1 terminal is connected to the EN1 terminal of the test order control circuit 200, and an enable signal output from the NSFLAG2 terminal of the test control circuit 400A is input. The ENP2 terminal is connected to the EN2 terminal of the test order control circuit 200, and an enable signal output from the NSFLAG3 terminal of the test control circuit 500 is input.

  An externally input clock signal is supplied to the CLK4 terminal. A reset signal input from the outside is supplied to the CL terminal. The MODEP0 terminal and the MODEP1 terminal output H level or L level signals for controlling the test mode to be executed. The RESULT2 terminal outputs a signal indicating the test execution result.

  The output of the NOR circuit 240 is supplied to the EN4 terminal of the counter 230. The output of the EN0 terminal, the output of the EN1 terminal, and the output of the EN2 terminal are input to the NOR circuit 240. The counter value of the counter 230 varies depending on signals output from the EN0 terminal, the EN1 terminal, and the EN2 terminal.

  A clock signal input from the outside is supplied to the CLK5 terminal of the counter 230, and a RESET signal supplied from the outside is supplied to the CL1 terminal.

  The output of the Q0 terminal of the counter 230 is supplied to one input of the AND circuits 243 and 244. The output of the Q0 terminal of the counter 230 is inverted and supplied to one input of the AND circuits 241 and 242. The Q0 terminal is connected to the MODE0 terminal, and a signal output from the Q0 terminal is supplied to the MODET0 terminal of the test control circuit 400A connected to the MODE0 terminal.

  The output of the Q1 terminal of the counter 230 is supplied to one input of the AND circuits 242 and 244. The output of the Q1 terminal of the counter 230 is inverted and supplied to one input of the AND circuits 241 and 243. The Q1 terminal is connected to the MODE1 terminal, and a signal output from the Q1 terminal is supplied to the MODET1 terminal of the test control circuit 400A connected to the MODE1 terminal.

  The output of the AND circuit 241 is output from the SMCNTL terminal and the LTEN terminal. The output of the AND circuit 241 is inverted and supplied to one input of the OR circuit 248. The output of the AND circuit 242 and the output of the AND circuit 243 are input to the OR circuit 245. The output of the OR circuit 245 is output from the MTEN terminal. The output of the OR circuit 245 is inverted and supplied to one input of the OR circuit 246.

  The output of the AND circuit 244 is output from the FTEN terminal. The output of the AND circuit 244 is inverted and supplied to one input of the OR circuit 247.

  The output of the OR circuit 246 is supplied to one input of the OR circuit 252. The output of the OR circuit 247 is supplied to one input of the OR circuit 253. The output of the OR circuit 248 is supplied to one input of the OR circuit 254.

  An external test mode signal is inverted and supplied to one input of the OR circuits 252 253 254.

  The output of the OR circuit 252 is output from the MTCCLK terminal and supplied as an operation clock signal to the test control circuit 400A. The output of the OR circuit 253 is output from the FTCCLK terminal and supplied to the test control circuit 500 as an operation clock signal. The output of the OR circuit 254 is output from the LTCCLK terminal and supplied to the test control circuit 300 as an operation clock signal.

  FIG. 6 is a diagram for explaining the relationship among the test mode, the input signal, and the output signal.

  In the test order control circuit 200 of the present embodiment, the relationship between the test mode, the input signal, and the output signal is set as shown in the table 60 shown in FIG.

  The test sequence control circuit 200 enters the initialization mode when an L level signal is input to the RESET terminal, and shifts to the test mode when an H level signal is input to the RESET terminal.

  First, the initialization mode will be described. In the test sequence control circuit 200, when an H level signal is input to the TM terminal and an L level signal is input to the RESET terminal to enter the initialization mode, the signal input to the CLK terminal is turned off, and the EN0 terminal, A signal input to the EN1 terminal and the EN2 terminal is an arbitrary level indicating 0 or 1 (indicated as X in FIG. 4). Further, the outputs of the SMCNTL terminal and the LTEN terminal become H level, and the outputs of the MTEN terminal and the FTEN terminal become L level. Further, the clock signals output from the LTCCLK terminal, the MTCCLK terminal, and the FTCCLK terminal are turned off. The outputs of the two MODE terminals are L level.

  Next, the test mode will be described.

  In the test order control circuit 200 of the present embodiment, a corresponding test mode is set based on a combination of signals input to the RESET terminal, the CLK terminal, the EN0 terminal, the EN1 terminal, and the EN2 terminal that are input terminals.

  First, the logic test mode will be described. In the test sequence control circuit 200, an H level signal is input to the TM terminal, an H level signal is input to the RESET terminal, a clock signal input to the CLK terminal is turned on, and an H level enable signal is input to the EN0 terminal. When input, it shifts to logic test mode. When the logic test mode is entered, the outputs of the SMCNTL terminal and the LTEN terminal become H level, and the outputs of the MTEN terminal and the FTEN terminal become L level. The clock signal output from the LTCCLK terminal is turned on, and the clock signals output from the MTCCLK terminal and the FTCCLK terminal are turned off. The outputs of the two MODE terminals are L level.

  Next, the macro test mode will be described. In the test sequence control circuit 200, an H level signal is input to the TM terminal, an H level signal is input to the RESET terminal, a clock signal input to the CLK terminal is turned on, and an H level enable signal is input to the EN1 terminal. When entered, the macro test mode is entered. When the macro test mode is entered, the output of the MTEN terminal becomes H level, the output of the SMCNTL terminal becomes X, and the outputs of the LTEN terminal and the FTEN terminal become L level. Further, the clock signal output from the MTCCLK terminal is turned on, and the clock signals output from the LTCCLK terminal and the FTCCLK terminal are turned off. The signal output from the MODE terminal is L level or H level.

  In the test sequence control circuit 200 of the present embodiment, the MODE 0 terminal and the MODE 1 terminal are provided as the MODE terminals, so that an H level signal may be output from either the MODE 0 terminal or the MODE 1 terminal. An L level signal may be output.

  Next, the function test mode will be described. In the test sequence control circuit 200, an H level signal is input to the TM terminal, an H level signal is input to the RESET terminal, a clock signal input to the CLK terminal is turned on, and an H level enable signal is input to the EN2 terminal. When entered, the function test mode is entered. When the function test test mode is entered, the output from the FTEN terminal becomes H level, the output from the SMCNTL terminal becomes X, and the outputs from the LTEN terminal and the MTEN terminal become L level. Further, the clock signal output from the FTCCLK terminal is turned on, and the clock signals output from the LTCCLK terminal and the MTCCLK terminal are turned off. Signals output from the two MODE terminals are L level.

  Next, the test operation determination circuit 210 included in the test order control circuit 200 of this embodiment will be described with reference to FIG. FIG. 7 is a diagram for explaining the test operation determination circuit of the present embodiment.

  The test operation determination circuit 210 of this embodiment outputs a signal indicating a test execution result indicating that the three test modes of the logic test mode, the macro test mode, and the function test mode have been executed at least once from the RESULT2 terminal.

  The test operation determination circuit 210 includes flip-flops (hereinafter referred to as FFs) 211, 212, 213, 214, AND circuits 215, 216, 217, 218, 219, and OR circuits 220, 221, 222, 223.

  A clock signal is externally supplied to the CLK4 terminal of the test operation determination circuit 210, and a reset signal is externally supplied to the CL terminal. A clock signal supplied from the CLK4 terminal and a reset signal supplied from the CL terminal are input to the FFs 211 to 214 of the test operation determination circuit 210.

  The output of the MODEP0 terminal is supplied to one input of the AND circuit 215, and the output of the MODEP1 terminal is inverted and supplied to the other input. The output of the AND circuit 215 is supplied to one input of the AND circuit 217. The output of the MODEP0 terminal is inverted and supplied to one input of the AND circuit 216, and the output of the MODEP1 terminal is supplied to the other input. The output of the AND circuit 216 is supplied to one input of the AND circuit 218.

  The other input of the AND circuits 217 and 218 is supplied with an input from the ENP1 terminal. The output of the AND circuit 217 is supplied to one input of the OR circuit 221. The output of the AND circuit 218 is supplied to one input of the OR circuit 222.

  An input from the ENP0 terminal is supplied to one input of the OR circuit 220. The output of the FF 211 is supplied to the other input of the OR circuit 220. The output of the OR circuit 220 is supplied to the FF 211.

  The output of the FF 212 is supplied to the other input of the OR circuit 221. The output of the OR circuit 221 is supplied to the FF 212. The output of the FF 213 is supplied to the other input of the OR circuit 222. The output of the OR circuit 222 is supplied to the FF 213.

  One input of the OR circuit 223 is supplied with an input from the ENP2 terminal. The output of the FF 214 is supplied to the other input of the OR circuit 223. The output of the OR circuit 223 is supplied to the FF 214. Outputs of the FFs 211, 212, 213, and 214 are supplied to the AND circuit 219. The output of the AND circuit 219 is output from the RESULT2 terminal.

  The FF 211 changes its output from 0 to 1 when an enable signal for notifying the end of the logic test is input from the ENP0 terminal. The FF 211 holds this output. When the enable signal for notifying the end of the macro test is input from the ENP1 terminal, the output of either FF212 or FF213 corresponding to the value of the signals of MODEP0 and MODEP1 changes from 0 to 1. The FF 212 and FF 213 hold this output. The FF 214 changes its output from 0 to 1 when an enable signal for notifying the end of the function test is input from the ENP2. The FF 214 holds this output.

  When all the outputs of the FFs 211 to 214 change from 0 to 1, the output of the AND circuit 219 becomes 1 (H level), and an H level signal is output from the RESULT2 terminal. The RESULT2 terminal is connected to the RESULT1 terminal of the test circuit 100A via the RESULT terminal of the test order control circuit 200, and the output of the RESULT2 terminal is supplied from the RESULT1 terminal to the outside of the test circuit 100A. Therefore, the test circuit 100A according to the present embodiment monitors the output of the RESULT1 terminal and notifies the test execution result that the four test targets have been tested at least once when the output of the RESULT1 terminal becomes H level. Can do.

  Next, the test control circuit 300 of this embodiment will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of the test control circuit of the present embodiment.

  The test control circuit 300 includes a counter 310, a register 320, an XOR circuit 331, 332, 333, 334, 335, an OR circuit 340, and a NOT circuit 350. The counter 310 of this embodiment is a 5-bit counter. The CLK terminal of the counter 310 is connected to the CLK1 terminal, and the clock signal supplied from the LTCCLK terminal is supplied. The CL terminal of the counter 310 is connected to the RESET1 terminal, and the reset signal supplied from the RESET1 terminal is inverted and input. The output of the OR circuit 340 is inverted and supplied to the RESET terminal of the counter 310.

  The output of the Q0 terminal of the counter 310 is supplied to one input of the XOR circuit 331. The output of the Q1 terminal of the counter 310 is supplied to one input of the XOR circuit 332. The output of the Q2 terminal of the counter 310 is supplied to one input of the XOR circuit 333. The output of the Q3 terminal of the counter 310 is supplied to one input of the XOR circuit 334. The output of the Q4 terminal of the counter 310 is supplied to one input of the XOR circuit 335.

  In the register 320, the maximum value of the counter is set. In the present embodiment, for example, the value set in the register 320 is 25. A unique bit indicating the maximum value 25 is output from the register 320 and supplied to the other input of the XOR circuits 331, 332, 333, 334, and 335.

  The outputs of the XOR circuits 331, 332, 333, 334, 335 are supplied to the OR circuit 340. The output of the OR circuit 340 is supplied to the input of the NOT circuit 350. The output of the NOT circuit 350 is connected to the NSFLAG1 terminal and is output as an enable signal.

  In the test control circuit 300 of this embodiment, when the output of the counter 310 matches the maximum value 25 set in the register 320, the output of the NOT circuit 350 becomes H level. This H level output is supplied from the NSFLAG1 terminal to the test sequence control circuit 200 as an enable signal.

  Although the test control circuit 300 has been described with reference to FIG. 8, the test control circuit 500 corresponding to the function test mode may have the same configuration. The maximum value set in the register 320 is 25 in FIG. 8, but the maximum value set in the test control circuit 500 may be 23, for example. The register 320 may be a fixed signal using a clip or the like instead of the register.

  Next, the test control circuit 400A of this embodiment will be described with reference to FIG. FIG. 9 is a diagram illustrating another example of the test control circuit of the present embodiment.

  The test control circuit 400A includes a counter 410 and registers 420 and 430. The test control circuit 400A includes AND circuits 421, 422, 423, 424, selectors 431, 432, 433, 434, 435, XOR circuits 441, 442, 443, 444, 445, OR circuit 450, NOR circuit 460, NOT circuit. 470.

  In the example of FIG. 9, the counter 410 is a 5-bit counter. The CLK terminal of the counter 410 is connected to the CLK2 terminal, and a clock signal supplied from the MTCCLK terminal is supplied. The CL terminal of the counter 410 is connected to the RESET2 terminal, and a reset signal supplied from the RESET2 terminal is input. The output of the OR circuit 450 is supplied to the RESET terminal of the counter 410.

  The output of the Q0 terminal of the counter 410 is supplied to one input of the XOR circuit 441. The output of the Q1 terminal of the counter 410 is supplied to one input of the XOR circuit 442. The output of the Q2 terminal of the counter 410 is supplied to one input of the XOR circuit 443. The output of the Q3 terminal of the counter 410 is supplied to one input of the XOR circuit 444. The output of the Q4 terminal of the counter 410 is supplied to one input of the XOR circuit 445.

  Further, the output of the Q0 terminal, the output of the Q1 terminal, the output of the Q2 terminal, the output of the Q3 terminal, and the output of the Q4 terminal of the counter 410 are supplied to the NOR circuit 460. The output of the NOR circuit 460 is supplied to one input of the AND circuit 423 and the AND circuit 424.

  In the register 420 and the register 430, the maximum value of the counter corresponding to the macro test for each selected memory is set. In the present embodiment, for example, the value set in the register 420 is 11 and the value set in the register 430 is 27. A unique bit indicating the value 11 is output from the register 420 and supplied to the first input of the selectors 431, 432, 433, 434, and 435. A unique bit indicating a value 27 is output from the register 430 and supplied to the second input of the selectors 431, 432, 433, 434, and 435.

  The selectors 431, 432, 433, 434, and 435 receive a signal supplied from the MODET0 terminal as a select signal. The selectors 431, 432, 433, 434, and 435 output a signal (a signal supplied from the register 420) supplied to the first input when the select signal is at the H level. When the select signal is at the L level, a signal supplied to the second input (a signal supplied from the register 430) is output. The outputs of the selectors 431, 432, 433, 434, 435 are supplied to the other inputs of the XOR circuits 441, 442, 443, 444, 445.

  The outputs of the XOR circuits 441, 442, 443, 444, 445 are supplied to the input of the OR circuit 450. The output of the OR circuit 450 is supplied to the input of the NOT circuit 470. The output of the NOT circuit 470 is connected to the NSFLAG2 terminal and is supplied to the test order control circuit 200 as an enable signal.

  A signal inputted from the MODET0 terminal is inverted and supplied to one input of the AND circuit 421, and a signal inputted from the MODET1 terminal is supplied to the other input of the AND circuit 421. The output of the AND circuit 421 is supplied to the other input of the AND circuit 423. The output of the AND circuit 421 is supplied from the M2 terminal to the memory 820. The output of the terminal M2 is a signal indicating that the memory 820 is a macro test target.

  A signal input from the MODET 0 terminal is supplied to one input of the AND circuit 422, and a signal input from the MODET 1 terminal is inverted and supplied to the other input of the AND circuit 422. The output of the AND circuit 422 is supplied to the other input of the AND circuit 424. The output of the AND circuit 422 is supplied to the memory 810 from the M1 terminal. The output of the terminal M1 is a signal indicating that the memory 810 is a macro test target.

  The output of the AND circuit 423 is supplied to the memory 820 from the MR2 terminal. The signal output from the MR2 terminal is a signal instructing the start of the macro test of the memory 820. The output of the AND circuit 424 is supplied to the memory 810 from the MR1 terminal. The signal output from the MR1 terminal is a signal instructing the start of the macro test of the memory 810.

  In the test control circuit 400A, for example, when an H level signal is input to the MODET0 terminal and an L level signal is input to the MODET1 terminal, a signal for selecting the memory 810 as a macro test target is output from the M1 terminal. The selectors 431 to 435 output the value set in the register 420 as the first input because the select signal is at the H level. Therefore, the test control circuit 400A performs a macro test on the memory 810 until the value of the counter 410 becomes equal to 11.

  When the count value of the counter 410 becomes 11, an enable signal for notifying the end of the macro test of the memory 810 is output from the NSFLAG2 terminal to the test order control circuit 200. The test sequence control circuit 200 advances the value of the counter 230 by one here. In this embodiment, at this time, an L level signal is input to the MODET0 terminal of the test control circuit 400A, and an H level signal is input to the MODET1 terminal.

  At this time, a signal for selecting the memory 820 as a macro test target is output from the M2 terminal. The selectors 431 to 435 output the value set in the register 430 as the second input because the select signal is at the L level. Therefore, the test control circuit 400A performs a macro test on the memory 820 until the value of the counter 410 becomes equal to 27.

  When the count value of the counter 410 becomes 11, an enable signal for notifying the end of the macro test of the memory 810 is output from the NSFLAG2 terminal to the test order control circuit 200.

  In this embodiment, the number of memories to be subjected to the macro test is two, but the number of memories is not limited to this. The number of registers included in the test control circuit 400A is preferably the same as the number of memory groups to be subjected to the macro test. At this time, memories belonging to one group can be tested simultaneously. Further, the registers 420 and 430 may be fixed signals using clips or the like instead of registers.

  Next, the operation of the test circuit 100A of this embodiment will be described with reference to FIG. FIG. 10 is a timing chart for explaining the operation of the test circuit of this embodiment.

  When the reset signal input to the RESET terminal of the test circuit 100A changes from the L level to the H level at the timing T1 of the test operation state where the H level signal is input to the TM terminal as the test mode signal, the test circuit 100A is initialized Transition from mode to test mode. When the test mode is shifted to timing T1, the clock signal input to the CLK terminal is turned on. Clock signals input from the LBCLK terminal, CLOCK1 terminal, and CLOCK2 terminal are also turned on. The signal input from the SM terminal becomes L level.

  At timing T1, the test sequence control circuit 200 starts counting from the counter value 0 by the counter 230, and outputs an H level signal from the SMCNTL terminal and the LTEN terminal. In the present embodiment, since the test mode corresponding to the count value 0 is the logic test mode, the test order control circuit 200 outputs an operation clock signal from the LTCCLK terminal to the CLK1 terminal of the test control circuit 300. At this time, the operation clock signal output from the MTCCLK terminal and the FTCCLK terminal is turned off.

  The test control circuit 300 starts counting by the counter 310 when the operation clock signal is input from the CLK1 terminal. When the count value of the counter 310 of the test control circuit 300 reaches the maximum value, the test control circuit 300 outputs an enable signal from the NSFLAG1 terminal to the EN0 terminal of the test order control circuit 200. Then, the count value of the counter 310 is returned to zero.

  When the enable signal is input to the EN0 terminal, the test sequence control circuit 200 advances the value of the counter 230 from 0 to 1 at timing T2. The test mode corresponding to the counter value 1 of the counter 230 is a macro test mode.

  At timing T2, the outputs of the SMCNTL terminal, LTEN terminal, and FTEN terminal of the sequence control circuit 200 become L level, the output of the MTEN terminal becomes H level, and the test mode shifts from the logic test mode to the macro test mode. The test sequence control circuit 200 outputs an operation clock signal from the MTCCLK terminal to the CLK2 terminal of the test control circuit 400A. At this time, the clock signals output from the LTCCLK terminal and the FTCCLK terminal are turned off.

  In this embodiment, the memory selected as the macro test target in the macro test corresponding to the counter value 1 of the counter 230 is the memory 810. Therefore, an H level signal indicating that the memory 810 has been selected as a test target is output from the M1 terminal of the test control circuit 400A. An H level signal instructing the start of the macro test of the memory 810 is output from the MR1 terminal. Signals output from the M1 terminal and MR1 terminal are supplied to the memory 810.

  In the test control circuit 400A, when the operation clock signal is input at the timing T2, counting by the counter 410 is started. Then, when the count value of the counter 410 becomes equal to the value set in the register 420, the test control circuit 400A outputs an enable signal for notifying the end of the macro test of the memory 810 from the NSFLAG2 terminal to the EN1 terminal of the test order control circuit 200. . Then, the count value of the counter 410 is returned to zero.

  At timing T3, the test order control circuit 200 advances the counter value from 1 to 2. The test mode corresponding to the counter value 2 is a macro test mode for the memory 820. Therefore, the output of the SMCNTL terminal, the LTEN terminal, the MTEN terminal, and the FTEN terminal is the same as the signal output at the timing T2.

  At timing T3, an H level signal indicating that the memory 820 has been selected as a test target is output from the M2 terminal of the test control circuit 400A. Further, an H level signal instructing the start of the macro test of the memory 820 is output from the MR2 terminal. Signals output from the M2 terminal and MR2 terminal are supplied to the memory 820.

  When the count value of the counter 410 becomes equal to the value set in the register 430, the test control circuit 400A outputs an enable signal for notifying the end of the macro test of the memory 820 from the NSFLAG2 terminal to the EN1 terminal of the test order control circuit 200. Then, the count value of the counter 410 is returned to zero.

  When the enable signal is input to the EN1 terminal, the test order control circuit 200 advances the value of the counter 230 from 2 to 3 at timing T4. The test mode corresponding to the counter value 3 of the counter 230 is a function test mode.

  At timing T4, the outputs of the SMCNTL terminal, the LTEN terminal, and the MTEN terminal of the test order control circuit 200 become L level, the output of the FTEN terminal becomes H level, and the test mode shifts from the macro test mode to the function test mode. The test sequence control circuit 200 outputs an operation clock signal from the FTCCLK terminal to the CLK3 terminal of the test control circuit 500. At this time, the clock signals output from the LTCCLK terminal and the MTCCLK terminal are turned off.

  When the operation clock signal is input from the CLK3 terminal, the test control circuit 500 starts counting by the counter. When the count value of the counter of the test control circuit 500 reaches the maximum value, the test control circuit 500 outputs an enable signal from the NSFLAG3 terminal to the EN2 terminal of the test order control circuit 200. Then, the counter value of the counter is returned to zero.

  When the enable signal is input to the EN2 terminal, the test sequence control circuit 200 returns the counter value of the counter 230 to the initial value 0 at the timing T5, and can perform tests in each test mode again in order from the logic test mode. .

  As described above, in the present embodiment, tests in the test modes corresponding to the count value of the counter 230 included in the test order control circuit 200 are sequentially executed, and the test control circuits 300, 400A, The test sequence control circuit 200 is notified from 500. In the present embodiment, with such a configuration, a plurality of different tests can be performed as one continuous test in the burn-in test.

In the embodiment of the present invention, the following configurations described below are conceivable.
(Appendix 1)
A test circuit for performing a burn-in test of a semiconductor integrated circuit,
A plurality of test control circuits for controlling the execution of a plurality of different tests corresponding to a plurality of test modes;
A test circuit having a test order control circuit that controls the plurality of test control circuits so as to continuously execute the plurality of different tests corresponding to the plurality of test modes by switching the plurality of test modes.
(Appendix 2)
The test sequence control circuit includes:
The test circuit according to appendix 1, wherein when a test end notification is received from any one of the plurality of test control circuits, the test control circuit corresponding to a test mode of a test to be executed next is operated.
(Appendix 3)
The test sequence control circuit includes:
The test circuit according to appendix 2, wherein the operation of a test control circuit other than the test control circuit corresponding to the test mode of the test being executed is stopped among the plurality of test control circuits.
(Appendix 4)
A plurality of test target circuits to be subjected to the plurality of different tests;
The test sequence control circuit includes:
The supplementary note 1 to 3, wherein when a test completion notification is received from any one of the plurality of test control circuits, the test target circuit to be tested next is operated. Test circuit as described in.
(Appendix 5)
A plurality of clock control circuits for supplying operation clock signals to the plurality of test target circuits;
The test sequence control circuit includes:
When a test end notification is received from any one of the plurality of test control circuits, an operation clock signal is sent to the test target circuit to be tested next in the plurality of clock control circuits. The test circuit according to appendix 4, wherein
(Appendix 6)
The clock control circuit includes:
The test circuit according to appendix 5, wherein an operation clock signal is not supplied to a test target circuit other than the test target circuit to be tested among the plurality of test target circuits.
(Appendix 7)
The test control circuit includes:
7. The test circuit according to any one of appendices 1 to 6, wherein when an execution of a test in a test mode corresponding to the test control circuit is completed, an enable signal for notifying the completion is output to the test order control circuit.
(Appendix 8)
The test control circuit has a counter,
8. The test circuit according to any one of appendices 1 to 7, wherein the enable signal is output to the test order control circuit when a value of the counter reaches a maximum value.
(Appendix 9)
The test control circuit includes:
8. The test circuit according to any one of appendices 4 to 7, wherein a test target circuit to be tested next is selected from a plurality of test target circuits.
(Appendix 10)
The test sequence control circuit includes:
A counter associated with a counter value and the plurality of test modes;
The test circuit according to any one of appendices 1 to 9, wherein the test signal is switched by receiving the enable signal from the test control circuit and incrementing a count value of the counter.
(Appendix 11)
The test circuit according to any one of appendices 1 to 10, wherein a signal indicating whether or not the plurality of different tests corresponding to the plurality of test modes has been executed is output.
(Appendix 12)
The test circuit according to any one of appendices 1 to 11, wherein the plurality of test modes include a logic test mode, a macro test mode, and a function test mode.
(Appendix 13)
A test method using a test circuit for performing a burn-in test of a semiconductor integrated circuit,
The test circuit includes:
Multiple test control procedures that control the execution of tests corresponding to multiple test modes;
A test method for executing a test sequence control procedure for controlling the plurality of test control circuits so as to continuously execute the tests corresponding to the plurality of test modes.

  The embodiments of the present invention are not limited to the specifically disclosed examples, and various modifications and changes can be made without departing from the scope of the claims.

It is a conceptual diagram of the test circuit of this embodiment. 4 is a flowchart for explaining an outline of the operation of the test circuit of the present embodiment. It is a figure which shows an example of the test circuit which concerns on this embodiment. It is a figure which shows the structure for operating a several test mode continuously in the test circuit of this embodiment. It is a figure for demonstrating the test order control circuit of this embodiment. It is a figure for demonstrating the relationship between a test mode, an input signal, and an output signal. It is a figure for demonstrating the test operation determination circuit of this embodiment. It is a figure which shows an example of the test control circuit of this embodiment. It is a figure which shows another example of the test control circuit of this embodiment. 4 is a timing chart for explaining the operation of the test circuit of the present embodiment.

100, 100A Test circuit 200 Test sequence control circuit 210 Test operation determination circuit 230, 310, 410 Counter 300, 400, 400A, 500 Test control circuit 320, 420, 430 Register 600 Logic test unit 610 Logic BIST controller 620, 630, 710 Clock control circuit 640 Scan circuit 650 Test target circuit 700 Function test unit 720 Function test target circuit 800 Macro test unit 810, 820 Memory

Claims (6)

A test circuit for performing a burn-in test of a semiconductor integrated circuit,
A plurality of test control circuits for controlling the execution of a plurality of different tests corresponding to a plurality of test modes;
A test circuit having a test order control circuit that controls the plurality of test control circuits so as to continuously execute the plurality of different tests corresponding to the plurality of test modes by switching the plurality of test modes. The test sequence control circuit includes:
2. The test circuit according to claim 1, wherein when a test end notification is received from any one of the plurality of test control circuits, a test control circuit corresponding to a test mode of a test to be executed next is operated. . The test sequence control circuit includes:
3. The test circuit according to claim 2, wherein among the plurality of test control circuits, the operation of a test control circuit other than the test control circuit corresponding to the test mode of the test being executed is stopped. A plurality of test target circuits to be subjected to the plurality of different tests;
The test sequence control circuit includes:
4. The test target circuit to be tested next is operated when a test end notification is received from any one of the plurality of test control circuits. 5. The test circuit described in the section. The test control circuit includes:
5. The test circuit according to claim 1, wherein when an execution of a test in a test mode corresponding to the test control circuit is completed, an enable signal for notifying the completion is output to the test order control circuit. 6. A test method using a test circuit for performing a burn-in test of a semiconductor integrated circuit,
The test circuit includes:
Multiple test control procedures to control the execution of tests corresponding to multiple test modes;
A test method for executing a test order control procedure for controlling the plurality of test control circuits so as to continuously execute the tests corresponding to the plurality of test modes.

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