JP2010199840A - Variable gain amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain amplifier which suppresses the lowering of a cutoff frequency when being controlled to a low gain. <P>SOLUTION: The variable gain amplifier includes a plurality of source-grounded transistors MBs supplied with input signals IN at the gate and turned to an active state respectively corresponding to gain control, a load circuit L1 connected to a power supply voltage, and gate-grounded transistors VG1 and VG2 provided between the load circuit and the drains of the source-grounded transistors, and output signals are generated in the connection node of the load circuit and the gate-grounded transistors. The variable gain amplifier is further provided with a drain current addition circuit 20 which is connected to the source of the gate-grounded transistor and supplies a drain current between the drain and source of the gate-grounded transistor, the drain current addition circuit supplies a first drain current to the source-grounded transistor when the number of the source-grounded transistors in an active state is a first number, and supplies a second drain current larger than the first drain current when it is a second number smaller than the first number. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a variable gain amplifier.

  The variable gain amplifier is an amplifier capable of variably controlling the gain according to the gain control signal. A variable gain amplifier that amplifies a high-frequency signal is provided in a receiver or a transmitter of a wireless communication device.

  The variable gain amplifier has, for example, a configuration in which a plurality of grounded-source transistors that input high-frequency input signals to the gate are connected in parallel, and by controlling a switch that applies a gate bias voltage to the gate of each source-grounded transistor, The number of active-source grounded transistors is increased or decreased, and the gain is variably controlled. The variable gain amplifier provides a load resistance or load inductance between the drain terminal of the common source transistor and the power supply, and outputs an output signal from the drain terminal.

  The variable gain amplifier may be configured by cascode-connecting a common-gate transistor between the drain of the common-source transistor and a load resistor or load inductance. In this case, the output terminal is a connection terminal between the drain terminal of the common-gate transistor and the load resistance or load inductance.

  Such a variable gain amplifier is described in the following Patent Documents 1, 2, 3, and the like.

JP 2007-259409 A JP 2007-221402 A JP 2003-60456 A

  A cascode-connected variable gain amplifier increases the gain by increasing the number of transistors that become active by applying a gate bias voltage among a plurality of common-source transistors provided in parallel. Reduce gain. That is, in order to increase the gain, the fact that the substantial gate width is increased by increasing the number of operating source (active state) source-grounded transistors is used. Therefore, when the gain increases, the drain current of the grounded-gate transistor connected to the output terminal increases and its drain-source resistance decreases. On the other hand, when the gain decreases, the drain current of the grounded-gate transistor decreases and its drain・ Source resistance increases.

  Since the output resistance of the amplifier depends on the drain-source resistance of the common-gate transistor, if the drain-source resistance varies according to the gain, the output resistance of the amplifier also varies. Since the frequency characteristics of the amplifier are inversely proportional to the signal frequency, output resistance, output capacitance, etc., an increase in output resistance due to a decrease in gain causes a reduction in cut-off frequency, which is not preferable.

  Accordingly, an object of the present invention is to provide a variable gain amplifier in which the cut-off frequency is suppressed from decreasing as the gain decreases.

  The first aspect of the variable gain amplifier includes a plurality of common-source transistors, each of which is supplied with an input signal to a gate and is activated according to gain control, a load circuit connected to a power supply voltage, the load circuit, and the plurality of A common-gate transistor provided between the drain of the common-source transistor and an output signal generated at a connection node between the load circuit and the common-gate transistor. The variable gain amplifier further includes a drain current addition circuit that is connected to a source of the grounded-gate transistor and supplies a drain current between a drain and a source of the grounded-gate transistor, and the active-source grounded transistor is a first grounded transistor. In the case of a number, the drain current addition circuit supplies a first drain current to the source-grounded transistor, and in the case of a second number less than the first number, a second greater than the first drain current. Supply the drain current.

  According to the first aspect, the fluctuation of the drain-source current of the common-gate transistor of the variable gain amplifier is suppressed, and the cut-off frequency is suppressed from decreasing with the decrease in gain.

It is a figure which shows the circuit example of the variable gain amplifier to which this Embodiment is applied. It is a figure which shows the frequency characteristic H (s) of the amplifier of FIG. 1 is a circuit diagram of a variable gain amplifier according to a first embodiment. 1 is a circuit diagram of a differential variable gain amplifier according to a first embodiment. FIG. It is a circuit diagram of the variable gain amplifier in 2nd Embodiment. FIG. 5 is a circuit diagram of a differential variable gain amplifier according to a second embodiment. It is a figure which shows the frequency characteristic H (s) of the amplifier in this Embodiment.

  FIG. 1 is a diagram illustrating a circuit example of a variable gain amplifier to which the present embodiment is applied. This variable gain amplifier includes a plurality of common-source transistors M1 to Mn whose gates are supplied with a high-frequency input signal IN, a load inductance L1 constituting a load circuit connected to a power supply voltage AVD, a load inductance L1 and a common-source source. A gate-grounded transistor MB provided between the drains of the transistors M1 to Mn and having a gate grounded at a high frequency, and an amplified output signal OUT is connected to a connection node between the load inductance L1 and the gate-grounded transistor MB. Generate. The load inductance L1 may be a load resistance element.

  A gate bias voltage VG1 is supplied to the gates of the plurality of common source transistors M1 to Mn via resistors R1 to Rn, respectively. A gate bias voltage VG1 is always supplied to the gate of the first common-source transistor M1 through the resistor R1, and the active state is maintained. On the other hand, the gate bias voltage VG1 is supplied to the gates of the second to nth common source transistors M2 to Mn via the resistors R2 to Rn and the amplification gate bias switches SW2 to SWn. These amplification gate bias switches SW2 to SW3 are on / off controlled by an amplification control signal (not shown).

  When increasing the gain, the amplification gate bias switches SW2 to SWn are sequentially turned on to increase the number of common-source transistors M2 to Mn that amplify the input signal. On the other hand, when the gain is decreased, the amplification gate bias switches SWn to SW2 are sequentially turned off to reduce the number of common source transistors M2 to Mn that amplify the input signal. Increasing the number of active-source grounded transistors supplied with the gate bias voltage VG1 means increasing the gate width and increasing the transconductance gm.

  A predetermined gate bias voltage VG2 is applied to the gate of the common-gate transistor MB. The amplifier of FIG. 1 is a cascode-connected amplifier in which a common source transistor and a common gate transistor are combined.

  The variable gain amplifier is required to have a highly accurate variable gain width in a desired frequency band. The gain of the amplifier with the common source transistor is determined by the mutual conductance gm of the transistor and the load. The mutual conductance gm can be expressed by the following equation.

 Here, Vod is the overdrive voltage, Vgs is the gate bias voltage, Vth is the threshold voltage of the transistor, μ is the mobility, Co is the gate capacitance per unit area, Wg is the gate width of the transistor, and Lg is the gate length of the transistor. is there.

  The transconductance gm means the slope of the transistor characteristics when the horizontal axis is the gate voltage and the vertical axis is the drain current. The overdrive voltage Vod is large, and the slope of the transistor increases as the gate width of the transistor increases. Means higher. Therefore, selectively applying the gate bias voltage VG1 to the gate of the common source transistor to make it active is equivalent to variably controlling the gate width Wg of the transistor, thereby making it possible to variably control the gain.

  The drain-source current (drain current) Ids of the common source transistor can be expressed by the following equation.

  As is apparent from this equation, when the gate width Wg of the common source transistors M1 to Mn is changed, the drain-source current also changes. Along with this, the drain-source current of the common-gate transistor MB also varies.

  On the other hand, the frequency characteristic of the output of the amplifier (the output transfer function with respect to the input) depends on the output resistance Rout. The following equation represents the frequency characteristic H (s).

Here, A ₀ is the gain at low frequency, s = jω is the frequency component of the input signal, R is the output resistance Rout of the amplifier, and C is the load capacitance of the output terminal of the amplifier (wiring capacitance and next stage circuit (Input capacity). According to this equation, when the frequency component s = jω increases (high frequency), the frequency characteristic H (s) decreases. This means the cutoff frequency. Further, according to this equation, H (s) decreases as RC increases, and H (s) increases as RC decreases.

On the other hand, the output resistance Rout of the amplifier includes gm _B which is a mutual conductance of the grounded gate transistor MB connected to the output terminal OUT, an output resistance ro _B of the transistor MB, an output resistance ro1 of the common source transistors M1 to Mn, and a load impedance. almost determined by the Z _L, it is shown in the following formula.

  Since the DC voltage Vds between the drain and source of the grounded-gate transistor MB is constant, when the drain-source current Ids decreases, the output resistance roB increases and the output resistance Rout of the amplifier also increases.

  Therefore, if the drain-source current Ids is reduced by reducing the number of active source grounded transistors in order to increase the gain of the amplifier of FIG. 1, the drain-source DC voltage Vds is constant. The resistance roB of the ground transistor MB increases, and the output resistance Rout of the amplifier also increases. As a result, the frequency characteristic H (s) of the amplifier is lowered, the cut-off frequency is lowered, and the gain in the high frequency band is lowered.

  FIG. 2 is a diagram showing the frequency characteristic H (s) of the amplifier of FIG. The horizontal axis is frequency and the vertical axis is gain (H (s)). As described above, when the gain of the amplifier is increased, the drain-source current Ids increases, the output resistance Rout decreases, and the cutoff frequency increases. Conversely, when the gain is lowered, the drain-source current Ids is reduced, the output providing Rout is increased, and the cut-off frequency is lowered. Therefore, when the gain is controlled to be low, the reduction in the gain in the high frequency band f0 is greatly reduced as compared with the high gain due to the reduction in the cut-off frequency.

  FIG. 3 is a circuit diagram of the variable gain amplifier according to the first embodiment. As in the amplifier of FIG. 1, this variable gain amplifier has a plurality of common-source transistors M1 to Mn whose gates are supplied with a high-frequency input signal IN through capacitors C1 to Cn, and a load connected to a power supply voltage AVD. The circuit includes a load inductance L1 constituting a circuit, and a gate-grounded transistor MB provided between the load inductance L1 and the drains of the common-source transistors M1 to Mn and having a gate grounded in a high-frequency manner. An amplified output signal OUT is generated at a connection node with the ground transistor MB. The load inductance L1 may be a load resistance element.

  The gain control circuit 10 turns on and off the amplification gate bias switches SW2 to SWn by the gain control signals GC2 to GCn, and supplies the gate bias voltage VG1 to the gates of the common source transistors M2 to Mn. If the gate widths of the common source transistors M1 to Mn are designed to a predetermined ratio, the gate width is increased at a predetermined ratio by increasing the number of active source grounded transistors to which the gate bias voltage VG1 is applied. , The gain can be increased by a predetermined ratio. Conversely, by reducing the number of active-source grounded transistors, the gate width can be reduced at a predetermined ratio, and the gain can be decreased at a predetermined ratio.

  The variable gain amplifier of FIG. 3 has a drain current adding circuit 20 at the source node N10 of the common-gate transistor MB. The drain current adding circuit 20 reduces the current supplied to the node N10 and decreases the number of active amplification grounded transistors M2 to Mn when the number of active amplification grounded transistors M2 to Mn increases. For example, the current supplied to the node N10 is increased. As a result, when the number of active amplification source grounded transistors M2 to Mn is decreased in order to reduce the gain, the additional drain current of the drain current adding circuit 20 increases, and the drain-source between the gate grounded transistor MB is increased. A decrease in current Ids can be suppressed, an increase in output resistance Rout can be suppressed, and a decrease in gain in a high frequency band can be suppressed.

  The drain current addition circuit 20 preferably includes the additional source grounded transistors MA2 to MAn, the resistors RA2 to RAn that supply the gate bias voltage VG1 to them, and the switches SWA2 to SWAn similarly to the amplification source grounded transistors M2 to Mn. And inverters INV2 to NVn. The switches SWA2 to SW2n are on / off controlled by inverted signals of the gain control signals GC2 to GCn. Further, preferably, the gate width of the additional source grounded transistors MA2 to MAn is the same as that of the amplifying source grounded transistors M2 to Mn.

  That is, when the amplification gate bias switch SW2 is turned off by the gain control signal GC2, the additional gate bias switch SWA2 is turned on by the control signal obtained by inverting the gain control signal GC2 by the inverter INV2, and the additional source grounded transistor MA2 is turned on. To the active state. As described above, when the gain gate bias switch SW2 is turned off and the amplification source grounded transistor M2 is set in the non-active state in accordance with the gain reduction control, the additional source grounded transistor MA2 is activated and the gate grounding is performed. The drain-source current of the transistor MB can be kept constant. Alternatively, even when the gate width of the additional source grounded transistor MA2 is smaller than the gate width of the amplifying source grounded transistor M2, it is possible to suppress a decrease in the drain-source current of the grounded gate transistor MB, and an excessive cutoff frequency. Can be suppressed.

  In the example of FIG. 3, the additional source grounded transistors MA2 to MAn are provided in the same number and the same size as the gain controlling grounded source transistors M2 to Mn. However, in order to suppress a decrease in the cut-off frequency when the gain is decreased, it corresponds to an amplifying source grounded transistor that is controlled to an active state when the gain is low, for example, transistors M2 to Mm (m <n). Only an additional source grounded transistor may be provided.

  With such a configuration, a reduction in the cut-off frequency due to the gain reduction is acceptable in the high gain region, but a reduction in the cut-off frequency due to the gain reduction can be suppressed in the low gain region. By reducing the number of additional source grounded transistors, it is possible to suppress an increase in overall power consumption.

  Furthermore, the size of the additional source grounded transistor may be smaller than that of the amplifying source grounded transistor. Since the transistor size is small, the added drain current is insufficient, but an excessive decrease in the drain-source current of the common-gate transistor MB can be suppressed.

  FIG. 4 is a circuit diagram of the differential variable gain amplifier according to the first embodiment. In the case of the differential type, the amplifier circuit of FIG. 3 is used to amplify the difference between the positive phase side input signal IN and the negative phase side input signal INx, and the positive phase side output signal OUT and the negative phase side output signal OUTx. Is generated. A circuit on the opposite phase side has x attached to the subscript of each transistor, resistance, and inductance.

  First, the amplifier is connected to a plurality of source grounded transistors M1 to Mn and M1x to Mnx whose gates are supplied with high-frequency input signals IN and INx through capacitors C1 to Cn and C1x to Cnx, respectively, and a power supply voltage AVD. Load inductances L1 and L1x constituting the load circuit, and gate inductance transistors MB provided between the load inductances L1 and L1x and the drains of the common source transistors M1 to Mn and M1x to Mnx and having a gate grounded in a high frequency manner. , MBx, and amplified output signals OUT, OUTx are generated at connection nodes between the load inductances L1, L1x and the common-gate transistors MB, MBx.

  Further, the drain current adding circuit 20 includes additional source grounded transistors MA2 to MAn, MA2x to MAnx, resistors RA2 to RAn and RA2x to RAnx for supplying the gate bias voltage VG1, and additional gate bias switches SWA2 to SWA2. SWAn. The additional gate bias switches SWA2 to SWAn are shared by the additional source grounded transistors MA2 to MAn and MA2x to MAnx on both sides.

  FIG. 5 is a circuit diagram of the variable gain amplifier according to the second embodiment. This variable gain amplifier has a common source transistor M1 to Mn for amplification whose high frequency input signal is supplied to the gate through a common capacitor C1, a load inductance L1 connected to the power supply voltage AVD, and a gate bias at the gate. A first grounded transistor MB that is supplied with voltage VG2 and is grounded at a high frequency, and a second grounded transistor M1 to Mn that is provided between the plurality of amplifying source grounded transistors M1 to Mn and the first grounded gate transistor MB, respectively. Gate-grounded transistors MC1 to MCn. The load inductance may be a load resistance.

  A gate bias voltage VG1 is applied to the amplifying source ground transistors M1 to Mn via a common resistor R1. However, the third gate bias voltage VG3 is supplied to the second grounded gate transistors MC2 to MCn via the amplification gate bias switches SWC2 to SWCn. The third gate bias voltage VG3 is supplied to the second grounded gate transistor MC1.

  When the gain is the smallest, only the amplifying source grounded transistor M1 is in an active state, and the input signal IN is amplified by a small drain current. The amplification gate bias switches SWC2 to SWCn are sequentially turned on by a gain control signal (not shown), thereby increasing the number of active amplification source grounded transistors M2 to Mn, increasing the drain current, and increasing the gain. Get higher.

  As described above, when the number of the active amplification common source transistors M1 to Mn is controlled by supplying the gate bias voltage VG3 to the second common gate transistors MC1 to MCn, the amplification common source transistor A common capacitor C1 and a common gate bias supply resistor R1 can be used for M1 to Mn, and the number of circuit elements can be reduced.

  In the second embodiment of FIG. 5, the drain current adding circuit 20 is connected to the source node N20 of the first grounded gate transistor MB. Similarly to the first embodiment, the drain current adding circuit 20 reduces the current supplied to the node N20 as the number of active source grounded transistors M2 to Mn increases in the active state, thereby increasing the active state. If the number of common source transistors M2 to Mn decreases, the current supplied to the node N10 is increased. As a result, when the number of active amplification source grounded transistors M2 to Mn is reduced in order to reduce the gain, the additional drain current of the drain current adding circuit 20 increases, and the drain of the first gate grounded transistor MB is increased. -Suppressing a decrease in the inter-source current Ids, suppressing an increase in the output resistance Rout, and suppressing a decrease in gain in a high frequency band.

  The drain current adding circuit 20 has additional source grounded transistors MA2 to MAn whose gate bias voltage VG1 is always supplied to the gate and additional gate grounded transistors MD2 to MDn. A third gate bias voltage VG3 is supplied to the gate by additional gate bias switches SWD2 to SWDn.

  As in the first embodiment, the additional gate bias switches SWD2 to SWDn are on / off controlled by an inverted signal of a gain control signal that controls the amplification gate bias switches SWC2 to SWCn. That is, when the amplification gate bias switches SWC2 to SWCn are sequentially turned on, the additional gate bias switches SWD2 to SWDn are sequentially turned off and the amplification gate bias switches SWC2 to SWCn are sequentially turned off. When this is done, the additional gate bias switches SWD2 to SWDn are sequentially turned on.

  Desirably, the additional source grounded transistors MA2 to MAn and the additional gate grounded transistors MD2 to MDn correspond to the amplifying source grounded transistors M2 to Mn and the amplifying second gate grounded transistors MC2 to MCn. It is provided and is the same size. However, the additional source grounded transistors MA2 to MAn and the additional gate grounded transistors MD2 to MDn are not necessarily the numbers corresponding to the amplifying source grounded transistors M2 to Mn and the amplifying second gate grounded transistors MC2 to MCn. There is no need to provide the same size.

  Similarly to the first embodiment, the variable gain amplifier of the second embodiment also suppresses a decrease in the drain-source current of the first grounded gate transistor MB when the gain is controlled to be low. Thus, an excessive decrease in the cut-off frequency can be suppressed.

  FIG. 6 is a circuit diagram of a differential variable gain amplifier according to the second embodiment. The variable gain amplifier of FIG. 5 is provided on the positive phase side and the negative phase side. A subscript x is given to each transistor, resistor, and capacitor on the negative phase side. This differential variable gain amplifier amplifies differential input signals IN and INx to generate differential output signals OUT and OUTx. Further, since the drain current adding circuit 20 is provided, even when the gain is controlled to be low, an excessive decrease in the drain-source current of the first grounded gate transistors MB and MBx is suppressed, and the cut-off frequency is decreased. Is suppressed.

  FIG. 7 is a diagram showing frequency characteristics H (s) of the amplifiers in the first and second embodiments. As in FIG. 2, the horizontal axis represents frequency and the vertical axis represents gain. In this embodiment, since the drain-source current of the grounded-gate transistor is suppressed from being excessively reduced when the gain is controlled to be low, the cutoff frequency is suppressed from decreasing even when the gain is low. The Therefore, as shown in FIG. 7, it is possible to suppress an excessive decrease in gain when the gain is controlled to be low in a predetermined high-frequency band f0.

  In the present embodiment, the common source transistor and the common gate transistor are all constituted by N-channel MOS transistors. However, these transistors may be constituted by P-channel MOS transistors. In this case, the power supply voltage AVD is replaced with the ground, and the ground is replaced with the positive power supply voltage.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of common-source transistors, each of which receives an input signal to the gate and is activated in response to gain control;
A load circuit connected to the supply voltage;
A common-gate transistor provided between the load circuit and the drains of the plurality of common-source transistors;
An output signal is generated at a connection node between the load circuit and the common gate transistor,
And a drain current addition circuit connected to the source of the grounded-gate transistor and supplying a drain current between the drain and source of the grounded-gate transistor,
When the number of the active source grounded transistors is the first number, the drain current adding circuit supplies the first drain current to the source grounded transistors, and when the second number is less than the first number. , A variable gain amplifier that supplies a second drain current greater than the first drain current.

(Appendix 2)
In Appendix 1,
The additional drain current circuit has a plurality of additional common source transistors in parallel with the common source transistor, and a third number of the additional sources when the first common source transistor is in the active state. Activate a grounded transistor and activate a fourth number of the additional source grounded transistors greater than the third number when the number of active source grounded transistors is a second number less than the first number A variable gain amplifier.

(Appendix 3)
A plurality of amplifying source-grounded transistors to which an input signal is supplied to a gate and a gate bias voltage is supplied to each according to gain control;
A load circuit connected to the supply voltage;
A grounded gate transistor provided between the load circuit and the drains of the plurality of common source transistors for amplification;
An output signal is generated at a connection node between the load circuit and the common gate transistor,
And a drain current addition circuit connected to the source of the grounded-gate transistor and supplying a drain current between the drain and source of the grounded-gate transistor,
When the common source transistor for amplification to which the gate bias voltage is supplied is the first number, the drain current addition circuit supplies the first drain current to the common source transistor, and the first number is smaller than the first number. A variable gain amplifier that supplies a second drain current larger than the first drain current when the number is two.

(Appendix 4)
In Appendix 3,
And a plurality of amplifying gate bias switches that are on / off controlled in accordance with a gain control signal and respectively supply a gate bias voltage to the gates of the plurality of amplifying source grounded transistors,
The drain current adding circuit is
A plurality of additional source grounded transistors provided in parallel between a drain and a source of the plurality of amplifying source grounded transistors;
A plurality of additional gate bias switches which are on / off controlled according to the gain control signal and supply the gate bias voltages to the gates of the plurality of additional source grounded transistors,
When any of the amplification gate bias switches is controlled to be turned on, any of the additional gate bias switches is controlled to be turned off, and when any of the amplification gate bias switches is controlled to be turned off, the addition is performed. A variable gain amplifier in which any one of the gate bias switches is controlled to be turned on.

(Appendix 5)
In Appendix 3,
The plurality of amplifying source grounded transistors have a predetermined ratio of gate width, and the plurality of additional source grounding transistors are provided corresponding to at least a part of the plurality of amplifying source grounded transistors. A variable gain amplifier having a ratio of gate widths.

(Appendix 6)
A plurality of common source transistors for amplification, wherein an input signal is supplied to the gate and a first gate bias voltage is applied to the gate;
A load circuit connected to the supply voltage;
A first grounded gate transistor provided between the load circuit and the drains of the plurality of common source transistors for amplification;
A plurality of second gate bias voltages are provided between the source of the first grounded gate transistor and the drains of the plurality of common source amplification transistors, respectively, and each of the second gate bias voltages is supplied in accordance with gain control. A grounded-gate transistor,
An output signal is generated at a connection node between the load circuit and the first grounded-gate transistor,
And a drain current adding circuit connected to the source of the first grounded-gate transistor and supplying a drain current between the drain and source of the first grounded-gate transistor,
When the number of second gate grounded transistors to which the second gate bias voltage is supplied is the first number, the drain current adding circuit supplies the first drain current to the amplification source grounded transistor, and A variable gain amplifier that supplies a second drain current greater than the first drain current in the case of a second number less than one.

(Appendix 7)
In Appendix 6,
And a plurality of amplifying gate bias switches that are on / off controlled in accordance with a gain control signal and supply the second gate bias voltage to the gates of the plurality of second gate-grounded transistors,
The drain current adding circuit is
A plurality of additional gate grounded transistors and a plurality of additional source grounded transistors provided in parallel with the plurality of second gate grounded transistors and a plurality of amplification source grounded transistors, and on / off control according to the gain control signal A plurality of additional gate bias switches for supplying the second gate bias voltage to the gates of the plurality of additional grounded gate transistors,
When any of the amplification gate bias switches is on-controlled, any of the additional gate bias switches is off-controlled, and when any of the gate bias switches is off-controlled, the additional gate A variable gain amplifier in which one of the bias switches is on-controlled.

(Appendix 8)
In Appendix 7,
The plurality of amplifying source grounded transistors have a predetermined ratio of gate width, and the plurality of additional source grounding transistors are provided corresponding to at least a part of the plurality of amplifying source grounded transistors. A variable gain amplifier having a ratio of gate widths.

(Appendix 9)
In any one of appendices 1 to 8,
The amplification source grounded transistor, gate grounded transistor, and load circuit are provided on the positive phase side and the negative phase side, respectively, and a variable gain amplifier that amplifies a differential input signal and generates a differential output signal.

IN: input signal OUT: output signals M1 to Mn: amplification source grounded transistor MB: source grounded transistors MA1 to MAn: additional source grounding transistors VG1, VG2: gate bias voltage L1: load circuit, load inductance AVD: power supply voltage

Claims (6)

A plurality of common-source transistors, each of which receives an input signal to the gate and is activated in response to gain control;
A load circuit connected to the supply voltage;
A common-gate transistor provided between the load circuit and the drains of the plurality of common-source transistors;
An output signal is generated at a connection node between the load circuit and the common gate transistor,
And a drain current addition circuit connected to the source of the grounded-gate transistor and supplying a drain current between the drain and source of the grounded-gate transistor,
When the number of the active source grounded transistors is the first number, the drain current adding circuit supplies the first drain current to the source grounded transistors, and when the second number is less than the first number. , A variable gain amplifier that supplies a second drain current greater than the first drain current. In claim 1,
The additional drain current circuit has a plurality of additional common source transistors in parallel with the common source transistor, and a third number of the additional sources when the first common source transistor is in the active state. Activate a grounded transistor and activate a fourth number of the additional source grounded transistors greater than the third number when the number of active source grounded transistors is a second number less than the first number A variable gain amplifier. A plurality of amplifying source-grounded transistors to which an input signal is supplied to a gate and a gate bias voltage is supplied to each according to gain control;
A load circuit connected to the supply voltage;
A grounded gate transistor provided between the load circuit and the drains of the plurality of common source transistors for amplification;
An output signal is generated at a connection node between the load circuit and the common gate transistor,
And a drain current addition circuit connected to the source of the grounded-gate transistor and supplying a drain current between the drain and source of the grounded-gate transistor,
When the common source transistor for amplification to which the gate bias voltage is supplied is the first number, the drain current addition circuit supplies the first drain current to the common source transistor, and the first number is smaller than the first number. A variable gain amplifier that supplies a second drain current larger than the first drain current when the number is two. In claim 3,
And a plurality of amplifying gate bias switches that are on / off controlled in accordance with a gain control signal and respectively supply a gate bias voltage to the gates of the plurality of amplifying source grounded transistors,
The drain current adding circuit is
A plurality of additional source grounded transistors provided in parallel between a drain and a source of the plurality of amplifying source grounded transistors;
A plurality of additional gate bias switches which are on / off controlled according to the gain control signal and supply the gate bias voltages to the gates of the plurality of additional source grounded transistors,
When any of the amplification gate bias switches is controlled to be turned on, any of the additional gate bias switches is controlled to be turned off, and when any of the amplification gate bias switches is controlled to be turned off, the addition is performed. A variable gain amplifier in which any one of the gate bias switches is controlled to be turned on. A plurality of common source transistors for amplification, wherein an input signal is supplied to the gate and a first gate bias voltage is applied to the gate;
A load circuit connected to the supply voltage;
A first grounded gate transistor provided between the load circuit and the drains of the plurality of common source transistors for amplification;
A plurality of second gate bias voltages are provided between the source of the first grounded gate transistor and the drains of the plurality of common source amplification transistors, respectively, and each of the second gate bias voltages is supplied in accordance with gain control. A grounded-gate transistor,
An output signal is generated at a connection node between the load circuit and the first grounded-gate transistor,
And a drain current adding circuit connected to the source of the first grounded-gate transistor and supplying a drain current between the drain and source of the first grounded-gate transistor,
When the number of second gate grounded transistors to which the second gate bias voltage is supplied is the first number, the drain current adding circuit supplies the first drain current to the amplification source grounded transistor, and A variable gain amplifier that supplies a second drain current greater than the first drain current in the case of a second number less than one. In claim 5,
And a plurality of amplifying gate bias switches that are on / off controlled in accordance with a gain control signal and supply the second gate bias voltage to the gates of the plurality of second gate-grounded transistors,
The drain current adding circuit is
A plurality of additional gate grounded transistors and a plurality of additional source grounded transistors provided in parallel with the plurality of second gate grounded transistors and a plurality of amplification source grounded transistors, and on / off control according to the gain control signal A plurality of additional gate bias switches for supplying the second gate bias voltage to the gates of the plurality of additional grounded gate transistors,
When any of the amplification gate bias switches is on-controlled, any of the additional gate bias switches is off-controlled, and when any of the gate bias switches is off-controlled, the additional gate A variable gain amplifier in which one of the bias switches is on-controlled.

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