JP2010192877A - Method of fabricating thin-film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming microcrystalline semiconductor layers having high crystallinity on insulating layers, and to provide a method of fabricating thin-film transistors having satisfactory electrical characteristics with high productivity. <P>SOLUTION: A gate electrode is formed on a substrate, and the insulating layer including nitrogen is formed on the gate electrode. Then, plasma is generated on the insulating layer including nitrogen by sedimentary gas including silicon, oxidizing gas including nitrogen, and hydrogen to form a silicon oxide layer. After that, plasma is generated on the silicon oxide layer by sedimentary gas including silicon or germanium, and hydrogen. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a method for manufacturing a thin film transistor and a display device using the thin film transistor.

As a kind of field effect transistor, a thin film transistor in which a channel region is formed in a semiconductor layer formed over a substrate having an insulating surface is known. A technique using amorphous silicon, microcrystalline silicon, or polycrystalline silicon as a semiconductor layer used in a thin film transistor is disclosed (see Patent Documents 1 to 5). A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display screen.

In addition, after introducing a silicon-containing gas and an oxygen-containing gas into the processing chamber of the plasma CVD apparatus and generating a plasma of these gases to form a silicon oxide film, the supply of the silicon-containing gas is stopped, and hydrogen is supplied into the reaction chamber. A good silicon oxide film is formed by generating hydrogen and oxygen plasma to fill defects in the silicon oxide film. Moreover, oxygen gas, nitrous oxide, etc. are used as oxygen-containing gas (refer patent document 6).

JP 2001-053283 A JP-A-5-129608 JP 2005-049832 A Japanese Patent Laid-Open No. 7-131030 JP 2005-191546 A JP-A-11-293470

An object of one embodiment of the present invention is to form a microcrystalline semiconductor layer with high crystallinity over a silicon oxide layer. Another object of one embodiment of the present invention is to provide a method for manufacturing a thin film transistor with favorable electrical characteristics with high productivity.

A gate electrode is formed over the substrate, and an insulating layer containing nitrogen is formed over the gate electrode. Next, plasma is generated on the insulating layer containing nitrogen using a deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen to form a silicon oxide layer. Next, the gist is to form a microcrystalline semiconductor layer on a silicon oxide layer by using a deposition gas containing silicon or germanium and hydrogen to generate plasma.

A gate electrode is formed over the substrate, and an insulating layer containing nitrogen is formed over the gate electrode. Next, plasma is generated on the insulating layer containing nitrogen using a deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen to form a silicon oxide layer. Next, on the silicon oxide layer, plasma is generated using a deposition gas containing silicon or germanium and hydrogen to form a first semiconductor layer having a thickness of 3 to 10 nm, preferably 3 to 5 nm. . Next, plasma is generated using a deposition gas containing silicon, a gas containing hydrogen, and nitrogen, and the first semiconductor layer is partially grown as a seed crystal to form a microcrystalline semiconductor. A second semiconductor layer having a plurality of cone-shaped convex portions is formed. Next, a semiconductor layer to which an impurity element imparting one conductivity type is added (hereinafter referred to as an impurity semiconductor layer) is formed, a conductive layer is formed, and a thin film transistor is manufactured. Note that a rare gas such as helium, argon, neon, krypton, or xenon may be used as a source gas for the first semiconductor layer.

A microcrystalline semiconductor layer is formed as the first semiconductor layer. A stack of the first semiconductor layer and the second semiconductor layer is a third semiconductor layer, and the third semiconductor layer includes a microcrystalline semiconductor layer in contact with the gate insulating layer, a mixed layer in contact with the microcrystalline semiconductor layer, Have Further, a layer including an amorphous semiconductor in contact with the mixed layer may be included. Note that the microcrystalline semiconductor layer in contact with the gate insulating layer includes a first semiconductor layer and a microcrystalline semiconductor layer which is crystal-grown using the first semiconductor layer as a seed crystal in the deposition of the second semiconductor layer.

The microcrystalline semiconductor layer included in the third semiconductor layer functions as a channel formation region of the thin film transistor, and a layer including an amorphous semiconductor functions as a high resistance region. The impurity semiconductor layer functions as a source region and a drain region of the thin film transistor, and the conductive layer functions as a wiring.

When a silicon oxide layer is formed using a deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen as a forming material of the gate insulating film, the oxidizing gas containing nitrogen reacts with hydrogen, and nitrogen and water are reacted. Generated. Next, the deposition gas containing silicon and the produced water react to produce silicon oxide and hydrogen. For this reason, the nitrogen content contained in the generated silicon oxide layer can be reduced.

By reducing the amount of nitrogen contained in the silicon oxide layer, when a microcrystalline semiconductor layer is formed over the silicon oxide layer, the crystallization speed of the microcrystalline semiconductor layer can be increased and the crystallinity can be increased. Therefore, a microcrystalline semiconductor layer with high crystallinity from the interface with the silicon oxide layer can be formed.

From the above, a microcrystalline semiconductor layer with high crystallinity can be formed over the silicon oxide layer. In addition, a thin film transistor with high on-state current and high field-effect mobility can be manufactured with high productivity. Further, a thin film transistor with low off-state current, high on-state current, and high field-effect mobility can be manufactured with high productivity.

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. 10A to 10D illustrate a method for manufacturing a thin film transistor. 10A to 10D illustrate a method for manufacturing a thin film transistor. 10A to 10D illustrate a method for manufacturing a thin film transistor. 10A to 10D illustrate a method for manufacturing a thin film transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. It is an example of the time chart explaining the process of forming a thin-film transistor. 10A and 10B illustrate a multi-tone mask that can be used in a method for manufacturing a thin film transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. It is a figure which shows an example of the CVD apparatus which can be used for the manufacturing process of a thin-film transistor. It is an example of the time chart explaining the process of forming a thin-film transistor. It is an example of the time chart explaining the process of forming a thin-film transistor. It is an example of the time chart explaining the process of forming a thin-film transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a thin film transistor. FIG. 11 is a cross-sectional view illustrating a display device. FIG. 11 is a cross-sectional view illustrating a display device. An electronic device to which a thin film transistor is applied. 10A to 10D illustrate a method for manufacturing a thin film transistor.

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the disclosed invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the disclosed invention. The Therefore, the disclosed invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a method for manufacturing a thin film transistor will be described with reference to FIGS. Thin film transistors have higher carrier mobility in the n-type than in the p-type. In addition, it is preferable that all thin film transistors formed over the same substrate have the same polarity because the number of steps can be reduced. Therefore, in this embodiment, a method for manufacturing an n-type thin film transistor is described.

A gate electrode 103 is formed on the substrate 101. Next, an insulating layer 104 containing nitrogen covering the gate electrode 103 is formed, and a silicon oxide layer 105 is formed over the insulating layer 104 containing nitrogen. (See FIG. 1A).

As the substrate 101, a glass substrate, a ceramic substrate, a plastic substrate having heat resistance enough to withstand the processing temperature of the manufacturing process, or the like can be used. In the case where the substrate does not require translucency, a metal substrate such as a stainless alloy provided with an insulating layer on the surface may be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used.

The gate electrode 103 may be formed as a single layer or a stack using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component. it can. Alternatively, a semiconductor layer typified by polycrystalline silicon doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used.

The gate electrode 103 is formed by forming a conductive layer using the above material on the substrate 101 by a sputtering method or a vacuum evaporation method, forming a mask on the conductive layer by a photolithography method, an inkjet method, or the like, The conductive layer can be formed by etching using a mask. In the photolithography process, a resist may be applied to the entire surface of the substrate. However, the resist can be saved by printing after printing the resist by a printing method in a region where a resist mask is to be formed, and the cost can be reduced. Reduction is possible.

Alternatively, a conductive nano paste such as silver, gold, or copper can be formed by discharging onto a substrate by an ink jet method and baking. Note that a nitride layer of the above-described metal material may be provided between the substrate 101 and the gate electrode 103 as a barrier metal that prevents adhesion between the gate electrode 103 and the substrate 101 and diffusion to the base. . Here, a conductive layer is formed over the substrate 101 and etched using a resist mask formed using a photomask.

Note that the side surface of the gate electrode 103 is preferably tapered. The semiconductor layer and the wiring layer are formed on the gate electrode 103 in a later process, so that the wiring is cut off at the level difference. In order to taper the side surface of the gate electrode 103, etching may be performed while the resist mask is retracted.

Further, a gate wiring (scanning line) and a capacitor wiring can be formed at the same time by the step of forming the gate electrode 103. Note that a scanning line refers to a wiring for selecting a pixel, and a capacitor wiring refers to a wiring connected to one electrode of a storage capacitor of the pixel. However, the present invention is not limited to this, and one or both of the gate wiring and the capacitor wiring may be provided separately from the gate electrode 103.

The insulating layer 104 containing nitrogen can be formed using a single layer or stacked layers of a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. By forming the insulating layer 104 containing nitrogen, it is possible to prevent impurities from the substrate, particularly alkali metal ions, from entering a microcrystalline semiconductor layer to be formed later, and fluctuation in threshold voltage of the thin film transistor Can be reduced.

The insulating layer 104 containing nitrogen can be formed by a CVD method, a sputtering method, or the like. In the case where the insulating layer 104 containing nitrogen is formed by a CVD method, high frequency power in the HF band from 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz, or high frequency power in the VHF band from 30 MHz to about 300 MHz. Typically, it is performed by applying 60 MHz. Alternatively, the insulating layer 104 containing nitrogen may be formed using a microwave plasma CVD apparatus with a high frequency (1 GHz or more). When the insulating layer 104 containing nitrogen is formed with a high frequency using a microwave plasma CVD apparatus, the withstand voltage between the gate electrode, the drain electrode, and the source electrode can be improved; thus, a highly reliable thin film transistor is obtained. be able to.

The silicon oxide layer 105 can be formed by a CVD method using a deposition gas containing silicon, an oxidation gas containing nitrogen, and hydrogen as a formation material of the gate insulating film. The silicon oxide layer 105 applies 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz HF band high frequency power, or VHF band high frequency power greater than 30 MHz to about 300 MHz, typically 60 MHz. It is done by doing. Alternatively, the silicon oxide layer 105 may be formed using a microwave plasma CVD apparatus with a high frequency (1 GHz or more). When the silicon oxide layer 105 is formed at a high frequency using a microwave plasma CVD apparatus, the breakdown voltage between the gate electrode, the drain electrode, and the source electrode can be improved; thus, a highly reliable thin film transistor can be obtained. it can.

The silicon oxide layer 105 is formed with a thickness that prevents nitrogen from entering the first semiconductor layer 106 formed later from the insulating layer 104 containing nitrogen. Alternatively, the silicon oxide layer 105 is formed to have a thickness at which the concentration of nitrogen desorbed from the insulating layer 104 containing nitrogen is reduced by etching of radicals in plasma when the silicon oxide layer is formed. Such a thickness is preferably 5 nm or more.

Typical examples of the deposition gas containing silicon include SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiF _{4, and the} like.

When a deposition gas containing silicon and oxygen or water are used as a raw material for the silicon oxide layer 105, the deposition gas containing silicon has high reactivity, and thus reacts when mixed between reaction chambers or piping of a plasma CVD apparatus. As a result, silicon oxide particles are generated. When a deposition gas containing silicon and an oxidizing gas containing nitrogen, typically nitrous oxide (N ₂ O), are used as a raw material for the silicon oxide layer 105, they do not react when mixed, and silicon in plasma Therefore, a silicon oxide layer can be deposited on the substrate in the reaction chamber.

However, if only a deposition gas containing silicon and an oxidation gas containing nitrogen are used as a raw material for the silicon oxide layer, nitrogen is mixed into the silicon oxide layer. The nitrogen is etched by hydrogen radicals during deposition of a microcrystalline semiconductor layer to be formed later, and is mixed into the deposited microcrystalline semiconductor layer.

Therefore, when hydrogen is used as a raw material for the silicon oxide layer together with a deposition gas containing silicon and an oxidizing gas containing nitrogen, as shown in Equation 1, an oxidizing gas containing nitrogen, typically oxygen sub-nitride and hydrogen, Reacts to produce nitrogen and water.

N ₂ O + H ₂ → N ₂ + H ₂ O (Equation 1)

Next, a silicon oxide layer having a low nitrogen content can be formed on the substrate by reacting the generated water and silicon-containing deposition gas, here silane, in plasma, as shown in Equation 2. it can.

2H ₂ O + SiH ₄ → SiO ₂ + 4H ₂ (Expression 2)

In addition, by using hydrogen as a raw material for the silicon oxide layer, a large amount of hydrogen radicals are generated in the plasma, and silicon oxide is deposited while being etched by the hydrogen radicals, so that a dense and hard silicon oxide layer is formed. Can do. Therefore, when the first semiconductor layer 107 is formed later, desorption of atoms due to etching of hydrogen radicals is reduced, so that the first semiconductor layer 107 with few impurities can be formed.

Next, the first semiconductor layer 106 is formed over the silicon oxide layer 105 (see FIG. 1B). The first semiconductor layer 106 is formed using a microcrystalline semiconductor layer. Typically, a microcrystalline silicon layer, a microcrystalline germanium layer, or a microcrystalline silicon germanium layer is formed. Since the first semiconductor layer 106 is formed over the silicon oxide layer 105 in which the nitrogen content is reduced, the first semiconductor layer with increased crystal growth rate and crystallinity from the interface of the silicon oxide layer 105 is formed. Can be formed.

The thickness of the first semiconductor layer 106 is 3 to 10 nm, preferably 3 to 5 nm, whereby a plurality of needles formed of a microcrystalline semiconductor are formed in the second semiconductor layer to be formed later. The length of the convex portion can be controlled.

The first semiconductor layer 106 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen in a treatment chamber of a plasma CVD apparatus. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, argon, neon, krypton, or xenon are mixed and formed by glow discharge plasma. The flow rate of hydrogen is diluted 10 to 2000 times, preferably 10 to 200 times the flow rate of the deposition gas containing silicon or germanium to form microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. .

Typical examples of the deposition gas containing silicon or germanium include SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiF ₄ , GeH ₄ , and Ge ₂ H ₆ . As the rare gas, one or more of helium, argon, neon, krypton, and xenon are used.

In addition, by using a rare gas such as helium, argon, neon, krypton, or xenon as a source gas for the first semiconductor layer 106, plasma is stabilized, and a deposition gas containing silicon or germanium, and hydrogen are dissociated. Promoted, increasing the amount of active species. For this reason, the reaction between the active species is promoted, and the deposition rate of the first semiconductor layer is increased. Further, when the deposition rate is increased, impurities in the treatment chamber are less likely to be taken in when the first semiconductor layer 106 is deposited, so that the amount of impurities contained in the first semiconductor layer 106 is reduced and the first semiconductor layer 106 is reduced. The crystallinity of the semiconductor layer 106 is increased. Therefore, the on-state current and field effect mobility of the thin film transistor can be increased, and the productivity of the thin film transistor can be increased.

In addition, when the first semiconductor layer 106 is formed, glow discharge plasma is generated from 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz HF band high frequency power, or more than 30 MHz to about 300 MHz. The high frequency power in the VHF band, typically 60 MHz, is applied. Further, it is performed by applying microwave high frequency power of 1 GHz or more. Note that the deposition rate can be increased by using high-frequency power in the VHF band or microwaves. Furthermore, by superimposing the high frequency power in the HF band and the high frequency power in the VHF band, plasma nonuniformity can be reduced even in a large-area substrate, and uniformity can be increased, and the deposition rate can be increased. .

Note that before forming the first semiconductor layer 106, a deposition gas containing silicon or germanium can be introduced while the pressure in the processing chamber of the CVD apparatus is reduced, so that impurity elements in the processing chamber can be removed. Alternatively, hydrogen can be introduced to remove the impurity element in the treatment chamber. Alternatively, a deposition gas containing silicon or germanium and hydrogen can be introduced to remove impurity elements in the treatment chamber. The impurity element in the treatment chamber is removed before the first semiconductor layer 106 is formed, so that the impurity element at the interface between the first silicon oxide layer 105 and the first semiconductor layer 106 of a thin film transistor to be formed later is reduced. It is possible to improve the electrical characteristics of the thin film transistor.

Here, the influence of the base layer on forming the microcrystalline silicon layer as the first semiconductor layer 106 on the crystallinity of the microcrystalline silicon layer is described below.

The crystallization process of Si in the case of containing an impurity element (N atom or O atom) was analyzed by classical molecular dynamics calculation. In the classical molecular dynamics method, the force acting on each atom is evaluated by defining the empirical potential that characterizes the interaction between atoms. By applying classical mechanics laws to each atom and numerically solving Newton's equation of motion, the motion (time evolution) of each atom can be traced deterministically.

Here, in order to investigate the state of Si crystal growth after the generation of Si crystal nuclei in the a-Si layer, as shown in FIG. The calculation model in the case of including an element (N atom, O atom) is shown.

FIG. 2A shows a model in which a crystal nucleus 141 is generated in a-Si not containing an impurity element, and single crystal silicon having a plane orientation (100) is grown from the crystal nucleus 141.

In FIG. 2B, a crystal nucleus 141 is generated in a-Si containing N atom 145 of 0.5 atom% and about 2.5 × 10 ²⁰ cm ⁻³ as an impurity element. The model by which single crystal silicon of orientation (100) grows is shown.

In FIG. 2C, a crystal nucleus 141 is generated in a-Si containing 0.5 atom% of O atoms 147 of about 0.5 × 10 ²⁰ cm ⁻³ as an impurity, and the plane orientation (100 ) Model of single crystal silicon growth.

In the above three calculation models shown in FIG. 2, classical molecular dynamics simulation was performed at 1025 ° C.

FIG. 3 shows the structure change by the simulation of FIG. Specifically, the model at 0 second is shown in FIG. 3A, the model at 0.525 seconds at 1025 ° C. is shown in FIG. 3B, and the model at 125 seconds at 1025 ° C. is shown in FIG. .

FIG. 4 shows the structure change by the simulation of FIG. Specifically, FIG. 4A shows a model at 0 second, FIG. 4B shows a model at 125 seconds at 1025 ° C., and FIG. 4C shows a model at 2n seconds at 1025 ° C.

FIG. 5 shows a structure change by the simulation of FIG. Specifically, FIG. 5A shows a model at 0 second, FIG. 5B shows a model at 0.525 seconds at 1025 ° C., and FIG. 5C shows a model at 1 n seconds at 1025 ° C. .

Table 1 shows the Si crystal growth rate of each calculation model.

The crystal nucleus 141 shown in FIG. 3A extends to the single crystal silicon growth region 151a shown in FIG. 3B and the single crystal silicon growth region 151b shown in FIG. 3C. From the above, it can be seen that when the a-Si layer does not contain an impurity element, Si 143 is crystal-grown.

However, in the case where N atoms are included in the a-Si layer, the crystal nucleus 141 shown in FIG. 4A becomes a single crystal silicon growth region 153a shown in FIG. 4B and the single crystal shown in FIG. It can be seen that the growth region extends to the crystal silicon growth region 153b, but the crystal growth region is narrower and the crystal growth rate is slower than in the case where the impurity element shown in FIG. 3 is not included. As shown in FIGS. 4B and 4C, when N atoms 145 are present in the a-Si layer, crystal growth is inhibited, and N atoms 145 are formed in the single crystal silicon growth regions 153a and 153b. It can be seen that it is not taken in and exists in the vicinity of the grain boundary.

In addition, in the case where the a-Si layer includes O atoms 147, the crystal nucleus 141 illustrated in FIG. 5A has a single crystal silicon growth region 155a illustrated in FIG. 5B and illustrated in FIG. Although the growth region extends to the single crystal silicon growth region 155b, the crystal growth region is narrower and the crystal growth rate is slower than the case where the impurity element shown in FIG. 3 is not included. However, compared with the case where N atom 145 shown in FIG. 4 is included, the crystal growth region is wide and the crystal growth rate is high. Furthermore, as shown in FIG. 5C, it can be seen that the O atoms 147 are taken into the growth region 155b of single crystal silicon, and the crystallinity of the entire film is relatively good. Therefore, even if the concentration of O contained in the film is high to some extent, the crystallinity of Si is not significantly affected, but if the N concentration is high, the crystallinity of Si is considered to be low.

Next, Table 2 shows bond distances of Si—Si, Si—N, and Si—O in single crystal silicon, SiN, and SiO _2, respectively.

FIG. 20 shows a schematic diagram in which the local structure of each calculation model is drawn two-dimensionally. 20A is a schematic diagram of the single crystal silicon shown in FIG. 3C, and FIG. 20B is a schematic diagram of a region having N atoms in the silicon shown in FIG. 4C. FIG. 20C is a schematic view of a region having O atoms in silicon in FIG.

In single-crystal silicon, both N and O atoms are interstitial impurities, but N atoms are tricoordinate and the Si—N bond distance is longer than the Si—O bond distance, and distortion is likely to occur in Si. For this reason, it is considered that N atoms suppress crystallization of silicon more than O atoms. On the other hand, since the O atom is two-coordinate and the Si—O bond distance is shorter than the Si—N bond distance, it is easy to interrupt between the Si—Si bonds, and even when Si—O—Si is formed, it is relatively distorted. Is small. FIG. 20D is a diagram in which O atoms which are impurities are bonded to each other in Si—Si bonds in single crystal silicon having a <111> structure. Impurity O atoms occupy interstitial positions in single-crystal silicon, and are in the form of interrupting between <111> Si—Si bonds.

From the above, it is considered that the strain caused by the coordination number and the bond distance with Si causes N atoms to reduce crystallinity of silicon rather than interstitial impurities of O atoms.

Accordingly, a silicon oxide layer with a low nitrogen content is formed using a deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen as a base layer of the microcrystalline semiconductor layer as in this embodiment mode. By forming, the crystallinity of the microcrystalline semiconductor layer can be increased.

Next, as illustrated in FIG. 1C, a second semiconductor layer is deposited over the first semiconductor layer 106, and the third semiconductor layer 106 and the second semiconductor layer are stacked. A semiconductor layer 107 is formed. Further, the impurity semiconductor layer 109 is formed over the third semiconductor layer 107, the conductive layer 111 is formed over the impurity semiconductor layer 109, and the resist mask 113 is formed over the conductive layer 111.

Here, the first semiconductor layer 106 is used as a seed crystal, and the second semiconductor layer is formed under the condition of partial crystal growth. Note that a deposition gas containing silicon or germanium, a gas containing hydrogen, and a gas containing nitrogen are mixed in a treatment chamber of a plasma CVD apparatus and formed by glow discharge plasma. Examples of the gas containing nitrogen include ammonia, nitrogen, nitrogen fluoride, nitrogen chloride, and the like.

At this time, a flow rate ratio between a deposition gas containing silicon or germanium and hydrogen is a flow rate ratio for forming a microcrystalline semiconductor layer similarly to the first semiconductor layer 106, and a gas containing nitrogen is used as a source gas. Thus, the crystal growth can be reduced more than the film formation conditions of the first semiconductor layer 106.

Here, as a typical example of the conditions for forming the microcrystalline semiconductor layer, the flow rate of hydrogen is 10 to 2000 times, preferably 50 to 200 times that of the deposition gas containing silicon or germanium.

In addition, a deposition gas can be increased by introducing a rare gas such as helium, argon, neon, krypton, or xenon into the source gas of the second semiconductor layer.

Note that when a rare gas such as helium, argon, neon, krypton, or xenon is introduced into the source gas of the second semiconductor layer, the crystallinity of the second semiconductor layer is increased, and the off current of the thin film transistor is reduced. Therefore, it is preferable to control the mixing ratio of the deposition gas containing silicon or germanium, the gas containing hydrogen, and the gas containing nitrogen. Typically, by increasing the deposition gas containing silicon or germanium with respect to hydrogen, which is a condition for increasing the amorphous property, the mixed layer 107b and the layer 107c containing an amorphous semiconductor have non-crystallinity and non-crystallinity. It is possible to control the crystallinity.

In the initial stage of deposition of the second semiconductor layer, a microcrystalline semiconductor layer is deposited on the first semiconductor layer 106 using the first semiconductor layer 106 as a seed crystal (initial stage of deposition). Thereafter, the crystal growth is partially suppressed, and a conical microcrystalline semiconductor region grows (mid-deposition stage). Furthermore, crystal growth of the conical microcrystalline semiconductor region is suppressed, and a layer containing an amorphous semiconductor is formed (late deposition).

Accordingly, in the third semiconductor layer 107 illustrated in FIGS. 1C and 6A, the microcrystalline semiconductor layer 107a in contact with the silicon oxide layer 105 is formed using the first semiconductor layer 106 and the second semiconductor layer 106. This corresponds to a microcrystalline semiconductor layer formed in the initial stage of layer deposition.

In addition, in the third semiconductor layer 107 illustrated in FIGS. 1C and 6A, the mixed layer 107b includes a conical microcrystalline semiconductor region 108a formed in the middle stage of deposition of the second semiconductor layer, and This corresponds to the amorphous semiconductor region 108b filling the gap.

In addition, in the third semiconductor layer 107 illustrated in FIGS. 1C and 6A, the layer 107c containing an amorphous semiconductor is formed using an amorphous semiconductor formed later in the deposition of the second semiconductor layer. Corresponds to the containing layer.

The microcrystalline semiconductor layer 107a is formed using a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, is a crystalline semiconductor having a short-range order and lattice distortion, and has a crystal grain size of 2 nm to 200 nm, preferably 10 nm. Columnar crystals or needle-like crystals having a thickness of 80 nm or more and more preferably 20 nm or more and 50 nm or less grow in the normal direction with respect to the substrate surface. For this reason, a crystal grain boundary may be formed at the interface between the columnar crystal or the needle crystal.

Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has a Raman spectrum shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, neon, krypton, or xenon to further promote lattice distortion, a stable microcrystalline semiconductor with improved stability can be obtained. A description of such a microcrystalline semiconductor is disclosed in, for example, US Pat. No. 4,409,134.

The layer 107c containing an amorphous semiconductor has an amorphous structure with few defects and high order. The layer 107c containing an amorphous semiconductor has nitrogen, an NH group, or an NH ₂ group. At this time, the concentration of nitrogen is 1 × 10 ²⁰ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ , preferably 2 × 10 ²⁰ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less. Furthermore, in addition to the amorphous structure, crystal grains having a grain size of 1 nm to 10 nm, preferably 1 nm to 5 nm may be included. Here, the layer containing an amorphous semiconductor is formed using a material in which a flow rate ratio between a deposition gas containing silicon or germanium and hydrogen is the same as that of the first semiconductor layer 106 to form a microcrystalline semiconductor layer. It can be formed by using a gas containing nitrogen as the gas. Here, the layer containing an amorphous semiconductor is a semiconductor layer having a small energy at the Urbach edge and a steep inclination of the level tail in the band gap when measured by CPM or low-temperature LP. . That is, the semiconductor layer has few defects and high order. Such a layer containing an amorphous semiconductor has a steep inclination of the level tail at the band edge of the electron band, so that the band gap becomes wide and the tunnel current hardly flows. As a result, the off-state current of the thin film transistor can be reduced.

Note that the amorphous semiconductor of the layer 107c containing an amorphous semiconductor is typically amorphous silicon.

As illustrated in FIG. 6A, the mixed layer 107b is provided between the microcrystalline semiconductor layer 107a and the layer 107c containing an amorphous semiconductor. The mixed layer 107b includes a microcrystalline semiconductor region 108a and an amorphous semiconductor region 108b filled between the microcrystalline semiconductor region 108a. Specifically, a microcrystalline semiconductor region 108a extending in a convex shape from the microcrystalline semiconductor layer 107a and an amorphous semiconductor region 108b formed using the same semiconductor as the layer 107c containing an amorphous semiconductor are formed. .

By forming the layer 107c containing an amorphous semiconductor with a highly ordered semiconductor layer with few defects and a steep inclination of the level tail at the band edge of the valence band, the off-state current of the thin film transistor Can be reduced. In addition, since the mixed layer 107b includes the conical microcrystalline semiconductor region 108a, resistance in the vertical direction (film thickness direction), that is, resistance between the mixed layer 107b and the source region or the drain region can be reduced. It is possible to increase the on-state current of the thin film transistor.

Note that the microcrystalline semiconductor region 108a included in the mixed layer 107b is substantially the same semiconductor as the microcrystalline semiconductor layer 107a, and the amorphous semiconductor region 108b included in the mixed layer 107b is a layer 107c containing an amorphous semiconductor. It is a semiconductor of almost the same quality. Therefore, the interface between the microcrystalline semiconductor layer and the layer containing an amorphous semiconductor corresponds to the interface between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b in the mixed layer 107b. It can be said that the interface of the layer containing a crystalline semiconductor is uneven.

As shown in FIG. 6B, the mixed layer 107b is provided between the microcrystalline semiconductor layer 107a and the impurity semiconductor layer 109, and an amorphous semiconductor is interposed between the mixed layer 107b and the impurity semiconductor layer 109. There is a case where the layer 107c containing is not formed. In such a case, in the structure illustrated in FIG. 6B, the ratio of the microcrystalline semiconductor region 108a to the amorphous semiconductor region 108b is preferably low. As a result, the off-state current of the thin film transistor can be reduced. Further, in the mixed layer 107b, resistance in the vertical direction (film thickness direction), that is, resistance between the third semiconductor layer 107 and the source region or the drain region can be reduced, and the on-state current of the thin film transistor can be reduced. It is possible to increase.

The microcrystalline semiconductor region 108a is a convex microcrystalline semiconductor with a tip narrowed from the silicon oxide layer 105 toward the layer 107c containing an amorphous semiconductor. Note that a convex microcrystalline semiconductor whose width increases from the silicon oxide layer 105 toward the layer 107c containing an amorphous semiconductor may be used.

In the mixed layer 107b, in the case where the microcrystalline semiconductor region 108a is a convex crystal grain with a tip narrowed from the silicon oxide layer 105 to the layer 107c containing an amorphous semiconductor, the microcrystalline semiconductor layer 107a side is more The ratio of the microcrystalline semiconductor region is higher than that of the amorphous semiconductor-containing layer 107c side. This is because the microcrystalline semiconductor region 108a grows in the film thickness direction from the surface of the microcrystalline semiconductor layer 107a, but the source gas contains a gas containing nitrogen or the source gas contains a gas containing nitrogen, When the flow rate of hydrogen with respect to silane is reduced according to the deposition conditions of the microcrystalline semiconductor film, the growth of crystal grains in the microcrystalline semiconductor region 108a is suppressed to become cone-shaped crystal grains, and only a layer including an amorphous semiconductor is eventually formed. This is because of deposition.

The mixed layer 107b includes nitrogen, typically an NH group or an NH ₂ group. This is because nitrogen, typically an NH group or an NH ₂ group, is formed of silicon atoms at an interface between crystal grains included in the microcrystalline semiconductor region 108a and an interface between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b. This is because defects are reduced when combined with dangling bonds. Therefore, dangling of silicon atoms is achieved by setting nitrogen to 1 × 10 ²⁰ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ , preferably 2 × 10 ²⁰ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ^3. The ring bond is easily cross-linked with nitrogen, preferably with an NH group, and the carrier flows easily. Alternatively, the dangling bonds of the semiconductor atoms at the interface described above are terminated with NH ₂ groups, and the defect level disappears. As a result, resistance in the vertical direction (thickness direction) when a voltage is applied between the source electrode and the drain electrode in the on state is reduced. That is, the field effect mobility and the on-current of the thin film transistor are increased.

In addition, by reducing the oxygen concentration in the mixed layer 107b, the bond that hinders the movement of carriers at the interface between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b or the interface between the microcrystalline semiconductor regions 108a can be reduced. Can do.

Note that here, the microcrystalline semiconductor layer 107a refers to a region having substantially the same thickness. The interface between the microcrystalline semiconductor layer 107a and the mixed layer 107b is a region obtained by extending a region closest to the silicon oxide layer 105 in a flat portion at the interface between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b. . Note that a straight dashed line between the microcrystalline semiconductor layer 107a and the mixed layer 107b and a straight dashed line between the mixed layer 107b and the layer 107c containing an amorphous semiconductor indicate respective interfaces. In actuality, the interface between the microcrystalline semiconductor layer 107a and the mixed layer 107b and the interface between the mixed layer 107b and the layer 107c containing an amorphous semiconductor are unclear.

The total thickness of the microcrystalline semiconductor layer 107a and the mixed layer 107b, that is, the distance from the interface of the silicon oxide layer 105 to the tip of the convex portion of the mixed layer 107b is 3 nm to 80 nm, preferably 5 nm to 30 nm. Thus, the off-state current of the thin film transistor can be reduced.

Further, by using a deposition gas containing silicon or germanium as a source gas for the second semiconductor layer and a gas containing nitrogen together with hydrogen, the mixed layer 107b and the crystallinity of the layer 107c containing an amorphous semiconductor are used. It is possible to control the amorphousness.

Next, the impurity semiconductor layer 109 is formed over the third semiconductor layer 107. The impurity semiconductor layer 109 is formed by glow discharge plasma in a processing chamber of a plasma CVD apparatus by mixing a deposition gas containing silicon or germanium, hydrogen, and phosphine (hydrogen dilution or silane dilution). A deposition gas containing silicon or germanium is diluted with hydrogen, and amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, amorphous silicon germanium to which phosphorus is added, and microcrystalline silicon germanium to which phosphorus is added Amorphous germanium to which phosphorus is added, microcrystalline germanium to which phosphorus is added, and the like are formed.

Further, a rare gas such as helium, argon, neon, krypton, or xenon can be introduced into the source gas of the impurity semiconductor layer 109 to increase the deposition rate.

Note that in the case where the third semiconductor layer 107 and the source and drain electrodes 125 to be formed later are in ohmic contact, the impurity semiconductor layer 109 is not necessarily formed.

A process from formation of the insulating layer 104 containing nitrogen to formation of the impurity semiconductor layer will be described below with reference to a time chart shown in FIG.

First, deposition of silicon nitride is performed to form a silicon nitride layer as an insulating layer containing nitrogen while heating the substrate over which the gate electrode 103 is formed in the treatment chamber 241 of the CVD apparatus described in Embodiment 2. The material gas used for the process is introduced into the process chamber 241 (preliminary process 201 in FIG. 7). Here, as an example, the flow rate of SiH ₄ is 40 sccm, the flow rate of H ₂ is 500 sccm, the flow rate of N ₂ is 550 sccm, the flow rate of NH ₃ is 140 sccm, the material gas is introduced and stabilized, and the pressure in the processing chamber is 100 Pa, The substrate temperature is set to 280 ° C., and plasma discharge is performed with an output of 370 W, thereby forming a silicon nitride layer of about 110 nm. Note that the source gas for the silicon nitride layer may be at least NH ₃ or N ₂ in addition to SiH ₄ .

Thereafter, only the supply of SiH ₄ is stopped, and after several seconds (here, 5 seconds), plasma discharge is stopped (SiN formation 203 in FIG. 7). This is because if the plasma discharge is stopped in a state where SiH ₄ exists in the processing chamber, a granular material or a powdery material containing silicon as a main component is formed, which causes a decrease in yield.

Next, the material gas used for depositing the silicon nitride layer is exhausted, and the material gas used for depositing the silicon oxide layer is introduced into the processing chamber 241 (gas replacement 205 in FIG. 7). Here, as an example, the flow rate of SiH ₄ is 10 sccm, the flow rate of N ₂ O is 800 sccm, the flow rate of H ₂ is 1500 sccm, the material gas is introduced and stabilized, the pressure in the processing chamber is 280 Pa, and the temperature of the substrate is By performing plasma discharge at 280 ° C. and an output of 50 W, a silicon oxide layer of about 110 nm is formed. Thereafter, similarly to the silicon nitride layer, only the supply of SiH ₄ is stopped, and after a few seconds (here, 5 seconds), plasma discharge is stopped (SiO 2 formation 207 in FIG. 7).

Through the above steps, the silicon oxide layer 105 with reduced nitrogen content can be formed. After the silicon oxide layer 105 is formed, the substrate 101 is unloaded from the processing chamber 241 (unload 225 in FIG. 7).

After unloading the substrate 101 from the processing chamber 241, for example, NF ₃ gas is introduced into the processing chamber 241 to clean the inside of the processing chamber 241 (cleaning process 227 in FIG. 7). After that, a process for forming an amorphous silicon layer in the process chamber 241 is performed (precoat process 229 in FIG. 7). By this treatment, an amorphous silicon layer is formed on the inner wall of the treatment chamber 241. After that, the substrate 101 is carried into the processing chamber 241 (load 231 in FIG. 7).

Next, a material gas used for deposition of the first semiconductor layer 106 is introduced into the treatment chamber 241 (gas replacement 209 in FIG. 7). Next, the first semiconductor layer 106 is formed over the silicon oxide layer 105. Here, as an example, the flow rate of SiH ₄ is 10 sccm, the flow rate of H ₂ is 1500 sccm, the flow rate of Ar is 1500 sccm, the material gas is introduced and stabilized, the pressure in the processing chamber is 280 Pa, the substrate temperature is 280 ° C., By performing plasma discharge with an output of 50 W, a microcrystalline silicon layer with a thickness of about 5 nm can be formed as the first semiconductor layer 106. Thereafter, similarly to the formation of the silicon nitride layer and the like described above, only the supply of SiH ₄ is stopped, and after several seconds (here, 5 seconds), plasma discharge is stopped (formation of the first semiconductor layer in FIG. 7). 211).

Thereafter, these gases are exhausted, and a gas used for depositing the second semiconductor layer is introduced (gas replacement 215 in FIG. 7).

Next, a second semiconductor layer is formed, and a third semiconductor layer 107 in which the first semiconductor layer 106 and the second semiconductor layer are stacked is formed. Here, as an example, the flow rate of SiH ₄ is 30 sccm, the flow rate of H ₂ is 1425 sccm, the flow rate of 1000 ppm NH ₃ (hydrogen dilution) is 25 sccm, the material gas is introduced and stabilized, the pressure in the processing chamber is 280 Pa, the substrate The temperature is set to 280 ° C., plasma discharge is performed by the output of RF power frequency of 13.56 MHz and the power of the RF power source of 50 W to form a second semiconductor layer of about 150 nm. Specifically, a microcrystalline semiconductor layer 107a, a mixed layer 107b, and a layer 107c containing an amorphous semiconductor are formed. In this process, ammonia is dissociated by plasma discharge to generate NH groups or NH ₂ groups. Or, N is eliminated. Therefore, the third semiconductor layer 107 contains nitrogen. Furthermore, an NH group or an NH ₂ group is included. Therefore, when the second semiconductor layer is deposited, dangling bonds are bridged or terminated, and the defect level can be reduced (second semiconductor layer formation 217 in FIG. 7).

Note that as the gas containing nitrogen in the treatment chamber, nitrogen gas may be flowed in the second semiconductor layer formation 217 instead of ammonia as indicated by a broken line 232. Alternatively, ammonia and nitrogen gas may be flowed. As a result, the third semiconductor layer 107 contains nitrogen. Furthermore, an NH group or an NH ₂ group is included. Therefore, dangling bonds in the third semiconductor layer 107 are cross-linked with NH groups, and the defect level is reduced. Alternatively, dangling bonds in the semiconductor layer 107 are terminated with NH ₂ groups, and the defect level is reduced.

In the third semiconductor layer 107 formed by such a method, the nitrogen concentration measured by secondary ion mass spectrometry is higher than the microcrystalline semiconductor layer 107a or between the microcrystalline semiconductor layer 107a and the mixed layer 107b. A constant concentration is exhibited from the vicinity of the interface to the interface of the impurity semiconductor layer. Note that there may be a peak concentration above the microcrystalline semiconductor layer 107a or in the vicinity of the interface between the microcrystalline semiconductor layer 107a and the mixed layer 107b.

In the second semiconductor layer formation 217, a rare gas may be used as a source gas as indicated by a broken line 234. As a result, the growth rate of the second semiconductor layer can be increased.

After that, these gases are exhausted, and a gas used for depositing the impurity semiconductor layer 109 is introduced (gas replacement 219 in FIG. 7).

Next, the impurity semiconductor layer 109 is formed over the entire surface of the third semiconductor layer 107. The impurity semiconductor layer 109 is formed into a pattern in a later step and becomes a source region and a drain region 127. First, a material gas used for deposition of the impurity semiconductor layer 109 is introduced into the treatment chamber 241. Here, as an example, the material gas is introduced and stabilized by setting the flow rate of SiH ₄ to 100 sccm and the flow rate of the mixed gas obtained by diluting PH ₃ to 0.5 vol% with H ₂ to 170 sccm. An amorphous silicon layer containing phosphorus of about 50 nm can be formed by performing a plasma discharge with an output of 60 W at a pressure in the treatment chamber 241 of 280 Pa and a substrate temperature of 280 ° C. Thereafter, similarly to the above-described formation of silicon nitride or the like, only the supply of SiH ₄ is stopped, and after several seconds (here, 5 seconds), plasma discharge is stopped (impurity semiconductor layer formation 221 in FIG. 7). Thereafter, these gases are exhausted (exhaust 223 in FIG. 7).

As described above, up to the impurity semiconductor layer 109 can be formed.

After that, the source gas of the impurity semiconductor layer 109 is exhausted (exhaust 223 in FIG. 7).

The conductive layer 111 can be formed as a single layer or a stacked layer using aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, or the like. Alternatively, an aluminum alloy to which a hillock preventing element is added (typically, an Al—Nd alloy that can be used for the gate electrode 103) may be used. Alternatively, crystalline silicon to which an impurity element which serves as a donor is added may be used. The layer on the side in contact with the crystalline silicon to which the impurity element to be a donor is added is formed of titanium, tantalum, molybdenum, tungsten, or nitride of these elements, and a laminated structure in which aluminum or an aluminum alloy is formed thereon Also good. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. For example, the conductive layer 121 may have a stacked structure in which an aluminum layer is sandwiched between titanium nitride layers.

The conductive layer 111 is formed by a CVD method, a sputtering method, or a vacuum evaporation method. Alternatively, the conductive layer 111 may be formed by discharging and baking a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like.

Next, a resist mask is formed over the conductive layer 111 by a photolithography process. The resist mask 113 has regions with different thicknesses. Such a resist mask can be formed using a multi-tone mask. It is preferable to use a multi-tone mask because the number of photomasks to be used is reduced and the number of manufacturing steps is reduced. In this embodiment, a multi-tone mask can be used in the step of forming the pattern of the third semiconductor layer 107 and the step of separating the source region and the drain region.

A multi-tone mask is a mask that can be exposed with multiple levels of light, and typically, exposure is performed with three levels of light: an exposed area, a half-exposed area, and an unexposed area. By using a multi-tone mask, a resist mask having a plurality of thicknesses (typically two types) can be formed by one exposure and development process. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

8A-1 and 8B-1 are cross-sectional views of typical multi-tone masks. 8A-1 shows a gray tone mask 180, and FIG. 8B-1 shows a halftone mask 185. FIG.

A gray-tone mask 180 illustrated in FIG. 8A-1 includes a light-blocking portion 182 formed using a light-blocking layer over a light-transmitting substrate 181 and a diffraction grating portion 183 provided using a pattern of the light-blocking layer. ing.

The diffraction grating unit 183 controls the light transmittance by having slits, dots, meshes, or the like provided at intervals equal to or less than the resolution limit of light used for exposure. Note that the slits, dots, or mesh provided in the diffraction grating portion 183 may be periodic or non-periodic.

As the substrate 181 having a light-transmitting property, quartz or the like can be used. The light shielding layer constituting the light shielding portion 182 and the diffraction grating portion 183 may be formed using metal, and is preferably provided with chromium, chromium oxide, or the like.

When the graytone mask 180 is irradiated with light for exposure, as shown in FIG. 8A-2, the light transmittance in the region overlapping the light shielding portion 182 becomes 0%, and the light shielding portion 182 or the diffraction grating portion. The transmissivity in the region where 183 is not provided is 100%. Further, the light transmittance in the diffraction grating portion 183 is generally in the range of 10 to 70%, and can be adjusted by the interval of slits, dots or meshes of the diffraction grating.

A halftone mask 185 illustrated in FIG. 8B-1 includes a semi-transmissive portion 187 formed using a semi-transmissive layer over a light-transmitting substrate 186 and a light-blocking portion 188 formed using a light-blocking layer. Has been.

The semi-translucent portion 187 can be formed using a layer of MoSiN, MoSi, MoSiO, MoSiON, CrSi or the like. The light shielding portion 188 may be formed using the same metal as the light shielding layer of the gray tone mask, and is preferably provided with chromium, chromium oxide, or the like.

When the exposure light is irradiated to the halftone mask 185, the light transmittance in the region overlapping with the light shielding portion 188 is 0% as shown in FIG. The light transmittance in the region where the portion 187 is not provided is 100%. The translucency in the semi-translucent portion 187 is approximately in the range of 10 to 70%, and can be adjusted by the type of material to be formed, the film thickness to be formed, or the like.

By performing exposure and development using a multi-tone mask, a resist mask having regions with different thicknesses can be formed.

Next, the third semiconductor layer 107, the impurity semiconductor layer 109, and the conductive layer 111 are etched using the resist mask 113. Through this step, the third semiconductor layer 107, the impurity semiconductor layer 109, and the conductive layer 111 are separated for each element, and the third semiconductor layer 115, the impurity semiconductor layer 117, and the conductive layer 119 are formed. Note that the third semiconductor layer 115 includes a microcrystalline semiconductor layer 115a, a mixed layer 115b, and a layer 115c containing an amorphous semiconductor (see FIG. 1D).

Next, the resist mask 113 is moved backward to form a separated resist mask 123. For the receding of the resist mask, ashing using oxygen plasma may be used. Here, the resist mask 123 can be formed by ashing the resist mask 113 so as to be separated over the gate electrode (see FIG. 9A).

Next, the conductive layer 119 is etched using the resist mask 123 to form a source electrode and a drain electrode 125 (see FIG. 9B). For the etching of the conductive layer 119, wet etching is preferably used. The conductive layer is isotropically etched by wet etching. As a result, the conductive layer recedes inward from the resist mask 123, and the source and drain electrodes 125 are formed. The source or drain electrode 125 functions as a signal line as well as the source or drain electrode. However, the present invention is not limited to this, and the signal line, the source electrode, and the drain electrode may be provided separately.

Next, part of the layer 115 c containing an amorphous semiconductor and the impurity semiconductor layer 117 are etched using the resist mask 123. Here, dry etching is used. Up to this step, a layer 129a including an amorphous semiconductor having a depression on the surface, a source region, and a drain region 127 are formed. After that, the resist mask 123 is removed (see FIG. 9C).

Note that here, the conductive layer 119 is wet-etched, and part of the layer 115c containing an amorphous semiconductor and the impurity semiconductor layer 117 are dry-etched, so that the conductive layer 119 is isotropically etched, so that the source electrode and The side surfaces of the drain electrode 125 and the side surfaces of the source region and the drain region 127 do not coincide with each other, and the side surfaces of the source region 1 and the drain region 127 are formed outside the side surfaces of the source electrode and the drain electrode 125.

In addition, the conductive layer 119 is etched, the source and drain electrodes 125 are formed, the third resist mask 123 is removed, and then part of the impurity semiconductor layer 117 and the layer 115c containing an amorphous semiconductor is etched. Also good. From this etching, the impurity semiconductor layer 117 is etched using the source and drain electrodes 125, so that the end portions of the source electrode and the source region are approximately aligned. Further, the end portions of the drain electrode and the drain region are approximately coincident.

Next, dry etching may be performed. The dry etching is performed under such a condition that the exposed layer 129c containing an amorphous semiconductor is not damaged and the etching rate for the layer 129c containing an amorphous semiconductor is low. That is, a condition is used in which the surface of the exposed layer 129c containing an amorphous semiconductor is hardly damaged and the thickness of the exposed layer 129c containing an amorphous semiconductor is hardly reduced. As an etching gas, typically Cl ₂ , CF ₄ , N _2, or the like is used. The etching method is not particularly limited, and an inductively coupled plasma (ICP) method, a capacitively coupled plasma (CCP) method, an electron cyclotron resonance (ECR) method is used. Alternatively, a reactive ion etching (RIE) method or the like can be used.

Next, the surface of the layer 129c containing an amorphous semiconductor may be irradiated with water plasma, ammonia plasma, nitrogen plasma, or the like.

The water plasma treatment can be performed by introducing a gas containing water as a main component typified by water vapor (H ₂ O vapor) into the reaction space to generate plasma.

As described above, after the source region and the drain region 127 are formed, further dry etching is performed under a condition that does not damage the layer 129c containing the amorphous semiconductor, so that the layer 129c containing the exposed amorphous semiconductor is obtained. Impurities such as residues present on the top can be removed. Further, by performing water plasma treatment subsequent to dry etching, the resist mask residue can be removed. By performing the water plasma treatment, insulation between the source region and the drain region can be ensured, off-state current of a completed thin film transistor can be reduced, and variation in electrical characteristics can be reduced.

Through the above process, a thin film transistor with a small number of masks, a low off-state current, a high on-state current and high field-effect mobility can be manufactured with high productivity.

(Embodiment 2)
In this embodiment, one embodiment of a plasma CVD apparatus which can be used for forming the insulating layer 104 containing nitrogen, the silicon oxide layer 105, the first semiconductor layer 106, the second semiconductor layer, and the impurity semiconductor layer 109. Will be described in detail.

A plasma CVD apparatus 261 shown in FIG. 10 is connected to a gas supply means 250 and an exhaust means 251.

A plasma CVD apparatus 261 illustrated in FIG. 10 includes a processing chamber 241, a stage 242, a gas supply unit 243, a shower plate 244, an exhaust port 245, an upper electrode 246, a lower electrode 247, an AC power source 248, A temperature control unit 249.

The processing chamber 241 is formed of a rigid material and is configured so that the inside can be evacuated. The processing chamber 241 is provided with an upper electrode 246 and a lower electrode 247. Note that FIG. 10 shows a configuration of a capacitive coupling type (parallel plate type), but inductive coupling type may be used as long as it can generate plasma inside the processing chamber 241 by applying two or more different high frequency powers. Other configurations may be applied.

When processing is performed by the plasma CVD apparatus shown in FIG. The supplied gas is introduced into the processing chamber 241 through the shower plate 244. A high frequency power is applied by an AC power source 248 connected to the upper electrode 246 and the lower electrode 247 to excite the gas in the processing chamber 241 and generate plasma. Further, the gas in the processing chamber 241 is exhausted through the exhaust port 245 connected to the vacuum pump. In addition, the temperature control unit 249 can perform plasma treatment while heating the workpiece.

The gas supply means 250 includes a cylinder 252 filled with a reaction gas, a pressure adjustment valve 253, a stop valve 254, a mass flow controller 255, and the like. In the processing chamber 241, a shower plate is formed between the upper electrode 246 and the substrate 101 and processed into a plate shape and provided with a plurality of pores. The reaction gas supplied to the upper electrode 246 is supplied into the processing chamber 241 from the pores inside the upper electrode 246 having a hollow structure.

The exhaust unit 251 connected to the processing chamber 241 includes a function of controlling the vacuum chamber and a pressure so that the inside of the processing chamber 241 is maintained at a predetermined pressure when a reaction gas is allowed to flow. The configuration of the exhaust unit 251 includes a butterfly valve 256, a conductance valve 257, a turbo molecular pump 258, a dry pump 259, and the like. When the butterfly valve 256 and the conductance valve 257 are arranged in parallel, the butterfly valve 256 is closed and the conductance valve 257 is operated, thereby controlling the exhaust speed of the reaction gas so that the pressure in the processing chamber 241 is kept within a predetermined range. Can keep. Further, high vacuum evacuation is possible by opening the butterfly valve 256 having a large conductance.

Note that when the processing chamber 241 is evacuated to a pressure lower than 10 ⁻⁵ Pa, it is preferable to use a cryopump 260 in combination. In addition, when the ultimate vacuum is exhausted to an ultra-high vacuum, the inner wall of the processing chamber 241 may be mirror-finished, and a baking heater may be provided to reduce gas emission from the inner wall.

As shown in FIG. 10, when pre-coating treatment is performed so that a film covering the entire processing chamber 241 is formed (deposited), the impurity element attached to the inner wall of the processing chamber (chamber) or the processing chamber (chamber ) Impurity elements constituting the inner wall can be prevented from entering the device. In this embodiment mode, the precoating process may be performed by forming a layer containing silicon as a main component, for example, an amorphous silicon film or the like. However, it is preferable that this film does not contain oxygen.

(Embodiment 3)
In this embodiment, a process for forming a second semiconductor layer which can be applied to Embodiment 1 will be described.

In this embodiment mode, the processing chamber is cleaned before the second semiconductor layer is formed, and then the inner wall of the chamber is covered with a silicon nitride layer, so that the second semiconductor layer contains nitrogen. Since the formation method of the insulating layer 104 containing nitrogen and the formation method of the first semiconductor layer 106 are the same as those in Embodiment Mode 1, here, from the second semiconductor layer to the formation of the impurity semiconductor layer 109, FIG. This will be described below with reference.

A first semiconductor layer 106 is formed on the entire surface of the silicon oxide layer 105. First, a material gas used for deposition of the first semiconductor layer 106 is introduced into the treatment chamber. Here, as an example, a microcrystalline silicon layer with a thickness of about 5 nm is formed as the first semiconductor layer 106 by a method similar to that in Embodiment 1. Thereafter, plasma discharge is stopped (first semiconductor layer formation 211 in FIG. 11). Thereafter, the substrate 101 is unloaded from the processing chamber 241 (unload 225 in FIG. 11).

After the substrate 101 is unloaded from the processing chamber 241, for example, NF ₃ gas is introduced into the processing chamber 241 to clean the inside of the processing chamber 241 (cleaning process 227 in FIG. 11). Thereafter, a process of forming a silicon nitride layer in the process chamber 241 is performed (precoat process 233 in FIG. 11). As the silicon nitride layer, conditions similar to those of the silicon nitride layer formed using the gate insulating layer of Embodiment 1 are used. By this treatment, a silicon nitride layer is formed on the inner wall of the treatment chamber 241. Thereafter, the substrate 101 is carried into the processing chamber 241 (load 231 in FIG. 11).

Note that the cleaning process 227 may not be performed. As a result, throughput can be improved.

Next, a material gas used for deposition of the second semiconductor layer is introduced into the processing chamber 241 (gas replacement 215 in FIG. 11). Next, a second semiconductor layer is formed, and a first semiconductor layer 106 and a third semiconductor layer 107 stacked with the second semiconductor are formed. When the silicon nitride layer formed on the inner wall of the processing chamber is exposed to plasma, part of the silicon nitride is dissociated and NH groups or NH ₂ groups are generated. Or, N is eliminated. Therefore, the third semiconductor layer 107 contains nitrogen. Here, as in Embodiment Mode 1, a second semiconductor layer with a thickness of 150 nm is formed. Thereafter, plasma discharge is stopped (second semiconductor layer formation 217 in FIG. 11).

In the third semiconductor layer 107 formed by such a method, the nitrogen concentration measured by secondary ion mass spectrometry is higher than the microcrystalline semiconductor layer 107a or between the microcrystalline semiconductor layer 107a and the mixed layer 107b. Near the interface, it has a peak concentration and decreases with respect to the deposition direction of the third semiconductor layer 107.

Note that ammonia may be flowed into the processing chamber in the second semiconductor layer formation 217 as indicated by a broken line 237a in FIG. Alternatively, as indicated by a broken line 237b, nitrogen gas may be flowed instead of ammonia. Alternatively, ammonia and nitrogen gas may be flowed. As a result, nitrogen can be contained in the third semiconductor layer 107, dangling bonds in the third semiconductor layer 107 are bridged or terminated, and a defect level is reduced.

In the third semiconductor layer 107 formed by such a method, the nitrogen concentration measured by secondary ion mass spectrometry is higher than the microcrystalline semiconductor layer 107a or between the microcrystalline semiconductor layer 107a and the mixed layer 107b. In the vicinity of the interface, it has a peak concentration and becomes a constant concentration with respect to the deposition direction of the third semiconductor layer 107.

In the second semiconductor layer formation 217, a rare gas may be used as a source gas as indicated by a broken line 238. As a result, the growth rate of the second semiconductor layer can be increased.

After that, these gases are exhausted, and a gas used for depositing the impurity semiconductor layer 109 is introduced (gas replacement 219 in FIG. 11). Further, as in Embodiment 1, the impurity semiconductor layer 109 is formed (impurity semiconductor layer formation 221 in FIG. 11). After that, the source gas of the impurity semiconductor layer 109 is exhausted (exhaust 223 in FIG. 11).

In the present embodiment, ammonia introduced in the pre-coating process into the processing chamber is dissociated by plasma discharge and becomes NH groups or NH ₂ groups. Or, N is eliminated. Further, N is desorbed from the nitrogen gas. Further, by the plasma discharge, the nitrogen gas reacts with hydrogen gas, which is a raw material gas for a layer containing an amorphous semiconductor, to generate NH groups or NH ₂ groups. Further, when the silicon nitride layer formed on the inner wall of the processing chamber is exposed to plasma, part of the silicon nitride is dissociated to generate NH groups or NH ₂ groups. Or, N is eliminated.

In this embodiment mode, a gas containing nitrogen is supplied to the treatment chamber in which the second semiconductor layer is formed, and N is desorbed. Furthermore, NH groups or NH ₂ groups are generated. Therefore, by forming the second semiconductor layer in the treatment chamber supplied with a gas containing nitrogen, dangling bonds are cross-linked or terminated, and the defect level can be reduced.

Further, by covering the inner wall of the processing chamber with a silicon nitride layer immediately before forming the second semiconductor layer, it is possible to suppress the oxygen concentration to be low and to make the nitrogen concentration higher than the oxygen concentration. A layer containing a quality semiconductor can be formed.

Further, by covering the inner wall of the processing chamber with the silicon nitride layer, it is possible to prevent the elements constituting the inner wall of the processing chamber from being mixed into the second semiconductor layer.

Through the above process, a thin film transistor with low off-state current, high on-state current, and high field-effect mobility can be manufactured with high productivity.

(Embodiment 4)
In this embodiment, a process for forming a second semiconductor layer which can be applied to Embodiment 1 will be described.

In this embodiment mode, a gas containing nitrogen is supplied to the treatment chamber before the second semiconductor layer is formed. Since the formation method of the insulating layer 104 containing nitrogen and the formation method of the first semiconductor layer 106 are the same as those in Embodiment Mode 1, here, from the first semiconductor layer 106 to the formation of the impurity semiconductor layer 109, FIG. This will be described below with reference to FIG.

A first semiconductor layer 106 is formed over the entire surface of the insulating layer 104 containing nitrogen. First, a material gas used for deposition of the first semiconductor layer 106 is introduced into the treatment chamber. Here, as an example, a microcrystalline silicon layer with a thickness of about 5 nm is formed as the first semiconductor layer 106 by a method similar to that in Embodiment 1. Thereafter, plasma discharge is stopped (first semiconductor layer formation 211 in FIG. 12).

Next, nitrogen is supplied to the surface of the first semiconductor layer 106. Here, nitrogen is supplied by exposing the surface of the first semiconductor layer 106 to ammonia (here, referred to as flash processing) (flash processing 213 in FIG. 12). Ammonia may contain hydrogen as indicated by a broken line 235a. Alternatively, nitrogen may be introduced into the treatment chamber 241 instead of ammonia as indicated by a broken line 235b. Alternatively, ammonia and nitrogen may be introduced into the treatment chamber 241. Here, as an example, the pressure in the processing chamber 241 is approximately 20 Pa to 30 Pa, the substrate temperature is 280 ° C., and the processing time is 60 seconds. In the process of this step, the substrate 101 is only exposed to ammonia, but a plasma process may be performed. After that, these gases are exhausted, and a gas used for depositing the second semiconductor layer is introduced (gas replacement 215 in FIG. 12).

Next, a second semiconductor layer is formed, and a third semiconductor layer 107 in which the first semiconductor layer 106 and the second semiconductor layer are stacked is formed. Here, the second semiconductor layer is formed using a layer containing an amorphous semiconductor containing nitrogen. Here, as an example, the material gas is introduced and stabilized with a flow rate of SiH ₄ of 30 sccm and a flow rate of H ₂ of 1500 sccm, the pressure in the processing chamber is 280 Pa, the temperature of the substrate is 280 ° C., and the RF power supply frequency is 13.56 MHz. The second semiconductor layer having a thickness of about 150 nm can be formed by performing plasma discharge with an output of power of 50 W from the RF power source.

In the step of forming the second semiconductor layer, ammonia introduced into the processing chamber by the flash process is decomposed by plasma discharge, and NH groups or NH ₂ groups are generated. Or, N is eliminated. Further, when the second semiconductor layer is deposited, dangling bonds are cross-linked or terminated, so that the defect level can be reduced. Note that in the case where nitrogen gas is introduced into the treatment chamber as nitrogen-containing gas, N is desorbed by plasma discharge. Alternatively, the nitrogen gas reacts with hydrogen gas, which is a source gas for the second semiconductor layer, to generate an NH group or an NH ₂ group.

Thereafter, similarly to the formation of the silicon nitride layer and the like described above, only the supply of SiH ₄ is stopped, and after a few seconds (here, 5 seconds), plasma discharge is stopped (formation of the second semiconductor layer in FIG. 12). 217). After that, these gases are exhausted, and a gas used for depositing the impurity semiconductor layer 109 is introduced (gas replacement 219 in FIG. 12). Thereafter, the impurity semiconductor layer 109 is formed as in Embodiment 1 (impurity semiconductor layer formation 221 in FIG. 12).

Thereafter, the source gas of the impurity semiconductor layer 109 is exhausted (exhaust 223 in FIG. 12).

A gas containing nitrogen is supplied to the treatment chamber in which the second semiconductor layer is formed in this embodiment mode. In the gas containing nitrogen, NH groups or NH ₂ groups are formed by plasma discharge. Or, N is eliminated. For this reason, when the second semiconductor layer is deposited, the dangling bonds are bridged or terminated, and the defect level can be reduced.

In the third semiconductor layer 107 formed by such a method, the nitrogen concentration measured by secondary ion mass spectrometry has a peak concentration in the vicinity of the interface between the microcrystalline semiconductor layer 107a and the mixed layer 107b. The concentration decreases with respect to the deposition direction of the mixed layer 107b and the layer 107c containing an amorphous semiconductor.

Note that ammonia may be flowed into the processing chamber in the second semiconductor layer formation 217 as indicated by a broken line 236a in FIG. Alternatively, nitrogen gas may be flowed as shown by a broken line 236b instead of ammonia. Alternatively, ammonia and nitrogen gas may be flowed. As a result, the nitrogen concentration in the third semiconductor layer 107 is increased, dangling bonds included in the third semiconductor layer 107 are bridged or terminated, and the defect level is reduced.

In the third semiconductor layer 107 formed by such a method, the nitrogen concentration measured by secondary ion mass spectrometry is near the interface between the microcrystalline semiconductor layer 107a or the microcrystalline semiconductor layer 107a and the mixed layer 107b. And has a constant concentration with respect to the deposition direction of the mixed layer 107b and the layer 107c containing an amorphous semiconductor.

Further, in the second semiconductor layer formation 217, a rare gas may be used as a source gas as indicated by a broken line 236c. As a result, the growth rate of the second semiconductor layer can be increased.

Through the above process, a thin film transistor with low off-state current, high on-state current, and high field-effect mobility can be manufactured with high productivity.

(Embodiment 5)
In Embodiment Mode 1, a method for manufacturing the second semiconductor layer is described with reference to FIGS.

In this embodiment mode, as a method for forming the second semiconductor layer, in Embodiment 1, after the first semiconductor layer formation 211 processing step, a gas containing nitrogen is introduced into the processing chamber by the flash processing 213. During the formation of the second semiconductor layer, a gas containing nitrogen is again introduced into the processing chamber as shown by a solid line 239a (see FIG. 13). Here, ammonia is used as the nitrogen-containing gas. Instead of ammonia, nitrogen gas may be used as indicated by a broken line 239b. Alternatively, ammonia and nitrogen gas may be used. As a result, the nitrogen concentration increases and the defect level can be reduced during the initial deposition stage and during the deposition of the second semiconductor layer.

Alternatively, as a method for adding nitrogen, further an NH group or an NH ₂ group to the _second semiconductor layer, in Embodiment 3, after the first semiconductor layer 106 is formed, a silicon nitride layer is formed in the treatment chamber. In the middle of forming the second semiconductor layer, a gas containing nitrogen may be introduced again into the processing chamber. Here, ammonia is used as the nitrogen-containing gas. Nitrogen gas may be used instead of ammonia. Alternatively, ammonia and nitrogen gas may be used. As a result, the nitrogen concentration increases and the defect level can be reduced during the initial deposition stage and during the deposition of the second semiconductor layer.

Thereafter, the source gas of the impurity semiconductor layer 109 is exhausted (exhaust 223 in FIG. 13).

Through the above process, a thin film transistor with low off-state current, high on-state current, and high field-effect mobility can be manufactured with high productivity.

(Embodiment 6)
A method for manufacturing a thin film transistor, which is different from that in Embodiment 1, is described with reference to FIGS.

Similarly to Embodiment Mode 1, a gate electrode 103 is formed over the substrate 101. Next, an insulating layer 104 containing nitrogen that covers the gate electrode 103 is formed, a silicon oxide layer 105 is formed over the insulating layer 104 containing nitrogen in the same manner as in Embodiment 1, and the first layer is formed on the silicon oxide layer 105. The semiconductor layer 106 is formed. Next, as in Embodiment Mode 1, the second semiconductor layer is formed over the first semiconductor layer 106, and the third semiconductor layer 107 in which the first semiconductor layer 106 and the second semiconductor layer are stacked is formed. Form. Next, the impurity semiconductor layer 109 is formed over the second semiconductor layer. After that, a resist mask (not shown) is formed over the impurity semiconductor layer 109 (see FIG. 14A).

Next, the third semiconductor layer 107 and the impurity semiconductor layer 109 are etched using a resist mask. Through this step, the third semiconductor layer 107 and the impurity semiconductor layer 109 are separated for each element, a third semiconductor layer 115 (a microcrystalline semiconductor layer 115a, a mixed layer 115b, a layer 115c containing an amorphous semiconductor), and An impurity semiconductor layer 117 is formed (see FIG. 14B).

Next, a conductive layer 111 is formed over the silicon oxide layer 105, the third semiconductor layer 115, and the impurity semiconductor layer 117 (see FIG. 14C).

Next, a resist mask (not shown) is formed over the conductive layer 111, and the conductive layer 111 is etched using the resist mask to form a source electrode and a drain electrode 133 (see FIG. 15A). ).

Next, the impurity semiconductor layer 117 is etched using the source and drain electrodes 133 as masks to form source and drain regions 127. In addition, the layer 115c containing an amorphous semiconductor is etched to form a layer 129c containing an amorphous semiconductor having a recess. After that, the resist mask is removed (see FIG. 15B).

Through the above process, a thin film transistor can be manufactured.

Note that in this embodiment, after the source and drain electrodes 133 are formed, the resist mask is not removed and part of the layer 115c containing an amorphous semiconductor is etched; however, after the resist mask is removed, impurities Part of the semiconductor layer 117 and the layer 115c containing an amorphous semiconductor may be etched. In this etching, the impurity semiconductor layer 117 is etched using the source and drain electrodes 133, so that the end portions of the source electrode and the source region substantially coincide with each other. Further, the end portions of the drain electrode and the drain region are approximately coincident.

Note that the method for manufacturing the second semiconductor layer of Embodiments 3 to 5 can be applied as appropriate instead of the second semiconductor layer described in this embodiment.

(Embodiment 7)
In this embodiment, a manufacturing process of an inverted staggered thin film transistor in which the stacked structure of semiconductor layers is different from that in Embodiments 1 to 6 is described below.

As in Embodiment 1, a gate electrode 103 is formed over a substrate 101 as illustrated in FIG. Next, an insulating layer 104 containing nitrogen that covers the gate electrode 103 is formed, a silicon oxide layer 105 is formed over the insulating layer 104 containing nitrogen, and a first semiconductor layer 106 is formed over the silicon oxide layer 105. Next, an amorphous semiconductor layer 110 is formed over the first semiconductor layer 106.

In this embodiment, a microcrystalline semiconductor layer having a thickness of 20 to 200 nm, preferably 30 to 100 nm, is formed as the first semiconductor layer 106.

The amorphous semiconductor layer 110 can be formed by a CVD method using a deposition gas containing silicon and hydrogen. It can be formed by a CVD method in which a deposition gas containing silicon is diluted with one or more kinds of rare gas elements selected from helium, argon, neon, krypton, and xenon. The amorphous semiconductor layer 110 can be formed using hydrogen at a flow rate of 0 to 5 times, preferably 1 to 3 times the flow rate of the deposition gas containing silicon. The amorphous semiconductor layer 110 has a high frequency power in the HF band of 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz, or a high frequency power in the VHF band of greater than 30 MHz to about 300 MHz, typically 60 MHz. Is applied.

The amorphous semiconductor layer 110 can be formed by sputtering a semiconductor target with hydrogen or a rare gas.

As the amorphous semiconductor layer 110, an amorphous silicon layer having a thickness of 30 to 200 nm, preferably 50 to 200 nm can be formed.

By providing the amorphous semiconductor layer 110 with high resistance over the first semiconductor layer 106 formed with a microcrystalline semiconductor layer, leakage current can be reduced in a thin film transistor to be formed later. Further, in a display device with a high applied voltage of the thin film transistor (for example, about 15 V), typically a liquid crystal display device, when the amorphous semiconductor layer 110 is formed thick, the withstand voltage is increased, and a high voltage is applied to the thin film transistor. Degradation of the thin film transistor can be reduced.

After that, a thin film transistor can be manufactured by the process of Embodiment 1 or 6 as shown in FIG. Here, by a process similar to that in Embodiment 1, the microcrystalline semiconductor layer 115a functioning as a channel formation region is formed over the silicon oxide layer 105, and the amorphous semiconductor layer 130 is formed over the microcrystalline semiconductor layer 115a. The In addition, a thin film transistor in which a source region and a drain region 127 are formed over the amorphous semiconductor layer 130 and a source electrode and a drain electrode 125 are formed over the source region and the drain region 127 can be manufactured.

The thin film transistor formed according to this embodiment mode has high on-state current and field-effect mobility because a microcrystalline semiconductor layer with high crystallinity is used as a channel formation region. In addition, by providing an amorphous semiconductor layer with high resistance over the microcrystalline semiconductor layer, off-state current can be reduced. Therefore, according to this embodiment mode, a thin film transistor with favorable electrical characteristics can be manufactured.

(Embodiment 8)
In this embodiment, a mode in which resistance of a source region and a drain region can be reduced in a thin film transistor having a channel length of 10 μm or less is described below. Here, description is made using Embodiment 1 and Embodiment 6, but the present invention can be applied to other embodiments as appropriate.

In the case where the impurity semiconductor layer 109 is formed using microcrystalline silicon to which phosphorus is added or microcrystalline silicon to which boron is added, the mixed layer 107b or the layer 107c containing an amorphous semiconductor illustrated in FIG. A microcrystalline semiconductor layer, typically a microcrystalline silicon layer, is formed between the impurity semiconductor layer 109 and the impurity semiconductor layer 109. In the thin film transistor described in Embodiment 6, a microcrystalline semiconductor layer, typically a microcrystalline silicon layer, is formed between the amorphous semiconductor layer 110 and the impurity semiconductor layer 109. With such a structure, a low-density layer is not formed at the initial stage of deposition of the impurity semiconductor layer 109, and the impurity semiconductor layer 109 can be crystal-grown using the microcrystalline semiconductor layer as a seed crystal. Can be improved. As a result, resistance generated at the interface between the impurity semiconductor layer 109 and the mixed layer 107b, the layer 107c containing an amorphous semiconductor, or the amorphous semiconductor layer 110 can be reduced. As a result, the amount of current flowing through the source region, the semiconductor layer, and the drain region of the thin film transistor can be increased, and the on-current and field-effect mobility can be increased.

(Embodiment 9)
In this embodiment, an element substrate in which the thin film transistor described in any of Embodiments 1 to 8 can be used and a display device including the element substrate are described below. Examples of the display device include a liquid crystal display device, a light-emitting display device, and electronic paper. The thin film transistor of the above embodiment can be used for an element substrate of another display device. Here, a liquid crystal display device including the thin film transistor described in Embodiment Mode 1, typically a VA (Vertical Alignment) liquid crystal display device will be described with reference to FIGS.

FIG. 17 shows a cross-sectional structure of a pixel portion of a liquid crystal display device. Over the substrate 301, the thin film transistor 303 and the capacitor 305 which are manufactured in the above embodiment modes are formed. In addition, the pixel electrode 309 is formed over the insulating layer 308 formed over the thin film transistor 303. The source or drain electrode 307 of the thin film transistor 303 and the pixel electrode 309 are connected to each other through an opening provided in the insulating layer 308. An alignment film 311 is formed on the pixel electrode 309.

The capacitor 305 includes a capacitor wiring 304 formed at the same time as the gate electrode 302 of the thin film transistor 303, a gate insulating layer 306, and a pixel electrode 309.

A stacked body from the substrate 301 to the alignment film 311 is referred to as an element substrate 313.

A light-blocking layer 323 that blocks light from entering the thin film transistor 303 and a coloring layer 325 are formed over the counter substrate 321. In addition, a planarization layer 327 is formed over the light-blocking layer 323 and the coloring layer 325. A counter electrode 329 is formed over the planarization layer 327, and an alignment film 331 is formed over the counter electrode 329.

Note that the light-blocking layer 323, the coloring layer 325, and the planarization layer 327 function as a color filter over the counter substrate 321. Note that one or both of the light-blocking layer 323 and the planarization layer 327 may not be formed over the counter substrate 321.

The colored layer has a function of preferentially transmitting light in an arbitrary wavelength range within the visible light wavelength range. In general, a colored layer that preferentially transmits light in the red wavelength range, light in the blue wavelength range, and light in the green wavelength range is often used in a color filter. However, the combination of the colored layers is not limited to this.

The substrate 301 and the counter substrate 321 are fixed with a sealant (not shown), and a liquid crystal layer 343 is filled inside the substrate 301, the counter substrate 321, and the sealant. In addition, a spacer 341 is provided in order to maintain a distance between the substrate 301 and the counter substrate 321.

The pixel electrode 309, the liquid crystal layer 343, and the counter electrode 329 overlap with each other, so that a liquid crystal element is formed.

FIG. 18 shows a liquid crystal display device different from that in FIG. Here, the coloring layer and the light shielding layer are not formed on the counter substrate 321 side, and the coloring layer and the light shielding layer are formed on the substrate 301 side where the thin film transistor 303 is formed.

FIG. 18 shows a cross-sectional structure of a pixel portion of a liquid crystal display device. Over the substrate 301, the thin film transistor 303 and the capacitor 305 which are manufactured in the above embodiment modes are formed.

In addition, a light-blocking layer 323 and a colored layer 351 are formed over the insulating layer 308 formed over the thin film transistor 303. In addition, a protective layer 353 is formed over the light-blocking layer 323 and the colored layer 351 in order to prevent impurities contained in the colored layer 351 from entering the liquid crystal layer 343. A pixel electrode 309 is formed over the light-blocking layer 323, the colored layer 351, and the protective layer 353. The light shielding layer 323 is provided to prevent external light from entering the thin film transistor 303 of each pixel, in particular, the channel formation region of the thin film transistor 303. Therefore, the light shielding layer 323 is provided so as to cover the thin film transistor 303. In FIG. 18, the light shielding layer 323 is provided between the thin film transistor 303 and the pixel electrode 309, but may be provided between the substrate 301 and the thin film transistor 303. Further, it may be provided between the thin film transistor 303 and the pixel electrode 309 and between the substrate 301 and the thin film transistor 303.

The colored layer 351 may be formed of a layer that preferentially transmits light in any wavelength range (red, blue, or green) for each pixel.

In addition, since the light-blocking layer 323 and the colored layer 351 also function as a planarization layer, uneven alignment of the liquid crystal layer 343 can be reduced.

The source or drain electrode 307 of the thin film transistor 303 and the pixel electrode 309 are connected to each other in an opening provided in the insulating layer 308, the light-blocking layer 323, the coloring layer 351, and the protective layer 353. An alignment film 311 is formed on the pixel electrode 309.

The capacitor 305 includes a capacitor wiring 304 formed at the same time as the gate electrode 302 of the thin film transistor 303, a gate insulating layer 306, and a pixel electrode 309.

A stacked body from the substrate 301 to the alignment film 311 is referred to as an element substrate 355.

An insulating layer 328 is formed over the counter substrate 321. A counter electrode 329 is formed over the insulating layer 328, and an alignment film 331 is formed over the counter electrode 329. Note that the insulating layer 328 is not necessarily provided.

The pixel electrode 309, the liquid crystal layer 343, and the counter electrode 329 overlap with each other, so that a liquid crystal element is formed.

Note that although a VA liquid crystal display device is shown here as a liquid crystal display device, the present invention is not limited to this. That is, an element substrate formed using the thin film transistor described in Embodiment 6 can be used for an FFS liquid crystal display device, an IPS liquid crystal display device, a TN liquid crystal display device, or another liquid crystal display device.

Since the liquid crystal display device of this embodiment uses a thin film transistor having a high on-state current and high electrolysis effect mobility and a low off-current as a pixel transistor, the display image quality of the liquid crystal display device is good (for example, high contrast). Can be increased. In addition, even if the size of the thin film transistor is reduced, the electrical characteristics of the thin film transistor are not reduced; therefore, the aperture ratio of the liquid crystal display device can be improved by reducing the area of the thin film transistor. Alternatively, the pixel area can be reduced, and the resolution of the liquid crystal display device can be increased.

In the liquid crystal display device illustrated in FIG. 18, the light-blocking layer 323 and the coloring layer 351 are formed over a substrate having a thin film transistor. For this reason, alignment with the board | substrate 301 which has a thin-film transistor, and the opposing board | substrate 321 becomes easy.

(Embodiment 10)
In the element substrate 313 described in Embodiment 9, the light-emitting element is provided without forming the alignment film 311, so that the element substrate can be used for a light-emitting display device or a light-emitting device. A light-emitting display device or a light-emitting device typically includes a light-emitting element using electroluminescence as a light-emitting element. A light-emitting element utilizing electroluminescence is roughly classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former is called an organic EL element and the latter is called an inorganic EL element.

In the light-emitting display device and the light-emitting device of this embodiment, a thin film transistor with high on-state current and high electrolysis effect mobility and low off-state current is used as a pixel transistor. A light-emitting display device and a light-emitting device with low power can be manufactured.

(Embodiment 11)
The display device including the thin film transistor according to any of the above embodiments can be applied to various electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, an electronic paper, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (a mobile phone) Large-sized game machines such as portable game machines, portable information terminals, sound reproduction apparatuses, and pachinko machines. In particular, as described in Embodiments 9 and 10, the thin film transistor according to any of the above embodiments is applied to a liquid crystal display device, a light-emitting device, an electrophoretic display device, or the like, so that the display portion of the electronic device is used. Can be used. Specific examples are given below.

The semiconductor device including the thin film transistor according to any of the above embodiments can be applied to electronic paper. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, it can be applied to electronic books (electronic books), posters, advertisements in vehicles such as trains, digital signage, PID (Public Information Display), display on various cards such as credit cards, etc. . An example of the electronic device is illustrated in FIG.

FIG. 19A illustrates an example of an electronic book 2700. For example, the electronic book 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated with a hinge 2711 and can be opened / closed. With such a configuration, an operation like a paper book can be performed.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text is displayed on the right display unit (display unit 2705 in FIG. 19A) and an image is displayed on the left display unit (display unit 2707 in FIG. 19A). Can be displayed.

FIG. 19A illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation keys 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the e-book reader 2700 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 2700 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

FIG. 19B illustrates an example of a digital photo frame 2800. For example, a digital photo frame 2800 has a display portion 2803 incorporated in a housing 2801. The display unit 2803 can display various images. For example, the display unit 2803 can display image data captured by a digital camera or the like to function in the same manner as a normal photo frame.

Note that the digital photo frame 2800 includes an operation unit, an external connection terminal (a terminal that can be connected to various types of cables such as a USB terminal and a USB cable), a recording medium insertion unit, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory storing image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 2803.

In addition, the digital photo frame 2800 may be configured to be able to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

FIG. 19C illustrates an example of a television device 2900. In the television device 2900, a display portion 2903 is incorporated in a housing 2901. Images can be displayed on the display portion 2903. Here, a configuration in which the housing 2901 is supported by a stand 2905 is shown. The display device described in Embodiments 9 and 10 can be applied to the display portion 2903.

The television device 2900 can be operated with an operation switch provided in the housing 2901 or a separate remote controller. Channels and volume can be operated with operation keys provided in the remote controller, and an image displayed on the display portion 2903 can be operated. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

Note that the television set 2900 is provided with a receiver, a modem, and the like. The receiver can receive general TV broadcasts, and can be connected one-way (sender to receiver) or two-way (sender to receiver) by connecting to a priority or wireless communication network via a modem. It is also possible to perform information communication between each other or between recipients).

FIG. 19D illustrates an example of a mobile phone 3000. The cellular phone 3000 includes operation buttons 3003 and 3007, an external connection port 3004, a speaker 3005, a microphone 3006, and the like in addition to the display portion 3002 incorporated in the housing 3001. The display devices described in Embodiments 9 and 10 can be applied to the display portion 3002.

In the cellular phone 3000 illustrated in FIG. 19D, the display portion 3002 is a touch panel, and a display content of the display portion 3002 can be operated by touching a finger or the like. Further, making a call or creating a mail can be performed by touching the display portion 3002 with a finger or the like.

There are mainly three screen modes of the display portion 3002. The first mode is a display mode mainly for displaying images. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

For example, when making a call or creating a mail, the display unit 3002 may be set to a character input mode mainly for inputting characters and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons in the most area of the screen of the display portion 3002.

Further, by providing a detection device having a sensor for detecting the inclination, such as a gyroscope or an acceleration sensor, in the mobile phone 3000, the orientation (vertical or horizontal) of the mobile phone 3000 is determined, and the display information on the display unit 3002 is displayed. It can be switched automatically.

The screen mode is switched by touching the display portion 3002 or operating the operation button 3007 of the housing 3001. Further, switching can be performed depending on the type of image displayed on the display portion 3002. For example, the display mode can be switched if the image signal to be displayed on the display unit is moving image data, and the input mode can be switched if it is text data.

In addition, in the input mode, when a signal detected by the optical sensor of the display unit 3002 is detected and there is no input by a touch operation on the display unit 3002, the screen mode is switched from the input mode to the display mode. You may control.

The display portion 3002 can also function as an image sensor. For example, the user can be authenticated by touching the display unit 3002 with a palm or a finger and capturing an image of a palm print, fingerprint, or the like with an image sensor. In addition, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Claims (12)

Forming a gate electrode on the substrate;
A deposition gas containing silicon and a gas containing nitrogen are mixed, high frequency power is applied, and an insulating layer containing nitrogen is formed on the gate electrode,
A deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen are mixed, and high frequency power is applied to form a silicon oxide layer on the insulating layer containing nitrogen,
A method for manufacturing a thin film transistor, wherein a deposition gas containing silicon or germanium and hydrogen are mixed and a high-frequency power is applied to form a microcrystalline semiconductor layer over the silicon oxide layer. Forming a gate electrode on the substrate;
A deposition gas containing silicon and a gas containing nitrogen are mixed, high frequency power is applied, and an insulating layer containing nitrogen is formed on the gate electrode,
A deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen are mixed, and high frequency power is applied to form a silicon oxide layer on the insulating layer containing nitrogen,
A deposition gas containing silicon or germanium is mixed with hydrogen, high-frequency power is applied to form a first semiconductor layer on the silicon oxide layer,
A deposition gas containing silicon or germanium, a gas containing hydrogen and nitrogen are mixed, high frequency power is applied, a second semiconductor layer is formed on the first semiconductor layer, and a gate insulating layer is formed. Forming a third semiconductor layer in which the first semiconductor layer and the second semiconductor layer are stacked;
Forming an impurity semiconductor layer on the third semiconductor layer;
A method for manufacturing a thin film transistor, wherein a conductive layer is formed over the impurity semiconductor layer. Forming a gate electrode on the substrate;
A deposition gas containing silicon and a gas containing nitrogen are mixed, high frequency power is applied, and an insulating layer containing nitrogen is formed on the gate electrode,
A deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen are mixed, and high frequency power is applied to form a silicon oxide layer on the insulating layer containing nitrogen,
A deposition gas containing silicon or germanium, hydrogen, and a rare gas are mixed, and high frequency power is applied to form a first semiconductor layer on the silicon oxide layer,
A deposition gas containing silicon or germanium, a gas containing hydrogen, a rare gas, and nitrogen are mixed, and a high frequency power is applied to form a second semiconductor layer on the first semiconductor layer, Forming a third semiconductor layer in which the first semiconductor layer and the second semiconductor layer are stacked on a gate insulating layer;
Forming an impurity semiconductor layer on the third semiconductor layer;
After etching the third semiconductor layer and the impurity semiconductor layer, a conductive layer is formed,
Etching the conductive layer to form a wiring,
A method for manufacturing a thin film transistor, characterized in that a source region and a drain region are formed by etching the etched impurity semiconductor layer. Forming a gate electrode on the substrate;
A deposition gas containing silicon and a gas containing nitrogen are mixed, high frequency power is applied, and an insulating layer containing nitrogen is formed on the gate electrode,
A deposition gas containing silicon, an oxidizing gas containing nitrogen, and hydrogen are mixed, and high frequency power is applied to form a silicon oxide layer on the insulating layer containing nitrogen,
A deposition gas containing silicon or germanium, hydrogen, and a rare gas are mixed, and high frequency power is applied to form a first semiconductor layer on the silicon oxide layer,
A deposition gas containing silicon or germanium, a gas containing hydrogen, a rare gas, and nitrogen are mixed, and a high frequency power is applied to form a second semiconductor layer on the first semiconductor layer, Forming a third semiconductor layer in which the first semiconductor layer and the second semiconductor layer are stacked on the silicon oxide layer;
Forming an impurity semiconductor layer on the third semiconductor layer;
Forming a conductive layer on the impurity semiconductor layer;
After etching the third semiconductor layer, the impurity semiconductor layer, and the conductive layer, the etched conductive layer is etched to form a wiring,
A method for manufacturing a thin film transistor, characterized in that a source region and a drain region are formed by etching the etched impurity semiconductor layer.   5. The method for manufacturing a thin film transistor according to claim 2, wherein the first semiconductor layer is a microcrystalline semiconductor layer.   6. The third semiconductor layer according to claim 2, wherein the third semiconductor layer includes a microcrystalline semiconductor layer in contact with the silicon oxide layer, and a microcrystalline semiconductor and an amorphous semiconductor in contact with the microcrystalline semiconductor layer. And a method for manufacturing a thin film transistor.   6. The third semiconductor layer according to claim 1, wherein the third semiconductor layer includes a microcrystalline semiconductor layer in contact with the silicon oxide layer, a mixed layer in contact with the microcrystalline semiconductor layer, and an amorphous in contact with the mixed layer. A method for manufacturing a thin film transistor, characterized in that a layer containing a crystalline semiconductor is stacked.   8. The method for manufacturing a thin film transistor according to claim 1, wherein the insulating layer containing nitrogen is a silicon nitride layer or a silicon nitride oxide layer.   9. The method for manufacturing a thin film transistor according to claim 1, wherein a rare gas is mixed with a deposition gas containing silicon or germanium and hydrogen.   10. The method for manufacturing a thin film transistor according to claim 1, wherein a rare gas is mixed together with a deposition gas containing silicon or germanium, a gas containing hydrogen, and nitrogen.   11. The method for manufacturing a thin film transistor according to claim 9, wherein the rare gas is helium, argon, neon, krypton, or xenon.   12. The method for manufacturing a thin film transistor according to claim 2, wherein the gas containing nitrogen is ammonia, nitrogen gas, nitrogen fluoride, or nitrogen chloride.