JP2010192580A - Thermoelectric conversion element and method of manufacturing the same - Google Patents

Thermoelectric conversion element and method of manufacturing the same Download PDF

Info

Publication number
JP2010192580A
JP2010192580A JP2009033842A JP2009033842A JP2010192580A JP 2010192580 A JP2010192580 A JP 2010192580A JP 2009033842 A JP2009033842 A JP 2009033842A JP 2009033842 A JP2009033842 A JP 2009033842A JP 2010192580 A JP2010192580 A JP 2010192580A
Authority
JP
Japan
Prior art keywords
silicon
type semiconductor
film
thermoelectric conversion
semiconductor block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009033842A
Other languages
Japanese (ja)
Other versions
JP5282598B2 (en
Inventor
Chihoko Kaneda
千穂子 金田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009033842A priority Critical patent/JP5282598B2/en
Publication of JP2010192580A publication Critical patent/JP2010192580A/en
Application granted granted Critical
Publication of JP5282598B2 publication Critical patent/JP5282598B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Silicon Compounds (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thermoelectric conversion element that can be produced with comparative ease, which has high electrical conducting properties and has low thermal conductivity and a high thermoelectric conversion efficiency, as well as, to provide a method of manufacturing the element. <P>SOLUTION: On an SiO<SB>2</SB>substrate 21, an Si film 22, into which a p-type or n-type impurity is introduced, is formed into a thickness, for instance, from 3 to 160 nm. After that, ion implantation equipment is used to form a wall 23 made of the SiO<SB>2</SB>onto the Si film 22 into a stripe shape, and then the surface of the Si film 22 is oxidized to form a SiO<SB>2</SB>film 24; by so doing, a silicon nano-wire is formed that is made of long and thin Si surrounded by the SiO<SB>2</SB>; and after repeatedly carrying out these steps to form a laminated structure, it is cut into a predetermined size to make a semiconductor block. A p-type semiconductor block and an n-type semiconductor block formed in this way are combined, to form a thermoelectric conversion element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、熱を電気に変換する熱電変換素子及びその製造方法に関する。   The present invention relates to a thermoelectric conversion element that converts heat into electricity and a method for manufacturing the same.

熱を電気に変換する熱電変換素子が開発されており、地球温暖化防止策の一つとして、熱電変換素子を用いてデータセンターや工場又は家庭等から排出される熱を電気に変換して再利用することが提案されている。   Thermoelectric conversion elements that convert heat into electricity have been developed, and as one of the measures to prevent global warming, the heat discharged from data centers, factories, or homes is converted into electricity using thermoelectric conversion elements and re-generated. Proposed to use.

熱電変換素子は、組成が異なる2種類の導体又は半導体を接合して形成される。これらの導体又は半導体の2つの接合部を異なる温度に保つと、ゼーベック効果により接合部間に起電力が発生する。一般的な熱電変換素子では組成が異なる2つの導体又は半導体を接合したものを1つのセルとし、複数のセルを直列に接続することによって大きな起電力を得ている。   The thermoelectric conversion element is formed by joining two types of conductors or semiconductors having different compositions. When the two junctions of these conductors or semiconductors are kept at different temperatures, an electromotive force is generated between the junctions due to the Seebeck effect. In a general thermoelectric conversion element, two conductors or semiconductors having different compositions are joined as one cell, and a large electromotive force is obtained by connecting a plurality of cells in series.

特表2002−540636号公報Japanese translation of PCT publication No. 2002-540636

Allon I. Hochbaum et al., Enhanced thermoelectric performance of rough silicon nanowires, NATURE Vol.451/10 January 2008Allon I. Hochbaum et al., Enhanced thermoelectric performance of rough silicon nanowires, NATURE Vol. 451/10 January 2008

ところで、熱電変換効率の指標となる熱電性能指数Z(K-1)は、下記(1)式により表わされる。 By the way, the thermoelectric figure of merit Z (K −1 ) serving as an index of the thermoelectric conversion efficiency is expressed by the following equation (1).

Z=α2/ρκ …(1)
ここで、αはゼーベック係数(V/K)、ρは電気抵抗率(Ωm)、κは熱伝導率(W/mK)である。
Z = α 2 / ρκ (1)
Here, α is the Seebeck coefficient (V / K), ρ is the electrical resistivity (Ωm), and κ is the thermal conductivity (W / mK).

この(1)式からわかるように、熱電変換効率を高くするためには、電気伝導性が高く(すなわち電気抵抗率ρの値が小さい)、且つ熱伝導性が低い(すなわち熱伝導率κの値が小さい)熱電変換素子材料が要求される。しかし、材料そのものの電気伝導性と熱伝導性との間には相関があり、一般的には電気伝導性が高い物質は熱伝導性も高い。   As can be seen from the equation (1), in order to increase the thermoelectric conversion efficiency, the electrical conductivity is high (that is, the value of the electrical resistivity ρ is small) and the thermal conductivity is low (that is, the thermal conductivity κ is low). Thermoelectric conversion element material (small value) is required. However, there is a correlation between the electrical conductivity and thermal conductivity of the material itself. In general, a substance having high electrical conductivity has high thermal conductivity.

熱電変換素子の材料としてBiTe系金属(例えばn型素子材料としてBi2Te2.85Se0.15、p型素子材料としてBi0.5Sb1.5Te3)を用いると、比較的大きな起電力が得られることが知られている。しかし、重金属を主成分とする材料は環境に大きな負荷を与えることが懸念されるため、重金属を主成分としない材料を用いて熱電変換素子を形成することが好ましい。 It is known that a relatively large electromotive force can be obtained by using a BiTe-based metal (for example, Bi 2 Te 2.85 Se 0.15 as an n-type element material and Bi 0.5 Sb 1.5 Te 3 as a p-type element material) as a material of a thermoelectric conversion element. It has been. However, since there is a concern that a material containing a heavy metal as a main component may give a large load to the environment, it is preferable to form a thermoelectric conversion element using a material that does not contain a heavy metal as a main component.

一方、無電解エッチング法を用いて水溶液中でシリコンナノワイヤを形成する方法が提案されており、この方法で作成された直径が50nmのシリコンナノワイヤでは熱電性能指数Zが0.6程度になることが報告されている。このシリコンナノワイヤを多数束ねて熱電変換素子を形成すれば、熱電変換効率が高い熱電変換素子が得られると考えられる。しかし、そのためには複雑な製造プロセスが必要となる。   On the other hand, a method of forming silicon nanowires in an aqueous solution using an electroless etching method has been proposed, and the thermoelectric figure of merit Z may be about 0.6 in a silicon nanowire having a diameter of 50 nm prepared by this method. It has been reported. It is considered that a thermoelectric conversion element having high thermoelectric conversion efficiency can be obtained by forming a thermoelectric conversion element by bundling a large number of silicon nanowires. However, this requires a complicated manufacturing process.

以上から、比較的容易に製造することができ、電気伝導性が高く且つ熱伝導性が低くて熱電変換効率が高い熱電変換素子及びその製造方法を提供することを目的とする。   In view of the above, an object is to provide a thermoelectric conversion element that can be manufactured relatively easily, has high electrical conductivity, low thermal conductivity, and high thermoelectric conversion efficiency, and a method for manufacturing the same.

一観点によれば、p型半導体ブロックと、n型半導体ブロックと、前記p型半導体ブロックと前記n型半導体ブロックとを電気的に接続する接続部とを有する熱電変換素子の製造方法において、基板の上にp型不純物又はn型不純物が導入されたシリコン膜を形成する工程と、前記シリコン膜に酸素を打ち込んで第1のシリコン酸化膜をストライプ状に形成し、前記シリコン膜を複数の領域に分割する工程と、前記シリコン膜の表面を酸化させて第2のシリコン酸化膜を形成し、前記第1のシリコン酸化膜と前記第2のシリコン酸化膜とにより囲まれたシリコンワイヤを形成する工程と、前記シリコンワイヤが形成された基板を切断して前記p型半導体ブロック又は前記n型半導体ブロックを形成する工程とを有する熱電変換素子の製造方法が提供される。   According to one aspect, in a method of manufacturing a thermoelectric conversion element having a p-type semiconductor block, an n-type semiconductor block, and a connection portion that electrically connects the p-type semiconductor block and the n-type semiconductor block, Forming a silicon film into which a p-type impurity or an n-type impurity is introduced, and implanting oxygen into the silicon film to form a first silicon oxide film in a stripe shape, and the silicon film is formed into a plurality of regions. And a step of oxidizing the surface of the silicon film to form a second silicon oxide film, and forming a silicon wire surrounded by the first silicon oxide film and the second silicon oxide film. A method of manufacturing a thermoelectric conversion element, comprising: a step of cutting the substrate on which the silicon wire is formed to form the p-type semiconductor block or the n-type semiconductor block It is provided.

なお、本願においてシリコンワイヤとはワイヤ状のシリコンをいい、直径(又は幅)がナノオーダーのシリコンナノワイヤを含むものとする。   In the present application, the silicon wire refers to wire-like silicon, and includes silicon nanowires having a nanometer diameter (or width).

上記観点によれは、シリコン膜に酸素を打ち込んで第1のシリコン酸化膜をストライプ状に形成し、更にシリコン膜の表面を酸化させて第2のシリコン酸化膜を形成して、シリコン酸化膜を細長い形状の複数のシリコン(シリコンワイヤ)に分離する。このような方法でシリコンワイヤを作成することにより、多数のシリコンワイヤからなる半導体ブロックを容易に形成することができる。シリコンワイヤは高い熱電性能指数を有するため、多数のシリコンワイヤを含む半導体ブロックで形成された熱電変換素子は、熱電変換効率が良好である。また、重金属を主原料としないため、環境に与える負荷が少ない。   According to the above aspect, oxygen is implanted into the silicon film to form a first silicon oxide film in a stripe shape, and the surface of the silicon film is oxidized to form a second silicon oxide film. Separated into a plurality of elongated silicon (silicon wires). By producing a silicon wire by such a method, a semiconductor block composed of a large number of silicon wires can be easily formed. Since silicon wires have a high thermoelectric figure of merit, thermoelectric conversion elements formed of semiconductor blocks including a large number of silicon wires have good thermoelectric conversion efficiency. In addition, since heavy metals are not used as the main raw material, the burden on the environment is small.

図1は、実施形態に係る熱電変換素子の構造を示す模式図である。Drawing 1 is a mimetic diagram showing the structure of the thermoelectric conversion element concerning an embodiment. 図2は、熱電変換素子の1つのセルを示す模式図である。FIG. 2 is a schematic diagram showing one cell of the thermoelectric conversion element. 図3(a),(b)は、実施形態に係る熱電変換素子の製造方法を示す断面図及び平面図(その1)である。Drawing 3 (a) and (b) is a sectional view and a top view (the 1) showing a manufacturing method of a thermoelectric conversion element concerning an embodiment. 図4(a),(b)は、実施形態に係る熱電変換素子の製造方法を示す断面図及び平面図(その2)である。4A and 4B are a cross-sectional view and a plan view (part 2) illustrating the method for manufacturing the thermoelectric conversion element according to the embodiment. 図5(a),(b)は、実施形態に係る熱電変換素子の製造方法を示す断面図及び平面図(その3)である。5A and 5B are a cross-sectional view and a plan view (part 3) illustrating the method for manufacturing the thermoelectric conversion element according to the embodiment. 図6(a),(b)は、実施形態に係る熱電変換素子の製造方法を示す断面図及び平面図(その4)である。6A and 6B are a cross-sectional view and a plan view (part 4) illustrating the method for manufacturing the thermoelectric conversion element according to the embodiment. 図7(a),(b)は、実施形態に係る熱電変換素子の製造方法を示す断面図及び平面図(その5)である。7A and 7B are a cross-sectional view and a plan view (No. 5) illustrating the method for manufacturing the thermoelectric conversion element according to the embodiment.

以下、実施形態について、添付の図面を参照して説明する。   Hereinafter, embodiments will be described with reference to the accompanying drawings.

図1は実施形態に係る熱電変換素子の構造を示す模式図である。   FIG. 1 is a schematic diagram illustrating a structure of a thermoelectric conversion element according to an embodiment.

本実施形態に係る熱電変換素子10は、2枚の伝熱板14a,14b間に複数のp型半導体ブロック11と複数のn型半導体ブロック12とを挟んだ構造を有している。p型半導体ブロック11及びn型半導体ブロック12は交互に並べられ、伝熱板14a,14bの面上に設けられた導体13により電気的に直列接続されている。また、直列接続されたp型半導体ブロック11及びn型半導体ブロック12の集合体の両端には、電力を取り出すための電極15a,15bが設けられている。   The thermoelectric conversion element 10 according to the present embodiment has a structure in which a plurality of p-type semiconductor blocks 11 and a plurality of n-type semiconductor blocks 12 are sandwiched between two heat transfer plates 14a and 14b. The p-type semiconductor blocks 11 and the n-type semiconductor blocks 12 are alternately arranged and are electrically connected in series by conductors 13 provided on the surfaces of the heat transfer plates 14a and 14b. In addition, electrodes 15a and 15b for taking out electric power are provided at both ends of an assembly of the p-type semiconductor block 11 and the n-type semiconductor block 12 connected in series.

図2は、熱電変換素子10の1つのセルを示す模式図である。p型半導体ブロック11及びn型半導体ブロック12は、いずれも細長い糸状のシリコンを多数束ねた構造を有している。p型半導体ブロック11のシリコンにはp型不純物(B(ホウ素)、Al(アルミニウム)、Ga(ガリウム)及びIn(インジウム)など)が導入され、n型半導体ブロック12にはn型不純物(P(リン),As(ヒ素)及びSb(アンチモン)など)が導入されている。以下、半導体ブロック11,12内の糸状のシリコンをシリコンナノワイヤ(シリコンワイヤ)16という。p型半導体ブロック11及びn型半導体ブロック12のシリコンナノワイヤ16中の不純物濃度は、例えば1015〜1021cm-3程度である。 FIG. 2 is a schematic diagram showing one cell of the thermoelectric conversion element 10. Each of the p-type semiconductor block 11 and the n-type semiconductor block 12 has a structure in which a number of elongated thread-like silicons are bundled. A p-type impurity (B (boron), Al (aluminum), Ga (gallium), In (indium), etc.) is introduced into the silicon of the p-type semiconductor block 11, and an n-type impurity (P (Phosphorus), As (arsenic), Sb (antimony), etc.). Hereinafter, the thread-like silicon in the semiconductor blocks 11 and 12 is referred to as a silicon nanowire (silicon wire) 16. The impurity concentration in the silicon nanowire 16 of the p-type semiconductor block 11 and the n-type semiconductor block 12 is, for example, about 10 15 to 10 21 cm −3 .

シリコンナノワイヤ16はその長さ方向の位置で太さ(幅)が異なる。各シリコンナノワイヤ16は、それらの間に介在する絶縁性のシリコン酸化物(SiO2)17により相互に分離されている。但し、各シリコンナノワイヤ16は完全に分離されている必要はなく、隣接するシリコンナノワイヤ16同士が部分的につながっていてもよい。 The silicon nanowires 16 have different thicknesses (widths) at positions in the length direction. The silicon nanowires 16 are separated from each other by an insulating silicon oxide (SiO 2 ) 17 interposed therebetween. However, the silicon nanowires 16 do not have to be completely separated, and adjacent silicon nanowires 16 may be partially connected to each other.

このような構造の熱電変換素子10において、2枚の伝熱板14a,14bに温度差を与えると、ゼーベック効果によりp型半導体ブロック11とn型半導体ブロック12との間に電位差が発生し、電極15a,15bから電流を取り出すことができる。   In the thermoelectric conversion element 10 having such a structure, when a temperature difference is given to the two heat transfer plates 14a and 14b, a potential difference is generated between the p-type semiconductor block 11 and the n-type semiconductor block 12 due to the Seebeck effect. A current can be taken out from the electrodes 15a and 15b.

高い熱電変換効率を得るためには、p型半導体ブロック11及びn型半導体ブロック12の電気抵抗率ρが低く、且つ熱伝導率κが高いことが必要である。本実施形態においては、シリコンナノワイヤ16に不純物が1015〜1021cm-3程度の濃度に導入されており、シリコンナノワイヤ16の1本当たりの電気抵抗率ρが10〜10-6Ωcm程度である。また、本実施形態においては、半導体ブロック11,12が細く且つ長さ方向の位置で太さ(幅)が変化する多数のシリコンナノワイヤ16により形成されている。このため、シリコンナノワイヤ16を伝わるフォノンがシリコンナノワイヤ16とシリコン酸化物17との界面で複雑に散乱されて熱伝導性が低くなる。これにより、熱電変換素子10の熱電性能指数Zが大きくなり、熱を効率的に電気に変換することができる。 In order to obtain high thermoelectric conversion efficiency, the p-type semiconductor block 11 and the n-type semiconductor block 12 need to have low electrical resistivity ρ and high thermal conductivity κ. In this embodiment, impurities are introduced into the silicon nanowire 16 at a concentration of about 10 15 to 10 21 cm −3 , and the electrical resistivity ρ per silicon nanowire 16 is about 10 to 10 −6 Ωcm. is there. Further, in the present embodiment, the semiconductor blocks 11 and 12 are formed of a large number of silicon nanowires 16 that are thin and whose thickness (width) changes at positions in the length direction. For this reason, the phonons transmitted through the silicon nanowires 16 are scattered in a complicated manner at the interface between the silicon nanowires 16 and the silicon oxide 17 and the thermal conductivity is lowered. Thereby, the thermoelectric figure of merit Z of thermoelectric conversion element 10 becomes large, and heat can be efficiently converted into electricity.

以下、実施形態に係る熱電変換素子の製造方法について説明する。最初に、p型半導体ブロック11の製造方法について、図3〜図7を参照して説明する。   Hereinafter, the manufacturing method of the thermoelectric conversion element which concerns on embodiment is demonstrated. Initially, the manufacturing method of the p-type semiconductor block 11 is demonstrated with reference to FIGS.

まず、図3(a)に断面図、図3(b)に平面図を示すように、表面がSiO2からなるSiO2基板21を用意する。半導体ブロック11,12の熱伝導率を低くするためにはシリコンナノワイヤ16を伝わるフォノンを散乱させることが有効であり、そのためにはSiO2基板21の表面は完全な平坦ではなく、この上に堆積されるSi部分の厚さの5〜40%の凹凸があることが好ましい。 First, as shown in a sectional view in FIG. 3A and a plan view in FIG. 3B, a SiO 2 substrate 21 having a surface made of SiO 2 is prepared. In order to reduce the thermal conductivity of the semiconductor blocks 11 and 12, it is effective to scatter phonons transmitted through the silicon nanowires 16. For this purpose, the surface of the SiO 2 substrate 21 is not completely flat, and is deposited on this surface. It is preferable that there is an unevenness of 5 to 40% of the thickness of the Si portion.

次に、図4(a)に断面図、図4(b)に平面図を示すように、例えばCVD法(Chemical Vapor Deposition)又はMBE(Molecular Beam Epitaxy)法により、SiO2基板21の上に厚さが3〜160nmのp型不純物が導入されたSi膜(p型Si膜)22を形成する。Si膜22の不純物濃度は、前述したように1015〜1021cm-3程度とする。 Next, as shown in a sectional view in FIG. 4A and a plan view in FIG. 4B, for example, on the SiO 2 substrate 21 by CVD (Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy). A Si film (p-type Si film) 22 into which a p-type impurity having a thickness of 3 to 160 nm is introduced is formed. The impurity concentration of the Si film 22 is about 10 15 to 10 21 cm −3 as described above.

CVD法でp型Si膜22を形成する場合は、例えばチャンバ内の圧力を0.25気圧(約2.53×104Pa)以下に維持する。そして、SiCl4とB26との混合ガスをチャンバ内に導入し、120℃の温度で反応させて、基板20(SiO2膜21)の上にp型Si膜22を成長させる。 When the p-type Si film 22 is formed by the CVD method, for example, the pressure in the chamber is maintained at 0.25 atm (about 2.53 × 10 4 Pa) or less. Then, a mixed gas of SiCl 4 and B 2 H 6 is introduced into the chamber and reacted at a temperature of 120 ° C. to grow a p-type Si film 22 on the substrate 20 (SiO 2 film 21).

MBE法でp型Si膜22を形成する場合は、例えばSi26(ジシランガス)又は固体Siソースを用い、温度が500℃、圧力が5×10-7Torr(6.65×10-5Pa)の条件で基板20(SiO2膜21)の上にシリコン膜を成長させる。ドーパントは、ドーパント元素単体の個体を加熱し、原子状の蒸気として供給する。ドーパントとしてGa又はInなどのSiよりも重い原子を用いれば、フォノン散乱をより一層大きくして熱伝導性をより効率的に低減することができる。 When the p-type Si film 22 is formed by the MBE method, for example, Si 2 H 6 (disilane gas) or a solid Si source is used, the temperature is 500 ° C., the pressure is 5 × 10 −7 Torr (6.65 × 10 −5). A silicon film is grown on the substrate 20 (SiO 2 film 21) under the condition of Pa). The dopant heats an individual solid dopant element and supplies it as atomic vapor. If an atom heavier than Si such as Ga or In is used as a dopant, phonon scattering can be further increased and thermal conductivity can be more efficiently reduced.

次に、図5(a)に断面図、図5(b)に平面図を示すように、イオン打ち込み装置を使用してSi膜22に酸素を打ち込み、Siと酸素とが結合してなるSiO2壁(第1のシリコン酸化膜)23をストライプ状(縞状)に形成する。SiO2壁23間の間隔は例えば3〜100nmとし、SiO2壁23の幅は例えば1/8層〜100nmとする。なお、1/8層とは、シリコンモノレイヤに対し酸素が1/8の割合(8個のSi原子に対し1つの酸素原子)で結合した層であり、絶縁性を確保できるとされている最低限の厚さである。 Next, as shown in a cross-sectional view in FIG. 5A and a plan view in FIG. 5B, oxygen is implanted into the Si film 22 using an ion implantation apparatus, and SiO formed by combining Si and oxygen. Two walls (first silicon oxide film) 23 are formed in a stripe shape. The interval between the SiO 2 walls 23 is, for example, 3 to 100 nm, and the width of the SiO 2 wall 23 is, for example, 1/8 layer to 100 nm. Note that the 1/8 layer is a layer in which oxygen is bonded to the silicon monolayer at a rate of 1/8 (one oxygen atom per 8 Si atoms), and it is said that insulation can be secured. The minimum thickness.

SiO2壁23の幅は均一である必要はなく、フォノンを効率的に散乱させるためにはSiO2壁23の幅が例えばSiO2壁23の厚さの5〜40%の範囲で変化していることが好ましい。また、イオン打ち込み時の加速電圧はSi膜22の厚さに応じて設定すればよく、例えば2.5〜120keVとする。但し、SiO2壁23の下端は下層のSiO2膜21までほぼ達していればよく、加速電圧を精密に制御する必要はない。 The width of SiO 2 wall 23 need not be uniform, varies in thickness 5-40% of the range of the width, for example, SiO 2 wall 23 of SiO 2 wall 23 in order to scatter phonons efficiently Preferably it is. Further, the acceleration voltage at the time of ion implantation may be set according to the thickness of the Si film 22, for example, 2.5 to 120 keV. However, the lower end of the SiO 2 wall 23 only needs to reach the lower SiO 2 film 21, and the acceleration voltage need not be precisely controlled.

次に、図6(a)に断面図、図6(b)に平面図を示すように、酸素を含む雰囲気中でSi膜22の表面を700〜1000℃の温度で酸化し、1/8層〜100nm程度の厚さのSiO2膜(第2のシリコン酸化膜)24を形成する。このとき、酸化後に残存するSi膜22の厚さが例えば3〜100nmになるように酸化を行えばよい。平坦性を特にコントロールしなければ、Si膜22の表面に形成された自然酸化膜(SiO2膜)には凹凸が自然に形成される。但し、凹凸が、その上に堆積されるSi膜の厚さの5〜40%程度の範囲に入るような形成条件を選択することが好ましい。 Next, as shown in a cross-sectional view in FIG. 6A and a plan view in FIG. 6B, the surface of the Si film 22 is oxidized at a temperature of 700 to 1000 ° C. in an oxygen-containing atmosphere. A SiO 2 film (second silicon oxide film) 24 having a thickness of about 100 nm to 100 nm is formed. At this time, the oxidation may be performed so that the thickness of the Si film 22 remaining after the oxidation becomes, for example, 3 to 100 nm. Unless the flatness is particularly controlled, irregularities are naturally formed in the natural oxide film (SiO 2 film) formed on the surface of the Si film 22. However, it is preferable to select the formation conditions such that the unevenness falls within a range of about 5 to 40% of the thickness of the Si film deposited thereon.

このようにして、Si膜22内に、SiO2膜21,24及びSiO2壁23(図2のシリコン酸化物17に対応)により分離された多数のシリコンワイヤ16が形成される。 Thus, a large number of silicon wires 16 separated by the SiO 2 films 21 and 24 and the SiO 2 walls 23 (corresponding to the silicon oxide 17 in FIG. 2) are formed in the Si film 22.

その後、SiO2膜24の上にp型不純物が導入されたSi膜22を3〜160nmの厚さに形成する工程(図4参照)、SiO2壁23を形成する工程(図5参照)、及びSiO2膜24を形成する工程(図6参照)を数回〜数十回繰り返して行い、最後に、この積層構造の周囲全体を酸化、あるいは自然酸化膜が形成されるまで大気中に放置することにより、図7(a)に断面図、図7(b)に平面図を示すような積層構造を形成する。 Thereafter, a step of forming a Si film 22 doped with p-type impurities on the SiO 2 film 24 to a thickness of 3 to 160 nm (see FIG. 4), a step of forming the SiO 2 wall 23 (see FIG. 5), And the step of forming the SiO 2 film 24 (see FIG. 6) are repeated several to several tens of times, and finally, the entire periphery of the laminated structure is left in the atmosphere until oxidation or a natural oxide film is formed. Thus, a laminated structure is formed as shown in a sectional view in FIG. 7A and a plan view in FIG.

その後、基板切断装置(ダイサー等)により上記のSiO2とSiとからなる積層膜を切断し、例えば1mm×1mm×10mm(シリコンナノワイヤの長さ方向)の大きさのp型半導体ブロック11(図2参照)を得る。 Thereafter, the laminated film made of SiO 2 and Si is cut by a substrate cutting device (such as a dicer), and the p-type semiconductor block 11 having a size of, for example, 1 mm × 1 mm × 10 mm (the length direction of the silicon nanowire) (see FIG. 2).

n型半導体ブロック12は、上述のp型半導体ブロックと同様にして形成する。但し、Si膜22に導入する不純物として、P、As又はSb等の5価の不純物を使用する。例えばCVD法でSi膜を形成するときは、SiCl4ガスにPH3又はAsH3等のガスを混合して使用する。また、MBE法でSi膜を形成する場合は、As又はSbなどのSiよりも重い原子をドーパントとして使用する。 The n-type semiconductor block 12 is formed in the same manner as the above-described p-type semiconductor block. However, pentavalent impurities such as P, As, or Sb are used as impurities introduced into the Si film 22. For example, when forming a Si film by the CVD method, a gas such as PH 3 or AsH 3 is mixed with SiCl 4 gas. Further, when forming a Si film by the MBE method, atoms heavier than Si such as As or Sb are used as a dopant.

このようにして所定の大きさのp型半導体ブロック11及びn型半導体ブロック12を形成した後、図1に示すように、導体パターン13が形成された伝熱板14aの上にp型半導体ブロック11及びn型半導体ブロック12を並べて配置し、半導体ブロック11,12と伝熱板14aの導体パターン13とを接着剤(高熱伝導性接着剤)により機械的及び電気的に接続する。このとき、半導体ブロック11,12は、シリコンナノワイヤ16の長さ方向が高さ方向となるように配置する。   After the p-type semiconductor block 11 and the n-type semiconductor block 12 having a predetermined size are formed in this way, as shown in FIG. 1, the p-type semiconductor block is formed on the heat transfer plate 14a on which the conductor pattern 13 is formed. 11 and the n-type semiconductor block 12 are arranged side by side, and the semiconductor blocks 11 and 12 and the conductor pattern 13 of the heat transfer plate 14a are mechanically and electrically connected by an adhesive (high thermal conductive adhesive). At this time, the semiconductor blocks 11 and 12 are arranged such that the length direction of the silicon nanowire 16 is the height direction.

次いで、半導体ブロック11,12の上に伝熱板14bを配置し、伝熱板14bの導体パターンと半導体ブロック11,12とを接着剤(高熱伝導性接着剤)により機械的及び電気的に接合する。また、半導体ブロック11,12の集合体の両端に引き出し電極15a,15bを例えば銀ペーストにより形成する。このようにして、本実施形態に係る熱電変換素子が完成する。   Next, the heat transfer plate 14b is disposed on the semiconductor blocks 11 and 12, and the conductor pattern of the heat transfer plate 14b and the semiconductor blocks 11 and 12 are mechanically and electrically joined by an adhesive (high thermal conductive adhesive). To do. In addition, lead electrodes 15a and 15b are formed on both ends of the assembly of the semiconductor blocks 11 and 12 by, for example, silver paste. Thus, the thermoelectric conversion element according to the present embodiment is completed.

本実施形態に係る熱電変換素子は、SiO2膜及びSiO2壁で分離されたそれぞれのシリコンナノワイヤ16の中を電流が流れるため、シリコンナノワイヤ16とシリコン酸化物17(SiO2膜21,24及びSiO2壁23)との界面でフォノンが散乱され、電気伝導性に比べて熱伝導性が低くなる。これにより、高い熱電性能指数が実現される。 In the thermoelectric conversion element according to the present embodiment, since a current flows through each silicon nanowire 16 separated by the SiO 2 film and the SiO 2 wall, the silicon nanowire 16 and the silicon oxide 17 (SiO 2 films 21, 24 and Phonons are scattered at the interface with the SiO 2 wall 23), and the thermal conductivity becomes lower than the electrical conductivity. Thereby, a high thermoelectric figure of merit is realized.

また、本実施形態においては、シリコンナノワイヤ16を、シリコンの堆積と酸化という単純なプロセスで形成する。従って、製造が容易である。また、これらのシリコンナノワイヤ16はシリコン酸化物17と一体的に形成される。従って、個々のシリコンナノワイヤ16を束ねる工程が不要であり、製造が容易である。   In the present embodiment, the silicon nanowire 16 is formed by a simple process of silicon deposition and oxidation. Therefore, manufacture is easy. Further, these silicon nanowires 16 are formed integrally with the silicon oxide 17. Therefore, the process of bundling the individual silicon nanowires 16 is unnecessary, and the manufacturing is easy.

本方法によれば、シリコンナノワイヤを用いた熱電変換材料を、豊富で安価かつ安全な材料を用いて、単純なプロセスで簡便かつ大量に作製することができる。   According to this method, thermoelectric conversion materials using silicon nanowires can be easily and in large quantities by a simple process using abundant, inexpensive and safe materials.

10…熱電変換素子、11…p型半導体ブロック、12…n型半導体ブロック、13…導体、14a,14b…伝熱板、15a,15b…電極、16…シリコンワイヤ、17…シリコン酸化物、20…基板、21…SiO2基板、22…Si膜、23…SiO2壁、24…SiO2膜。 DESCRIPTION OF SYMBOLS 10 ... Thermoelectric conversion element, 11 ... p-type semiconductor block, 12 ... n-type semiconductor block, 13 ... Conductor, 14a, 14b ... Heat-transfer plate, 15a, 15b ... Electrode, 16 ... Silicon wire, 17 ... Silicon oxide, 20 ... Substrate, 21 ... SiO 2 substrate, 22 ... Si film, 23 ... SiO 2 wall, 24 ... SiO 2 film.

Claims (5)

p型半導体ブロックと、n型半導体ブロックと、前記p型半導体ブロックと前記n型半導体ブロックとを電気的に接続する接続部とを有する熱電変換素子の製造方法において、
基板の上にp型不純物又はn型不純物が導入されたシリコン膜を形成する工程と、
前記シリコン膜に酸素を打ち込んで第1のシリコン酸化膜をストライプ状に形成し、前記シリコン膜を複数の領域に分割する工程と、
前記シリコン膜の表面を酸化させて第2のシリコン酸化膜を形成し、前記第1のシリコン酸化膜と前記第2のシリコン酸化膜とにより囲まれたシリコンワイヤを形成する工程と、
前記シリコンワイヤが形成された基板を切断して前記p型半導体ブロック又は前記n型半導体ブロックを形成する工程と
を有することを特徴とする熱電変換素子の製造方法。
In a method of manufacturing a thermoelectric conversion element having a p-type semiconductor block, an n-type semiconductor block, and a connection portion that electrically connects the p-type semiconductor block and the n-type semiconductor block.
Forming a silicon film doped with p-type impurities or n-type impurities on a substrate;
Implanting oxygen into the silicon film to form a first silicon oxide film in a stripe shape, and dividing the silicon film into a plurality of regions;
Oxidizing the surface of the silicon film to form a second silicon oxide film, and forming a silicon wire surrounded by the first silicon oxide film and the second silicon oxide film;
And a step of cutting the substrate on which the silicon wire is formed to form the p-type semiconductor block or the n-type semiconductor block.
前記シリコン膜を形成する工程と、前記第1のシリコン酸化膜を形成する工程と、前記第2のシリコン酸化膜を形成する工程とを複数回繰り返して前記基板上に積層構造を形成し、その後前記基板を切断する工程を実施することを特徴とする請求項1に記載の熱電変換素子の製造方法。   The step of forming the silicon film, the step of forming the first silicon oxide film, and the step of forming the second silicon oxide film are repeated a plurality of times to form a laminated structure on the substrate, and then The method for manufacturing a thermoelectric conversion element according to claim 1, wherein a step of cutting the substrate is performed. 前記基板は、その表面にシリコン酸化物からなる自然酸化膜を有することを特徴とする請求項1又は2に記載の熱電変換素子の製造方法。   The method for manufacturing a thermoelectric conversion element according to claim 1, wherein the substrate has a natural oxide film made of silicon oxide on a surface thereof. p型半導体ブロックと、n型半導体ブロックと、前記p型半導体ブロックと前記n型半導体ブロックとを電気的に接続する接続部とを有する熱電変換素子において、
前記p型半導体ブロック及び前記n型半導体ブロックの少なくとも一方が、不純物が導入された複数のシリコンワイヤと、それらのシリコンワイヤ間に配置された酸化物とを有することを特徴とする熱電変換素子。
In a thermoelectric conversion element having a p-type semiconductor block, an n-type semiconductor block, and a connection portion that electrically connects the p-type semiconductor block and the n-type semiconductor block,
A thermoelectric conversion element, wherein at least one of the p-type semiconductor block and the n-type semiconductor block includes a plurality of silicon wires into which impurities are introduced and an oxide disposed between the silicon wires.
前記シリコンワイヤの幅は、3nm乃至100nmの範囲であることを特徴とする請求項4に記載の熱電変換素子。   The thermoelectric conversion element according to claim 4, wherein the width of the silicon wire is in a range of 3 nm to 100 nm.
JP2009033842A 2009-02-17 2009-02-17 Method for manufacturing thermoelectric conversion element Active JP5282598B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009033842A JP5282598B2 (en) 2009-02-17 2009-02-17 Method for manufacturing thermoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009033842A JP5282598B2 (en) 2009-02-17 2009-02-17 Method for manufacturing thermoelectric conversion element

Publications (2)

Publication Number Publication Date
JP2010192580A true JP2010192580A (en) 2010-09-02
JP5282598B2 JP5282598B2 (en) 2013-09-04

Family

ID=42818317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009033842A Active JP5282598B2 (en) 2009-02-17 2009-02-17 Method for manufacturing thermoelectric conversion element

Country Status (1)

Country Link
JP (1) JP5282598B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171716A (en) * 2010-02-16 2011-09-01 Korea Electronics Telecommun Thermoelectric device, method of forming the same, and temperature sensing sensor and heat-source image sensor using the same
JP2012235113A (en) * 2011-05-04 2012-11-29 Consorzio Delta Ti Research Heat-electricity conversion device utilizing seebeck/peltier effects and alternately laminated with conductive layer and dielectric layer in thickness of nanometer (nm) class
JP2014505998A (en) * 2010-12-03 2014-03-06 アルファベット エナジー インコーポレイテッド Low thermal conduction matrix with embedded nanostructure and its method
JP2015530743A (en) * 2012-08-17 2015-10-15 シリシウム エナジー,インコーポレイテッド System and method for forming a thermoelectric device
WO2016182210A1 (en) * 2015-05-14 2016-11-17 한국기계연구원 Electronic material using electrochemical process, and preparation method therefor
USD819627S1 (en) 2016-11-11 2018-06-05 Matrix Industries, Inc. Thermoelectric smartwatch
US10003004B2 (en) 2012-10-31 2018-06-19 Matrix Industries, Inc. Methods for forming thermoelectric elements
US10205080B2 (en) 2012-01-17 2019-02-12 Matrix Industries, Inc. Systems and methods for forming thermoelectric devices
US10290796B2 (en) 2016-05-03 2019-05-14 Matrix Industries, Inc. Thermoelectric devices and systems
US10644216B2 (en) 2014-03-25 2020-05-05 Matrix Industries, Inc. Methods and devices for forming thermoelectric elements
US10749094B2 (en) 2011-07-18 2020-08-18 The Regents Of The University Of Michigan Thermoelectric devices, systems and methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002540636A (en) * 1999-03-11 2002-11-26 エネコ インコーポレイテッド Hybrid thermionic energy converter and method thereof
JP2011517109A (en) * 2008-04-11 2011-05-26 ウニベルジッタ デグリ スツディ ディ ミラノ−ビコッカ Bidirectional thermoelectric conversion device using the Savebeck / Peltier effect using nanowires made of conductive material or semiconductor material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002540636A (en) * 1999-03-11 2002-11-26 エネコ インコーポレイテッド Hybrid thermionic energy converter and method thereof
JP2011517109A (en) * 2008-04-11 2011-05-26 ウニベルジッタ デグリ スツディ ディ ミラノ−ビコッカ Bidirectional thermoelectric conversion device using the Savebeck / Peltier effect using nanowires made of conductive material or semiconductor material

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011171716A (en) * 2010-02-16 2011-09-01 Korea Electronics Telecommun Thermoelectric device, method of forming the same, and temperature sensing sensor and heat-source image sensor using the same
JP2014505998A (en) * 2010-12-03 2014-03-06 アルファベット エナジー インコーポレイテッド Low thermal conduction matrix with embedded nanostructure and its method
JP2012235113A (en) * 2011-05-04 2012-11-29 Consorzio Delta Ti Research Heat-electricity conversion device utilizing seebeck/peltier effects and alternately laminated with conductive layer and dielectric layer in thickness of nanometer (nm) class
US10749094B2 (en) 2011-07-18 2020-08-18 The Regents Of The University Of Michigan Thermoelectric devices, systems and methods
US10205080B2 (en) 2012-01-17 2019-02-12 Matrix Industries, Inc. Systems and methods for forming thermoelectric devices
JP2015530743A (en) * 2012-08-17 2015-10-15 シリシウム エナジー,インコーポレイテッド System and method for forming a thermoelectric device
US10003004B2 (en) 2012-10-31 2018-06-19 Matrix Industries, Inc. Methods for forming thermoelectric elements
US10644216B2 (en) 2014-03-25 2020-05-05 Matrix Industries, Inc. Methods and devices for forming thermoelectric elements
WO2016182210A1 (en) * 2015-05-14 2016-11-17 한국기계연구원 Electronic material using electrochemical process, and preparation method therefor
US10290796B2 (en) 2016-05-03 2019-05-14 Matrix Industries, Inc. Thermoelectric devices and systems
US10580955B2 (en) 2016-05-03 2020-03-03 Matrix Industries, Inc. Thermoelectric devices and systems
USD819627S1 (en) 2016-11-11 2018-06-05 Matrix Industries, Inc. Thermoelectric smartwatch

Also Published As

Publication number Publication date
JP5282598B2 (en) 2013-09-04

Similar Documents

Publication Publication Date Title
JP5282598B2 (en) Method for manufacturing thermoelectric conversion element
US10305014B2 (en) Methods and devices for controlling thermal conductivity and thermoelectric power of semiconductor nanowires
KR101482598B1 (en) Thermoelectric material, method for producing same, and thermoelectric conversion module using same
US7767564B2 (en) Nanowire electronic devices and method for producing the same
US8569740B2 (en) High efficiency thermoelectric materials and devices
JP5677713B2 (en) Thermal-electrical conversion device using the Savebeck / Pelty effect using processed layers made of semiconductor material without the need for nanostructures
US20130000688A1 (en) Thermoelectric device
JP6072427B2 (en) Thermal-electrical conversion device using the Savebeck / Pelty effect in which conductive layers and dielectric layers of nanometer (nm) thickness are alternately laminated
EP2609635B1 (en) Thermoelectric module comprising thermoelectric element doped with nanoparticles and manufacturing method of the same
US20140224296A1 (en) Nanowire composite for thermoelectrics
CN103682073B (en) Thermoelement
JP5585101B2 (en) Thermoelectric conversion element and manufacturing method thereof
RU2628676C1 (en) Thermoelectric element
WO2024048473A1 (en) Thermoelectric conversion element and method for manufacturing thermoelectric conversion element
WO2024048471A1 (en) Thermoelectric conversion element
KR20150093279A (en) thermoelectric device and manufacturing of the same
Kochergin High Efficiency Thermoelectric Materials and Devices
KR20130061942A (en) Thermoelectric device using cladded nanowires for improvement of thermoelectric figure of merit

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111006

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130412

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130430

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130513

R150 Certificate of patent or registration of utility model

Ref document number: 5282598

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150