JP2010192518A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of having low ON resistance and a high breakdown voltage at the same time. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 12 made of GaN, an n-type diffusion layer 11 formed on a surface of the semiconductor substrate 12, an n+-type diffusion layer 17 formed on part of a surface of the n-type diffusion layer 11, a drain electrode 13 and a source electrode 14 formed on the n-type diffusion layer 11 apart from each other, a gate electrode 15 formed on the n+-type diffusion layer 17 between the drain electrode 13 and the source electrode 14, and a trench 19 formed on the semiconductor substrate 12 between the gate electrode 15 and the drain electrode 13, extending in a depth direction and filled with a high-resistance body 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to RF devices such as HEMTs and FETs.

  Since a substrate made of GaN or GaAs has excellent physical and electrical characteristics, a high electron mobility transistor (HEMT) for application of a high voltage, a field effect transistor (FET) is particularly effective. This is used in a semiconductor device such as a transistor.

  For example, in a FET, a p-type impurity layer is formed as a channel layer on a semiconductor substrate, and n + -type impurity layers are formed on the surface of the p-type impurity layer so as to be separated from each other. Further, a drain electrode or a source electrode is formed on each n + -type impurity layer, and a gate electrode is formed on the p-type impurity layer between these n + -type impurity layers via an insulating film. Yes.

  Since such FETs are operated by applying a high voltage, it is necessary to improve the breakdown voltage. The following structures are known as structures for improving the breakdown voltage.

  That is, a structure for reducing the impurity concentration of the channel layer (see Patent Document 1) or a structure for increasing the distance between the gate and drain (see Patent Document 2).

  However, it is known that the relationship between the breakdown voltage and the on-resistance is a trade-off relationship, and there is a problem that the on-resistance increases when the breakdown voltage is improved by the above-described conventional FET structure. . Further, when the distance between the gate and the drain is increased, there is a problem that not only the on-resistance is increased but also the size of the device is increased.

  Thus, it is difficult to achieve both high breakdown voltage and low on-resistance in the conventional high voltage application FET. Such a problem also applies to HEMTs.

JP 2008-235590 A JP-A-5-29351

  An object of the present invention is to provide a semiconductor device capable of simultaneously realizing a low on-resistance and a high breakdown voltage.

  The semiconductor device of the present invention is formed on a semiconductor substrate made of GaN or GaAs, a first impurity diffusion layer formed on the surface of the semiconductor substrate, and a part of the surface of the first impurity diffusion layer, The second impurity diffusion layer of the first conductivity type having the same conductivity type as that of the first impurity diffusion layer and having a higher impurity concentration than the first impurity diffusion layer is formed on the first impurity diffusion layer and spaced apart from each other. A drain electrode and a source electrode, a gate electrode formed on the second impurity diffusion layer and formed between the drain electrode and the source electrode, and the semiconductor between the gate electrode and the drain electrode The substrate includes a trench extending in the depth direction and filled with a high resistance inside.

  The semiconductor device of the present invention includes a semiconductor substrate made of GaN or GaAs, an electron supply layer formed on the surface of the semiconductor substrate, and a drain electrode and a source electrode formed on the electron supply layer so as to be separated from each other. And a gate electrode formed between the drain electrode and the source electrode on the electron supply layer, and extended in the depth direction on the semiconductor substrate between the gate electrode and the drain electrode. And a trench in which an electron transit layer is formed on the inner surface, and a high resistance body penetrating the electron supply layer and filling the inside of the trench.

  According to the present invention, it is possible to provide a semiconductor device capable of simultaneously realizing a low on-resistance and a high breakdown voltage.

It is a top view which shows the principal part of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 1B is a cross-sectional view taken along a broken line AA ′ in FIG. 1A. It is a top view which shows the principal part of the semiconductor device which concerns on the modification of 1st Embodiment. It is sectional drawing along broken line AA 'of FIG. 2A. It is a top view which shows the principal part of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 3B is a cross-sectional view taken along the broken line AA ′ of FIG. 3A. It is a top view which shows the principal part of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 4B is a cross-sectional view taken along the broken line AA ′ of FIG. 4A. It is sectional drawing which shows the principal part of the semiconductor device which concerns on the modification of 3rd Embodiment.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1A is a top view showing the main part of the semiconductor device according to the first embodiment. 1B is a cross-sectional view taken along a broken line AA ′ in FIG. 1A. Note that the semiconductor device of this embodiment shown in FIGS. 1A and 1B is an FET.

  As shown in FIG. 1B, in the FET according to this embodiment, the drain electrode 13 and the source electrode 14 are separated from each other on the surface of the semiconductor substrate 12 made of GaN having the n-type diffusion layer 11 formed on the surface. A gate electrode 15 is formed between the drain electrode 13 and the source electrode 14. Although the gate electrode 15 is formed on the surface of the semiconductor substrate 12 without a gate insulating film as shown in FIG. 1B, it may be formed with a gate insulating film interposed therebetween.

  As shown in FIG. 1A, the above-described n-type diffusion layer 11 is surrounded by element isolation layers 16 on all sides. In such an n-type diffusion layer 11, a channel layer composed of an n + -type diffusion layer 17 is formed on the surface of the n-type diffusion layer 11 below the gate electrode 15. Further, in a region extending from the lower side of the gate electrode 15 spaced from the surface of the n-type diffusion layer 12 to the lower side of the source electrode 14, a planar shape having a certain thickness in the depth direction as shown in FIG. 1A. The p-type diffusion layer 18 is formed. The three sides of the p-type diffusion layer 18 are in contact with the element isolation layer 16, and the remaining one side is formed at least below the gate electrode 15. Further, as shown in FIG. 1B, a part of the upper surface of the p-type diffusion layer 18 is in contact with the lower surface of the n + -type diffusion layer 17. Such a p-type diffusion layer 18 allows a drain-source current to pass through the n + -type diffusion layer 17 immediately below the gate electrode 15 without diffusing in the depth direction.

  In the FET according to this embodiment, a trench 19 is formed in the n-type diffusion layer 11 between the gate electrode 15 and the drain electrode 13 as shown in FIGS. 1A and 1B. A high resistance body 20 such as SiN, GaN, or AlGaN is embedded in the trench 19.

  In the FET according to the present embodiment described above, the trench 19 is formed in the n-type diffusion layer 11 between the gate electrode 15 and the drain electrode 13 as described above. A high resistance body 20 such as SiN, GaN, or AlGaN is embedded in the trench 19 and has a higher resistance than that of the n-type diffusion layer 11. Therefore, a current flowing between the drain and source, that is, the drain source The movement of electrons between them flows so as to detour through the vicinity of the side surface and the bottom surface of the trench 19 as indicated by arrows in FIG. 1B. Accordingly, since the electron moving distance between the gate electrode 15 and the drain electrode 13 can be substantially increased due to the depth of the trench 19, the breakdown voltage can be improved.

  Further, as described above, the electrons move so as to bypass the trench 19. Therefore, the drain-source current can be passed to a position away from the surface of the n-type diffusion layer 11. Therefore, the influence of the electric field generated on the surface of the n-type diffusion layer 11 by the surface charge trap can be reduced, so that the breakdown voltage can be improved.

  Further, the direction of the electric field perpendicular to the surface of the n-type diffusion layer 11 generated between the gate electrode 15 and the drain electrode 13 is changed with respect to the side surface of the trench 19 by a current flow that bypasses the trench 19. Can be vertical. Therefore, the electric field concentration generated at the end of the gate electrode 15 on the drain electrode 13 side can be reduced, and the breakdown voltage can be improved.

  As described above, in the n-type diffusion layer 11, the trench 19 is provided between the gate electrode 15 and the drain electrode 13, and SiN, GaN, AlGaN or the like, which is the high resistance body 20, is embedded in the trench 19. The breakdown voltage of the device can be improved.

  In addition, since the breakdown voltage can be improved due to the depth of the trench 19 as described above, the impurity concentration of the n-type diffusion layer 11 as the channel layer can be set to a high concentration. Accordingly, the on-resistance can be reduced. That is, by setting the depth of the trench 19 to a desired depth, the required high breakdown voltage and low on-resistance can be realized simultaneously.

  In addition, since it is not necessary to actually increase the distance between the gate electrode 15 and the drain electrode 13, it is not necessary to increase the occupied area of the device in order to obtain a required breakdown voltage, and an FET having a smaller occupied area than the conventional one is obtained. be able to.

  The FET according to the first embodiment described above can also be applied to the FET shown in FIGS. 2A and 2B, for example. FIG. 2A is a top view showing a main part of an FET according to a modification of the first embodiment. 2B is a cross-sectional view taken along a broken line AA ′ in FIG. 2A.

  As shown in FIG. 2B, in the FET according to the modification, the n-type diffusion layer 11 shown in FIG. 1B formed on the surface of the semiconductor substrate 12 made of GaN extends along the surface of the semiconductor substrate 12 and the trench 19 described above. This is different from the FET according to the first embodiment.

  According to the FET according to such a modification, the drain-source current flows through the n-type diffusion layer 11 having a resistance lower than that of the semiconductor substrate 12 as indicated by an arrow in the drawing. Thus, since the location where the current flows is defined by the n-type diffusion layer 11, the p-type diffusion layer 18 may not be formed unlike the FET according to the first embodiment.

  Even with the FET according to the modification of the first embodiment described above, it is possible to provide an FET capable of simultaneously realizing a low on-resistance and a high breakdown voltage, as described above.

(Second Embodiment)
FIG. 3A is a top view showing the main part of the semiconductor device according to the second embodiment. FIG. 3B is a cross-sectional view taken along the broken line AA ′ in FIG. 3A.

  As shown in FIG. 3B, the semiconductor device according to the second embodiment has a plurality of FETs 21 shown in the first embodiment arranged in parallel on a semiconductor substrate 12 made of GaN. . If the attention is paid to any one FET 21a, the two FETs 21b and 21c arranged adjacent to both ends of the FET 21 have the same source electrode 14 as the FET 21a in the FET 21b. They are arranged so as to have a common drain electrode 13. That is, the FET 21a and the FETs 21b and 21c at both ends thereof are arranged so that drain-source currents flow in opposite directions.

  The drain electrodes 13 of the plurality of FETs 21 arranged as described above are connected to the drain electrode connection pad 22 in common. Similarly, each source electrode 14 is connected in common to a source electrode connection pad 23 formed facing the drain electrode connection pad 22 across the active portion of the FET 21. Furthermore, each gate electrode 15 is connected in common to a gate electrode connection line 24 formed in parallel with the source electrode connection pad 23 between the source electrode connection pad 23 and the active portion of the FET 21. The gate electrode connection line 24 is connected to a gate electrode connection pad 25 formed to face the line 24 with the source electrode connection pad 23 interposed therebetween.

  Even in the semiconductor device according to the second embodiment described above, since each FET 21 is the FET according to the first embodiment described above, a semiconductor capable of simultaneously realizing a low on-resistance and a high breakdown voltage. An apparatus can be provided.

(Third embodiment)
FIG. 4A is a top view showing the main part of the semiconductor device according to the third embodiment. 4B is a cross-sectional view taken along a broken line AA ′ in FIG. 4A. Note that the semiconductor device of this embodiment shown in FIGS. 4A and 4B is a HEMT.

  As shown in FIG. 4B, in the HEMT according to this embodiment, a trench 34 is formed between a drain electrode 32 and a gate electrode 33 described later in a semiconductor substrate 31 made of GaN.

  An n-GaN layer 35 that is an electron transit layer is formed by epitaxial growth on a part and bottom of the inner side wall of the trench 34. In such a trench 34 in which the n-GaN layer 35 is formed on the inner surface, the trench 34 is filled, and at least exposed to the surface of an n-AlGaN layer 36 described later, such as SiN, GaN, AlGaN, etc. The high resistance body 37 is embedded.

  On the surface of the semiconductor substrate 31 in which such a trench 34 is formed, an n-AlGaN layer 36 as an electron supply layer is also formed by epitaxial growth. In the vicinity of the interface between the semiconductor substrate 31 and the n-AlGaN layer 36 formed in this way, a high-mobility two-dimensional electron gas induced in these heterojunctions is generated, as indicated by a dotted line in the figure. . The source and gate are formed with a low resistance, and the gate and drain are formed with a high resistance by a trench 34 filled with a high resistance 37.

  A drain electrode 32 and a source electrode 38 are formed at predetermined positions on the surface of the n-AlGaN layer 36 so as to be separated from each other, and a gate is provided between the drain electrode 32 and the source electrode 38. An electrode 33 is formed. Such side surfaces of the HEMT are covered with an element isolation layer 39.

  In the HEMT described above, a current flows due to the movement of an electron gas generated in the vicinity of the interface between the semiconductor substrate 31 and the n-AlGaN layer 36. At this time, the drain-source current flows along the interface between the semiconductor substrate 31 and the n-AlGaN layer 36 as indicated by the arrow in FIG. 4B, and between the gate and drain, the high resistance element 37 inside the trench 34 It flows so as to detour through the n-GaN layer 35 formed in the vicinity of the side surface and the bottom surface. Therefore, since the electron moving distance between the gate electrode 33 and the drain electrode 32 can be substantially increased due to the depth of the trench 34, the breakdown voltage can be improved.

  Further, as described above, the electron flow moves so as to bypass the high resistance body 37 inside the trench 34. Therefore, a drain-source current can be passed through a region away from the surface of the n-AlGaN layer 36. Accordingly, the influence of the surface charge trap can be reduced, and the breakdown voltage can be improved.

  Further, the electric field concentration generated at the end of the gate electrode 33 on the drain electrode 32 side can be reduced by such a current flow, so that the breakdown voltage can be improved.

  Moreover, since the breakdown voltage can be improved due to the depth of the trench 34, the impurity concentration of the n-AlGaN layer 36 can be set to a high concentration. Accordingly, the on-resistance can be reduced. That is, by setting the depth of the trench 34 to a desired depth, the required high breakdown voltage and low on-resistance can be realized simultaneously.

  Further, since it is not necessary to actually increase the distance between the gate electrode 33 and the drain electrode 32, it is not necessary to increase the occupied area of the device in order to obtain a required breakdown voltage, and a HEMT having a smaller occupied area than the conventional one is obtained. be able to.

  Note that the HEMT according to the third embodiment described above can also be applied to the HEMT shown in FIG. 5, for example. A HEMT according to a modification of the third embodiment is shown in FIG. Note that the top view of this HEMT is the same as FIG. FIG. 5 is a cross-sectional view taken along the broken line AA ′ in FIG. 4A.

  As shown in FIG. 5, in the HEMT according to the modification, the n-GaN layer 35 inside the trench 34 is not formed, and the n-AlGaN layer is also formed at the place where the n-GaN layer 35 shown in FIG. 4B is formed. The point 36 is formed is different from the HEMT according to the third embodiment.

  Even in the HEMT according to such a modification, it is possible to provide an FET capable of simultaneously realizing a low on-resistance and a high breakdown voltage, as described above.

  The embodiment of the present invention has been described above. However, the embodiment is not limited to the above-described embodiment.

  For example, in each embodiment described above, the semiconductor substrates 12 and 31 may be GaAs. In this case, the trenches 19 and 34 can be filled with high resistances 20 and 37 such as SiN, GaAs, and AlGaAs to obtain the same effect as described above.

  Other than this, for example, the conductivity type of each layer may be changed to the opposite conductivity type, and the like may be freely modified without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 11 ... N type diffused layer 12, 31 ... Semiconductor substrate 13, 32 ... Drain electrode 14, 38 ... Source electrode 15, 33 ... Gate electrode 16, 39 ... Element isolation layer 17 ... n + type diffusion layer 18 ... p type diffusion layer 19, 34 ... trench 20, 37 ... high resistance elements 21, 21a, 21b, 21c ... FET
22 ... Drain electrode connection pad 23 ... Source electrode connection pad 24 ... Gate electrode connection line 25 ... Gate electrode connection pad 35 ... n-GaN layer 36 ... n-AlGaN layer

Claims (8)

A semiconductor substrate made of GaN or GaAs;
A first impurity diffusion layer formed on the surface of the semiconductor substrate;
A second impurity diffusion layer of a first conductivity type formed on a part of the surface of the first impurity diffusion layer, having the same conductivity type as the first impurity diffusion layer and having a higher impurity concentration than the first impurity diffusion layer; ,
A drain electrode and a source electrode formed on the first impurity diffusion layer and spaced apart from each other;
A gate electrode formed on the second impurity diffusion layer and formed between the drain electrode and the source electrode;
In the semiconductor substrate between the gate electrode and the drain electrode, a trench is formed extending in the depth direction and filled with a high resistance inside, and
A semiconductor device comprising:   A planar second conductivity type third impurity having a thickness in the depth direction in a region extending from under the gate electrode to under the source electrode inside the first impurity diffusion layer of the first conductivity type. The semiconductor device according to claim 1, further comprising a diffusion layer.   2. The semiconductor according to claim 1, wherein the first impurity diffusion layer is formed on a surface of the semiconductor substrate except directly under the gate electrode and a surface along a side surface and a bottom surface of the trench. apparatus.   The high resistance body is a high resistance body made of any one of SiN, GaN, or AlGaN, or a high resistance body made of any one of SiN, GaAs, or AlGaAs. 4. The semiconductor device according to any one of 3.   A semiconductor device comprising the plurality of semiconductor devices according to claim 1, wherein the semiconductor devices are arranged in parallel. A semiconductor substrate made of GaN or GaAs;
An electron supply layer formed on the surface of the semiconductor substrate;
A drain electrode and a source electrode formed on the electron supply layer so as to be spaced apart from each other;
A gate electrode formed between the drain electrode and the source electrode on the electron supply layer;
In the semiconductor substrate between the gate electrode and the drain electrode, a trench formed in the depth direction and having an electron transit layer formed on the inner surface;
A high-resistance body that penetrates the electron supply layer and fills the inside of the trench;
A semiconductor device comprising:   The semiconductor device according to claim 6, wherein the electron supply layer is formed on a surface of the semiconductor substrate and a surface along a side surface and a bottom surface of the high resistance body.   The high resistance body is a high resistance body made of any one of SiN, GaN, or AlGaN, or a high resistance body made of any one of SiN, GaAs, or AlGaAs. 8. The semiconductor device according to any one of 7 above.

Images