JP2010186878A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective function for preventing breakage of a semiconductor device, and to improve the withstand voltage of the semiconductor device, in a horizontal semiconductor device. <P>SOLUTION: A trench 16 is formed on a wafer surface between an n+ emitter region 6 and a p+ collector region 12, and the inside thereof is embedded with a trench embedding insulation film 17. A p-type floating region 13 is arranged on the wafer surface between the n+ emitter region 6 and the trench 16. Thereby, a p-type floating region 13 being a protective function for detecting abnormality of this semiconductor device is provided, and a drift region for supporting the withstand voltage is bent by the trench 16 to increase an effective drift length. In a first switch arranged in a protective circuit of such a semiconductor circuit, a gate threshold voltage of the semiconductor device and a turn-on time not smaller than the turn-on time of the semiconductor device are set. The gate voltage of the semiconductor device is controlled by detecting the voltage of the p-type floating region 13 by the first switch. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a horizontal power semiconductor device.

  An insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), which is one of power semiconductor devices in which a MOS type field effect transistor (MOSFET: Metal Oxide Field Effect Transistor) and a bipolar transistor are fused, is formed inside. The on-resistance can be greatly reduced by the conductivity modulation by the pnp transistor. Therefore, it is used especially for an inverter driver or a plasma display panel (PDP) driver.

  In general, a power semiconductor device such as an IGBT has a withstand capability against a large current or an overvoltage, and when a load exceeding the withstand capability is applied to the semiconductor device, an internal short circuit may occur between the electrodes, which may lead to a breakdown. The cause of the internal short circuit in the semiconductor device is that the collector-emitter voltage becomes excessively high when the semiconductor device is on (FUL: Fault Under Load), or the collector-emitter voltage is fixed at a high potential. For example, the semiconductor device is turned on (HSF: Hard Switching Fault). In order to prevent the power semiconductor device from being destroyed due to such a cause, various protection functions are required for protecting the power semiconductor device from overcurrent and overvoltage.

  As a method for protecting a semiconductor device from overvoltage, for example, a method of connecting an avalanche diode to an individual semiconductor device (discrete device) such as a transistor or IGBT has been proposed (for example, see Non-Patent Document 1).

  Also, as a method for protecting the semiconductor device from overcurrent, there is a method in which a sense IGBT is provided in the main IGBT, the current flowing through the main IGBT is monitored, and the gate voltage is cut off when the overcurrent flows through the main IGBT. (For example, refer nonpatent literature 2).

  As another method for protecting a semiconductor device from overcurrent, a voltage between the collector and the emitter of the IGBT is monitored, and when an overvoltage is applied between the collector and the emitter, a current flowing through the IGBT is controlled (hereinafter referred to as an “overcurrent”). Have been proposed (for example, see Non-Patent Documents 3 to 5).

  In the technique of Non-Patent Document 2, there is a problem that power consumption is large in addition to checking consistency of electrical performance between the sense IGBT and the main IGBT. In addition, there is a problem that vibration is likely to occur in the current waveform due to the feedback loop at the time of current detection. On the other hand, in voltage sensing, the current detection accuracy is lower than that in the technique of Non-Patent Document 2, but there is an advantage that the detection current has less noise and the entire apparatus can be simplified.

  In the voltage sensing described above, a sensor (hereinafter referred to as a voltage sensor) for monitoring an overvoltage applied to the semiconductor device is provided. As the voltage sensor, one using a diode, a MOSFET provided with a gate oxide film having a film thickness similar to that of a LOCOS (Local Oxidation of Silicon) oxide film (hereinafter referred to as a field MOSFET), Some semiconductor devices are formed integrally with a semiconductor device and use a semiconductor region (hereinafter referred to as a floating region) independent of the power supply voltage of the semiconductor device.

Each voltage sensor described above will be described. Note that in this specification and the accompanying drawings, a semiconductor in which n or p is mentioned means that an electron or a hole is a carrier, respectively. Further, n ⁺ and n ^- as such, subjected to n or p ⁺ or ^- that is, a relatively high impurity concentration or a relatively low impurity concentration than the impurity concentration of the semiconductor which they are not attached, respectively To express.

FIG. 24 is a circuit diagram showing an example of conventional voltage sensing. As shown in FIG. 24, in voltage sensing using a diode, a diode 2002, a sensing resistor 2003, a comparator 2004, and a gate control circuit 2005 are provided in the IGBT 2001 in order to protect the IGBT 2001. The collector terminal of the IGBT 2001 is connected to the cathode terminal of the diode 2002 and the output terminal 2007. The emitter terminal of the IGBT 2001 is grounded. A gate control circuit 2005 is connected to the gate terminal of the IGBT 2001. A control voltage input terminal (sense input) 2008 is connected to the anode terminal of the diode 2002 via a sensing resistor 2003. When the voltage V _{OUT at the} output terminal 2007 is higher than the voltage V _{S at the} control voltage input terminal 2008, the sense voltage V _SEN at the node 2006 between the diode 2002 and the sensing resistor 2003 is preset by the comparator 2004. Compared to the voltage V _REF , the gate control circuit 2005 is driven. The gate control circuit 2005 functions to cut off or reduce the gate voltage of the IGBT 2001 (see, for example, Non-Patent Document 3).

FIG. 25 is a circuit diagram showing another example of conventional voltage sensing. As shown in FIG. 25, in voltage sensing using a field MOSFET, a field MOSFET 2102, a sensing resistor 2103, and a gate control circuit 2105 are connected to the MOSFET 2101 in order to protect the MOSFET 2101. The drain terminal of the MOSFET 2101 is connected to the gate terminal of the field MOSFET 2102 via the output terminal 2104. The source terminal of the MOSFET 2101 is grounded. The gate terminal of the MOSFET 2101 is connected to the gate control circuit 2105. The drain terminal of the field MOSFET 2102 is connected to the power supply voltage terminal 2106. The source terminal of the field MOSFET 2102 is connected to the sensing resistor 2103 and the gate control circuit 2105. The sensing resistor 2103 and the gate control circuit 2105 are grounded. The voltage across the sensing resistor 2103 is controlled by the gate-source voltage-drain-source current (V _gs -I _ds ) characteristic of the field MOSFET 2102 and is input to the gate control circuit 2105. Then, the gate voltage of the MOSFET 2101 is controlled by the gate control circuit 2105 (see, for example, Non-Patent Document 6).

FIG. 26 is a circuit diagram showing another example of conventional voltage sensing. As shown in FIG. 26, in voltage sensing in which a floating region is provided in a vertical main IGBT 1000, a switch 1017 for controlling the gate voltage of the main IGBT 1000 is provided. On the front surface of the main IGBT 1000, a p base region 1004, a p ⁺ low resistance region 1005, an n ⁺ emitter region 1006, an emitter electrode 1007, a gate electrode 1008, and a gate are formed on part of the surface layer of the n ⁻ drift layer 1003. An insulating film 1009 is provided. The rear surface of the main IGBT1000, n ^- on the back surface of the drift layer 1003, n the buffer layer 1011, p ⁺ collector layer 1012 and a collector electrode 1010 is provided. A gate terminal 1015, an emitter terminal 1016, and a collector terminal 1018 are connected to the gate electrode 1008, the emitter electrode 1007, and the collector electrode 1010.

A part of the surface layer of the n ⁻ drift layer 1003 is provided with a p-type floating region 1013 apart from the p base region 1004. A floating electrode 1014 is provided on part of the surface of the p-type floating region 1013. The floating electrode 1014 is electrically insulated from the gate electrode 1008 by the gate insulating film 1009. The p-type floating region 1013 is connected to the gate terminal of the switch 1017 through the floating electrode 1014.

  The source terminal of the switch 1017 is connected to the emitter electrode 1007 of the main IGBT 1000. The drain terminal of the switch 1017 is connected to the gate electrode 1008 of the main IGBT 1000. For example, a MOSFET or the like is used as the switch 1017, and the gate threshold voltage of the switch 1017 is set according to the limit value of the collector-emitter voltage of the main IGBT 1000. When the collector-emitter voltage of the main IGBT 1000 exceeds the limit value, the switch 1017 is turned on to control the gate voltage of the main IGBT 1000 (see, for example, Non-Patent Document 7).

FIG. 27 is a cross-sectional view showing another example of conventional voltage sensing. As shown in FIG. 27, in the voltage sensing in which the floating region is provided in the horizontal main IGBT 1100, a switch 1017 for controlling the gate voltage of the main IGBT 1100 is provided as in the semiconductor device shown in FIG. In the main IGBT 1100 shown in FIG. 27, an n ⁻ drift layer 1003 is provided on the front surface of the p ⁺ low resistivity substrate 1001. the n ^- surface layer of the drift layer 1003, p base region 1004 and the n buffer region 1011 is disposed apart from each other. An n ⁺ emitter region 1006 is provided in part of the surface layer of the p base region 1004. A p ⁺ low resistance region 1005 is provided adjacent to the n ⁺ emitter region 1006. A part of the p ⁺ low resistance region 1005 occupies a part of the region below the n ⁺ emitter region 1006. A p ⁺ collector region 1012 is provided in part of the surface layer of the n buffer region 1011.

An emitter electrode 1007 is provided from a part of the surface of the n ⁺ emitter region 1006 to the surface of the p ⁺ low resistance region 1005. That is, the emitter electrode 1007, n ⁺ emitter region 1006 and the p ⁺ low resistance region 1005 are short-circuited. A gate electrode 1008 is provided through a gate insulating film 1009 from a part of the surface of the n ⁺ emitter region 1006 to a part of the surface of the n ⁻ drift layer 1003. A collector electrode 1010 is provided on a part of the surface of the p ⁺ collector region 1012. Between the gate electrode 1008 and the collector electrode 1010, a floating electrode 1014 is provided on a part of the surface of the n ⁻ drift layer 1003 with an insulating film 1019 interposed therebetween. A back electrode 1020 is provided on the back surface of the p ⁺ low resistivity substrate 1001. A gate terminal 1015, an emitter terminal 1016, and a collector terminal 1018 (not shown) are connected to the gate electrode 1008, the emitter electrode 1007, and the collector electrode 1010. The insulating film 1019 and the floating electrode 1014 function as a voltage sensor.

n ^- drift layer 1003 is connected to the gate terminal of the switch 1017 via a floating electrode 1014. The source terminal of the switch 1017 is connected to the emitter electrode 1007 of the main IGBT 1100. The drain terminal of the switch 1017 is connected to the gate electrode 1008 of the main IGBT 1100. The method for controlling the gate voltage of the main IGBT 1100 is the same as the example shown in FIG. 26 (see, for example, Patent Document 1).

In the technique shown in Patent Document 1, the gate voltage V _GM1 of the switch 1017 is floating through the electrostatic potential V _B in the surface layer of the n ⁻ drift layer 1003 below the insulating film 1019, via the n ⁻ drift layer 1003 and the insulating film 1019. The capacitance C _SEN formed between the electrode 1014 and the gate capacitance C _GM1 of the switch 1017 has a value satisfying the following expression (1).

V _GM1 = (C _SEN / (C _SEN + C _GM1 )) V _B (1)

The gate capacitance C _GM1 is mainly a capacitance due to the gate insulating film of the switch 1017. To perform the partial pressure for controlling the gate voltage of the main IGBT1100 reasonable is the sensing capacitance C _SEN and the gate capacitance C _GM1 is required to be of the same order of magnitude.

  By the way, a method of providing a dielectric trench in the drift region is widely known as a method for improving the breakdown voltage of the semiconductor device while reducing the area of each region provided in the semiconductor device (for example, Patent Document 2, Non-Patent Document). (Ref. Literature 8 and Non-Patent Literature 9).

As such a semiconductor device, for example, a lateral MOSFET will be described. FIG. 28 is a cross-sectional view showing a conventional semiconductor device having a dielectric trench. In the semiconductor device 1300 shown in FIG. 28, an n ⁺ buried layer 1302 and an n ⁻ epitaxial layer 1303 are stacked on the front surface of a p-type substrate 1301. A p body region 1305 and an n buffer region 1304 are provided in contact with each other on part of the surface layer of the n ⁻ epitaxial layer 1303. An n ⁺ source region 1307 is provided in part of the surface layer of the p body region 1305. A p ⁺ low resistance region 1306 is provided adjacent to the n ⁺ source region 1307. An n ⁺ drain region 1308 is provided in part of the surface layer of the n buffer region 1304. A trench 1309 is provided in contact with the n ⁺ drain region 1308 so as not to penetrate the n buffer region 1304. The trench 1309 is filled with a trench buried insulating film 1310 such as an oxide film.

A gate electrode 1312 is provided through a gate oxide film 1313 from a part of the n ⁺ source region 1307 to a part of the trench 1309. The source electrode 1311 is in contact with both the n ⁺ source region 1307 and the p ⁺ low resistance region 1306, are short-circuited to the n ⁺ source region 1307 and the p ⁺ low resistance region 1306. Drain electrode 1314 is in contact with n ⁺ drain region 1308. The end of n ⁺ drain region 1308 on the gate electrode 1312 side is separated from the boundary between p body region 1305 and n buffer region 1304 by a first length L _D. The end of the trench 1309 on the gate electrode 1312 side is separated from the boundary between the p body region 1305 and the n buffer region 1304 by the second length L _P.

In such a semiconductor device 1300, since the trench embedded insulating film 1310 having a breakdown electric field larger than that of silicon is provided in the drift region, carriers in the semiconductor substrate move along the trench 1309, so that no trench is formed. The effective drift length L _eff can be increased as compared with the semiconductor device having the structure. Therefore, even if the surface area of the drift region of the semiconductor device 1300 is reduced, the drift length L _eff can be increased by adjusting the outer periphery of the trench 1309, and the on-resistance (RonA) is reduced. . At this time, the drift length L _eff can be made longer than the first length L _D , and the trench depth _LT and the trench width from the region below the n ⁺ drain region 1308 to the bottom surface of the trench 1309 when the L _B, a value that satisfies the following equation (2).

L _eff = L _P + 2L _T + L _B > L _D (2)

Japanese Patent Laid-Open No. 11-266016 (FIG. 54)

JP 2006-5175 A

T. Yamazaki, 2 others, The IGBT with monolithic overvoltage protection circuit (The IGBT protection protection circuit, United States) on Power Semiconductor Devices and ICs 1993), 1993, p. 41-45

Y. Seki, 3 others, A new IGBT with a monolithic over-current voltage protection circuit (A new IGBT with a monolithic over-current protection circuit), (Switzerland), Power Semiconductor Device Symposium (Swiss 19) ISPSD '94: Proceedings of International Symposium on Power Semiconductor Devices and ICs 1994), 1994, p. 31-35

R.Letor, 1 other, Short Circuit Behavior of IGBT's Correlated to the Intrinsic Device Structure and on the application in the circuit in the application circuit), (USA), I Triple E Transactions on Industry Applications, March-April 1995, Vol. 31, No. 2, p. 234-239

S. Musumeci, 2 others, A New Gate Circuit Performing Fault Protection of IGBTs, Duaring Short Circuit Transforms (200), 2nd, 2), A New Gate Circuit Performing Fraction of IGBTs I. Triple E Industry Applications Conference (IEEE Industry Applications Conference 2002), 2002, Vol. 4, p. 2614-2621

C. Caramel, 4 others, Interaction Analyzes and Insulation Techniques for Short-Circuit Integrated Protection Structure (Instruction Analysis for Short-Circuit Int. Of the 18th International Symposium on Power Semiconductor Devices and IC's (Proceedings of the 18th International Symposium on Power Semiconductor Dev ices & IC's), June 4-8, 2006, p6-46.

T. Terashima, 3 others, 60V field NMOS and PMOS transistors for the multi-voltage system integration (60V field NMOS and PMOS transistors for the multi-voltage system integration, power semiconductor symposium 1) Proceedings of 2001, International Symposium on Power Semiconductor Devices & IC's), 2001, p. 259-262

In-Hwan Ji, 7 others, A New 1200V PT-IGBT with protection circuit Employing the Lateral IGBT and Floating p-well voltage sensing scheme (A new 1200V PT-IGBT with protection circuit L floating p-well voltage sensing scheme, Extended Abstracts of the 2006 International Conference on Solid State Devices of the 2006 International Institute Conference on Solid State Devices and Materials), 2006 years, p. 512-513

M. Zitouni, 5 others, A New Concept for the Lateral DMOS Transistor for Smart Power IC's (Canada), Canada Device International Symposium 1999 (ISPSD '99: Proceedings of International Symposium on Power Semiconductor Devices and IC's 1999), 1999, p. 73-76

H. Teranishi, Nine, A High Density, Low On-resistance 700V Class Trench Offset Drain LDMOSFET (TOD-DMOS) (A high density, low on-resistance 700 V class trench offset OD DMOS), (USA), I Triple E International Electron Devices Meeting Technical Digest 2003 (IEEE International Devices Meeting (IEDM) Technical Digest 2003), p. 757-760

  In the techniques of Non-Patent Documents 3 to 6 described above (see FIGS. 24 and 25), a high voltage device for voltage sensing is required in addition to the main IGBT. On the other hand, the technique shown in Non-Patent Document 7 (see FIG. 26) does not require a high voltage device for voltage sensing. However, when this technology is applied to a lateral IGBT, there arises a problem that the breakdown voltage of the IGBT is lowered.

A lateral IGBT to which the technique shown in Non-Patent Document 7 described above is applied will be described. FIG. 23 is a cross-sectional view illustrating an example of voltage sensing. A main IGBT 1200 shown in FIG. 23 is provided with an insulating layer 1002 on the front surface of a p ⁺ low resistivity substrate 1001. An n ⁻ drift layer 1003 is provided on the surface of the insulating layer 1002. On the surface layer of the n ⁻ drift layer 1003, similarly to the semiconductor device shown in FIG. 27, a p base region 1004, a p ⁺ low resistance region 1005, an n ⁺ emitter region 1006, an emitter electrode 1007, a gate electrode 1008, and a gate insulating film 1009, a collector electrode 1010, an n buffer layer 1011 and a p ⁺ collector layer 1012 are provided. A back electrode 1020 is provided on the back surface of the p ⁺ low resistivity substrate 1001. Further, a gate terminal, an emitter terminal, and a collector terminal (not shown) are connected to the gate electrode 1008, the emitter electrode 1007, and the collector electrode 1010.

A p-type floating region 1013 is provided on the surface layer of the n ⁻ drift layer 1003 between the p base region 1004 and the n buffer layer 1011. A floating electrode 1014 is provided on the surface of the p-type floating region 1013. The switch 1017 is connected to the p-type floating region 1013 through the emitter electrode 1007, the gate electrode 1008, and the floating electrode 1014, similarly to the semiconductor device shown in FIG.

In the main IGBT 1200 shown in FIG. 23, since the p-type floating region 1013 is provided in the surface layer of the n ⁻ drift layer 1003, a region where an effect as a base region actually appears (hereinafter referred to as an effective base region) is formed. It will be shorter. Therefore, the breakdown voltage of the main IGBT 1200 is reduced. In the lateral IGBT shown in FIG. 27 described above, the insulating layer 1019 of the main IGBT 1100 becomes thin, which adversely affects the breakdown voltage of the main IGBT 1100.

  An object of the present invention is to provide a semiconductor device capable of providing a protection function for preventing destruction of a semiconductor device in a horizontal semiconductor device in order to solve the above-described problems caused by the prior art. It is another object of the present invention to provide a semiconductor device that can improve the breakdown voltage of the semiconductor device.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to claim 1 is provided in a first semiconductor region of a first conductivity type and a part of a surface layer of the first semiconductor region. A first conductivity type second semiconductor region having a resistivity lower than that of the first semiconductor region, and the first semiconductor region and the second semiconductor region in contact with the first semiconductor region. A third semiconductor region of a second conductivity type provided in a part of the surface layer; a gate electrode provided on a part of the surface of the third semiconductor region via a gate insulating film; A first conductivity type emitter region provided in a part of the first semiconductor region and a part of a surface layer of the first semiconductor region apart from the second semiconductor region and the third semiconductor region; The first conductivity type fourth having a lower resistivity than the first semiconductor region. A semiconductor region; a collector region of a second conductivity type provided in a part of the fourth semiconductor region; and between the second semiconductor region and the third semiconductor region and the fourth semiconductor region. A trench provided, a trench embedded insulating film embedded in the trench, a part of a surface layer of the first semiconductor region, in contact with the first semiconductor region and the second semiconductor region; A fifth semiconductor region of a second conductivity type provided between the third semiconductor region and the trench, an emitter electrode in contact with the emitter region, a collector electrode in contact with the collector region, and the fifth And a floating electrode having a floating potential in contact with the semiconductor region.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the emitter electrode is grounded, and the floating electrode is a gate terminal of a first field effect transistor having a first threshold voltage. The gate electrode is connected to the drain terminal of a second field-effect transistor having a second threshold voltage lower than the first threshold voltage, and the collector electrode has a high voltage output A drain terminal of the first field effect transistor is connected to a first power supply terminal having a circuit power supply potential, and a source terminal of the first field effect transistor is connected to the second power supply terminal. Connected to the gate terminal of the first field effect transistor and one end of the resistor, and the body potential of the first field effect transistor and the second field effect transistor. Body potential of the transistor is a ground potential, the source terminal and the other end of the resistor of said second field effect transistor is characterized in that it is grounded.

  A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the emitter electrode is connected to a source terminal of a first field effect transistor having a first threshold voltage via a resistor. The emitter electrode is further connected to a source terminal and a high voltage output terminal of a second field effect transistor having a second threshold voltage lower than the first threshold voltage, and the floating electrode is A gate terminal of the first field effect transistor and a drain terminal of the first field effect transistor; and the gate electrode is connected to a drain terminal of the second field effect transistor; The electrode is connected to the second power supply terminal of the high voltage output stage, and the source terminal of the first field effect transistor is connected to the second power supply terminal. The field effect transistor is connected to the gate terminal and one end of the resistor, and the body potential of the first field effect transistor and the body potential of the second field effect transistor are kept at the potential of the emitter electrode. The source terminal of the second field effect transistor and the other end of the resistor are connected to an emitter electrode.

  According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the first field effect transistor and the second field effect transistor are field effect transistors having a metal oxide semiconductor structure. It is characterized by that.

  A semiconductor device according to a fifth aspect of the present invention includes a first conductivity type first semiconductor region and a resistivity higher than that of the first semiconductor region provided in a part of a surface layer of the first semiconductor region. First conductivity type second semiconductor region having a low level, and the second conductivity type provided in part of the surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region A third semiconductor region, a gate electrode provided on a surface of a part of the third semiconductor region via a gate insulating film, and a first conductivity provided in a part of the third semiconductor region The resistivity of the source region of the mold and a part of the surface layer of the first semiconductor region, which is provided apart from the second semiconductor region and the third semiconductor region, than the first semiconductor region A first conductive type fourth semiconductor region having a low level and a part of the fourth semiconductor region A drain region of the first conductivity type, a trench provided between the second semiconductor region and the third semiconductor region and the fourth semiconductor region, and embedded in the trench A trench buried insulating film, a part of a surface layer of the first semiconductor region, in contact with the first semiconductor region and the second semiconductor region, and between the third semiconductor region and the trench A fifth semiconductor region of a second conductivity type provided; a source electrode in contact with the source region; a drain electrode in contact with the drain region; and a floating electrode having a floating potential in contact with the fifth semiconductor region. It is characterized by that.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the first semiconductor region is provided on a support substrate via an insulating layer. Features.

  A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the first semiconductor region is provided on a support substrate.

  A semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to any one of the first to seventh aspects, wherein the fifth semiconductor region is in contact with the trench.

  According to the invention of each claim described above, by providing the trench in the first semiconductor region, carriers in the semiconductor substrate move along the trench, so that the effective drift length of the semiconductor device is provided. It can be made longer than the drift length of a semiconductor device having a configuration that is not. In addition, by providing the semiconductor device with the first field effect transistor that detects the voltage applied to the fifth semiconductor region, the gate voltage can be reduced when an overvoltage is applied to the semiconductor device. Thereby, the substantial short circuit tolerance of the semiconductor device can be increased.

  According to the semiconductor device of the present invention, the lateral semiconductor device has an effect of providing a protection function for preventing the semiconductor device from being destroyed. Moreover, there is an effect that the breakdown voltage of the semiconductor device can be improved.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment; 6 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing another example of the semiconductor device according to the second embodiment. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device used for manufacture of IGBT of this invention. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device used for manufacture of IGBT of this invention. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device used for manufacture of IGBT of this invention. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device used for manufacture of IGBT of this invention. It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device used for manufacture of IGBT of this invention. It is a characteristic view which shows the electrostatic potential distribution at the time of breakdown in the semiconductor device concerning this invention. It is a characteristic view which shows the current-voltage characteristic of the OFF state in the semiconductor device shown in FIG. 14, and the conventional semiconductor device. It is a circuit diagram which shows an example of the protection circuit using the semiconductor device concerning this invention. It is a circuit diagram which shows an example of the abnormality detection circuit of the semiconductor device concerning this invention. It is a circuit diagram which shows an example of the abnormality detection circuit of the semiconductor device concerning this invention. It is a characteristic view which shows the relationship between the collector-emitter voltage concerning the semiconductor device of this invention, and a floating voltage. It is a characteristic view which shows the simulation result about the relationship between the collector-emitter current of the semiconductor device concerning this invention, and the voltage of each electrode. It is a characteristic view which shows the simulation result about the relationship between the collector-emitter current of the semiconductor device concerning this invention, and the voltage of each electrode. It is a characteristic view which shows the voltage characteristic of the semiconductor device concerning this invention. It is sectional drawing which shows an example of the conventional voltage sensing. It is a circuit diagram which shows an example of the conventional voltage sensing. It is a circuit diagram which shows another example of the conventional voltage sensing. It is a circuit diagram which shows another example of the conventional voltage sensing. It is sectional drawing which shows another example of the conventional voltage sensing. It is sectional drawing which shows the semiconductor device which has the conventional dielectric trench.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. The lateral n-channel IGBT shown in FIG. 1 is manufactured using an SOI substrate. The SOI substrate has a structure in which an insulating layer 2 made of an oxide film or the like and an n ⁻ drift region 3 a are stacked in this order on a p support substrate 1. The n ⁻ drift region 3a corresponds to the first semiconductor region.

N well region 3b is provided in a part of the surface layer of n ⁻ drift region 3a. n-well region 3b is, n ^- are more heavily doped than the drift region 3a, n ^- have a lower resistivity than the drift region 3a.

p base region 4, n ^- the part of the surface layer of the drift region 3a, n ^- is provided in contact with the drift region 3a and the n-well region 3b. N well region 3b and p base region 4 correspond to a second semiconductor region and a third semiconductor region, respectively.

Gate electrode 8 is provided on part of p base region 4 and on the surface of n well region 3b with gate insulating film 9 interposed. The n ⁺ emitter region 6 is provided in a part of the p base region 4 so as to be aligned with the end of the gate electrode 8 on the p base region side (the end on the n ⁺ emitter region 6 in FIG. 1). .

The channel is formed at the interface between the gate insulating film 9 and the p base region 4 between the n ⁺ emitter region 6 and the n well region 3b when the gate voltage exceeds the threshold voltage. Some The p base region 4, and p ⁺ low resistance region 5a formed so as to occupy the lower n ⁺ emitter region 6 and p ⁺ base contact region 5b which is adjacent to the n ⁺ emitter region 6 is provided ing. The p ⁺ low resistance region 5a is preferably formed so as to occupy the lower side of the n ⁺ emitter region 6 in a range that does not affect the threshold as in the present embodiment.

Outside the edge of the gate electrode 8 on the p base region side, a gate sidewall spacer region 18 made of an oxide film or a nitride film is provided in contact with the edge. The p ⁺ low resistance region 5a is formed so as not to enter the region where the channel is formed by utilizing the gate sidewall spacer region 18 so as not to affect the threshold value.

Further, n buffer region 11 is provided in a part of the surface layer of n ⁻ drift region 3 a, apart from n well region 3 b and p base region 4. n buffer region 11, n ^- are more heavily doped than the drift region 3a, n ^- have a lower resistivity than the drift region 3a. The n buffer region 11 corresponds to a fourth semiconductor region, and becomes a drift region that holds the breakdown voltage of the device together with the n ⁻ drift region 3a and the n well region 3b. As described above, this device is a punch-through type IGBT having the n buffer region 11.

The p ⁺ collector region 12 is provided in a part of the n buffer region 11 and is isolated from the n ⁻ drift region 3 a by the n buffer region 11.

A trench 16 is formed between n well region 3b and p base region 4 and n buffer region 11 so as to be separated from n well region 3b and n buffer region 11 so as not to penetrate n ⁻ drift region 3a. Yes. The trench 16 is filled with a trench buried insulating film 17 such as an oxide film.

The p-type floating region 13 is provided in a part of the surface layer of the n ⁻ drift region 3 a between the p base region 4 and the trench 16 in contact with the n ⁻ drift region 3 a and the n well region 3 b. The p-type floating region 13 corresponds to a fifth semiconductor region.

The emitter electrode 7 is in contact with both the n ⁺ emitter region 6 and the p ⁺ base contact region 5b, and short-circuits the p ⁺ base contact region 5b and the n ⁺ emitter region 6. The collector electrode 10 is in contact with the p ⁺ collector region 12. The floating electrode 14 is in contact with the p-type floating region 13. In FIG. 1, reference numeral 19 denotes an insulating film cover layer such as an oxide film provided to reduce plasma etching damage to the gate insulating film 9 during manufacturing, and reference numeral 15 denotes an interlayer insulating film.

In the above configuration, by providing the trench 16, the effective drift length of the semiconductor device is the length from the p base region 4 to the trench 16 via the region under the p-type floating region 13 (hereinafter referred to as the first). A ₁ ), a length from the region below the p-type floating region 13 to the side surface on the gate electrode 8 side of the trench 16 (hereinafter referred to as a second drift length) A ₂ , A length along the bottom surface of the trench 16 (hereinafter referred to as a third drift length) A ₃ and a length along a side surface of the trench 16 on the collector electrode 10 side (hereinafter referred to as a fourth drift length) A ₄ and the total length A ₅ from the trench 16 to the p ⁺ collector region 12 (hereinafter referred to as a fifth drift length) A ₅ .

As a result, the breakdown voltage of the semiconductor device according to the first embodiment is reduced to the effective base region of the pnp transistor including the p base region 4, the n ⁻ drift region 3a and the n buffer region 11, and the p ⁺ collector region 12. The withstand voltage determined by

On the other hand, the semiconductor device of the structure provided with no trench 16 (hereinafter, the conventional semiconductor device) in the voltage of the p ⁺ collector region 12 increases, p base region 4 and the n ^- drift region 3a and the p-type floating The pnp transistor composed of the region 13 punches through, and the width of the effective base region is reduced. The effective drift length in the conventional semiconductor device is the length from the p base region 4 to the trench 16 (hereinafter referred to as the sixth drift length) B ₁ , the third drift length A ₃ , and the fifth of the sum of the drift length a _5.

  Therefore, in the semiconductor device according to the first embodiment, the effective drift length can be increased as compared with the conventional semiconductor device. Thereby, the breakdown voltage of the semiconductor device according to the first embodiment can be made higher than the breakdown voltage of the conventional semiconductor device. The reason will be described later.

In addition, in a semiconductor device having a configuration in which only the trench 16 is provided without providing the p-type floating region 13 (hereinafter referred to as a semiconductor device in which only the trench 16 is provided), an effective drift length is obtained by providing the trench. , A sixth drift length B ₁ , a length along the side surface of the trench 16 on the gate electrode 8 side (hereinafter referred to as a seventh drift length) B ₂ , a third drift length A ₃ , a fourth Is the sum of the drift length A ₄ and the fifth drift length A ₅ .

At this time, the sum of the sixth drift length B ₁ and the seventh drift length B ₂ in the semiconductor device in which only the trench 16 is provided, and the first drift length A ₁ and the second drift length in the semiconductor device according to the first embodiment. The sum of the drift lengths A ₂ can be made substantially the same. For this reason, in the semiconductor device according to the first embodiment, even if the p-type floating region 13 is provided, the effective drift length of the semiconductor device provided with only the trench 16 can be made substantially the same.

  Thereby, in the semiconductor device according to the first embodiment, even if the surface area of the effective base region is narrowed, the effective drift length is equal to or greater than that of the conventional semiconductor device by adjusting the outer periphery of the trench 16. Can be length. That is, the semiconductor device according to the first embodiment can be downsized while maintaining or improving the withstand voltage of the semiconductor device of the conventional example.

2 to 4 are sectional views showing another example of the semiconductor device according to the first embodiment. As shown in FIG. 2, the lateral IGBT may have a configuration in which an n ⁻ drift region 3 a is stacked on a p support substrate 1 without using an SOI substrate. Further, as shown in FIGS. 3 and 4, a lateral LDMOS transistor structure may be used instead of the lateral IGBT structure. The semiconductor device illustrated in FIG. 3 is manufactured without using an SOI substrate, similarly to the semiconductor device illustrated in FIG. The semiconductor device illustrated in FIG. 4 is manufactured using an SOI substrate.

In the semiconductor device having the lateral LDMOS transistor structure shown in FIGS. 3 and 4, an n ⁺ drain region 31 is provided in place of the p ⁺ collector region 12 in the semiconductor device shown in FIG. An n ⁺ source region 33 is provided in place of the n ⁺ emitter region 6. A source electrode 34 is provided in place of the emitter electrode 7. Source electrode 34 is in contact with both n ⁺ source region 33 and p ⁺ base contact region 5 b, and short-circuits p ⁺ base contact region 5 b and n ⁺ source region 33. A drain electrode 32 is provided in place of the collector electrode 10. The drain electrode 32 is in contact with the n ⁺ drain region 31.

Incidentally, the withstand voltage of the semiconductor device of the lateral LDMOS transistor structure includes a p base region 4, n ^- drift region 3a and the n buffer region 11, determined by the effective base region of the pnp transistor consisting of the n ⁺ drain region 31..

As described above, according to the first embodiment, by providing the trench 16 in the n ⁻ drift region 3 a, the effective drift length of the semiconductor device can be reduced to the drift of the semiconductor device having the configuration in which the trench 16 is not provided. Can be longer than long. Thereby, the breakdown voltage of the semiconductor device can be made higher than the breakdown voltage of the conventional semiconductor device. In addition, the effective drift length of the semiconductor device can be made substantially the same as the drift length of the semiconductor device in which only the trench 16 is provided without providing the p-type floating region 13. As a result, even if the semiconductor device is reduced in size and the surface area of the effective base region is reduced, the effective drift length is made equal to or longer than that of the conventional semiconductor device by adjusting the outer periphery of the trench 16. can do.

(Embodiment 2)
FIG. 5 is a sectional view of the semiconductor device according to the second embodiment. In the semiconductor device shown in FIG. 1, the p-type floating region 13 is formed on a part of the surface layer of the n ⁻ drift region 3a between the p base region 4 and the trench 16, and the n ⁻ drift region 3a and the n well region 3b. And may be provided in contact with the trench 16.

6 to 8 are sectional views showing another example of the semiconductor device according to the second embodiment. As shown in FIG. 6, the lateral IGBT may have a configuration in which an n ⁻ drift region 3 a is stacked on a p support substrate 1 without using an SOI substrate. Further, as shown in FIGS. 7 and 8, a lateral LDMOS transistor structure may be used instead of the lateral IGBT structure. The semiconductor device illustrated in FIG. 7 is manufactured without using an SOI substrate, similarly to the semiconductor device illustrated in FIG. The semiconductor device illustrated in FIG. 8 is manufactured using an SOI substrate. The structure of the lateral LDMOS transistor is the same as that of the first embodiment (see FIGS. 3 and 4).

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

Next, a manufacturing process of the semiconductor device according to the present invention will be described with reference to FIGS. 9 to 13 are cross-sectional views showing states during the manufacture of the semiconductor device of the present invention. Here, the semiconductor device according to the first embodiment will be described as an example. First, as shown in FIG. 9, an insulating layer 2 such as an oxide film and an n ⁻ drift region 3a are stacked in this order on the surface of the p support substrate 1, and the n well region 3b, p Base region 4, p ⁺ low resistance region 5a, p ⁺ base contact region 5b, n ⁺ emitter region 6, gate electrode 8, gate insulating film 9, n buffer region 11, p ⁺ collector region 12, p-type floating region 13, A gate sidewall spacer region 18, an insulating film cover layer 19 and an interlayer insulating film 15 are formed.

At this time, the p ⁺ low resistance region 5a is formed under the n ⁺ emitter region 6 by ion-implanting boron or the like through the gate sidewall spacer region 18, for example. At this time, boron ions are implanted into the channel region by the insulating film cover layer 19 and the gate electrode 8 to protect the channel region. Further, by using the gate sidewall spacer region 18, the p ⁺ low resistance region 5a is formed so that boron ions do not enter the channel region side.

  Next, as shown in FIG. 10, a photoresist 41 for trench etching is applied to the surface of the interlayer insulating film 15, and a mask pattern for forming the trench 16 in the photoresist 41 is formed by photolithography. Next, as shown in FIG. 11, using the photoresist 41 as a mask, the interlayer insulating film 15 is opened by, for example, reactive ion etching (RIE).

Next, as shown in FIG. 12, after removing the photoresist 41 and cleaning the substrate, a trench 16 is formed in the n ⁻ drift region 3a by trench etching using the interlayer insulating film 15 as a mask. In this trench etching step, etching residues remaining on the substrate surface and the side walls of the openings of the interlayer insulating film 15 are also removed. In the removal of the etching residue, although not shown, the opening of the interlayer insulating film 15 is widened by, for example, about 100 nm using wet etching, for example. Next, the sidewall of the trench 16 in the vicinity of the opening of the trench 16 may be removed by, for example, about 100 nm by chemical dry etching (CDE: chemical dry etching).

  Next, as shown in FIG. 13, a low-temperature oxidation process of, eg, about 800 ° C. is performed on the sidewalls and bottom surface of the trench 16 to grow an oxide film of, eg, about 20 nm. . The trench buried insulating film 17 is a dense oxide film, for example, an oxide film formed by chemical vapor deposition (CVD) at a high temperature, and an oxide film having a good fillability, for example, ozone CVD. It is formed by a tetraethoxysilane (TEOS) film using

  Next, after planarization by chemical mechanical polishing (CMP), a contact portion of the floating electrode 14 is formed by photolithography and RIE, and the floating electrode 14 in contact with the contact portion is formed. Next, the emitter electrode 7 and the collector electrode 10 are formed to complete the semiconductor device as shown in FIG. The manufacturing process described above can also be applied to a semiconductor device of a lateral LDMOS transistor.

Next, the current-voltage (I _CE -V _CE ) characteristic at the breakdown in the OFF state of the semiconductor device according to the present invention will be described. FIG. 14 is a characteristic diagram showing the electrostatic potential distribution during breakdown in the semiconductor device according to the present invention. FIG. 15 is a characteristic diagram showing current-voltage characteristics in the off state in the semiconductor device shown in FIG. 14 and the conventional semiconductor device. FIG. 14 shows an electrostatic potential distribution in the semiconductor device of the example. Further, as shown below, the semiconductor device of the embodiment, the semiconductor device having only the p-type floating region 13 (conventional semiconductor device), and the configuration in which the p-type floating region 13 and the trench 16 are not provided. A semiconductor device (hereinafter, referred to as a semiconductor device of a comparative example) was manufactured, and an I _CE -V _CE curve in each semiconductor device is shown in FIG. The semiconductor device of embodiment, in the configuration shown in FIG. 1, n ^- the thickness of the drift region 3a and 14 [mu] m, and the distance between the p base region 4 and the p-type floating region 13 and the 3.0 [mu] m, p of the gate electrode 8 The distance between the end of the mold floating region and the trench 16 is 4.0 μm, the distance between the trench 16 and the n buffer region 11 is 4.0 μm, the depth of the trench 16 is 10 μm, and the width of the trench 16 is 0.2 μm. This is a semiconductor device when the thickness is 8 μm.

The conventional semiconductor device has the same configuration as the semiconductor device shown in FIG. In the conventional semiconductor device, the thickness of the n ⁻ drift region 3 a is 10 μm, the distance between the p base region 4 and the p type floating region 13 is 4.0 μm, and the distance between the p type floating region 13 and the n buffer region 11 is The interval was set to 4.0 μm. In the semiconductor device of the comparative example, the interval between the p base region 4 and the n buffer region 11 is 10.5 μm.

From the results shown in FIG. 15, it can be seen that the breakdown voltage of the semiconductor device of the example is improved as compared with the semiconductor device of the conventional example. The breakdown voltage of the semiconductor device of the example is 248V. This is because, in the conventional semiconductor device, due to the presence of the p-type floating region 13, the effective base of the pnp transistor comprising the p base region 4, the n ⁻ drift region 3 a and the n buffer region 11, and the p ⁺ collector region 12. This is because the width of the region is narrowed.

In the semiconductor device of the conventional example, when the voltage of the p ⁺ collector region 12 increases, a depletion layer spreads from a part of the n ⁻ drift region 3 a in contact with the p base region 4 toward the n buffer region 11 and has a certain voltage value. , A pnp transistor comprising the p base region 4, the n ⁻ drift region 3 a and the p-type floating region 13 punches through. Therefore, potential V _P of the p-type floating region 13 and the floating electrode 14 is fixed. Thereafter, when the voltage of p ⁺ collector region 12 further increases, the pnp transistor comprising p type floating region 13 fixed at potential V _P , n ⁻ drift region 3 a and n buffer region 11, and p ⁺ collector region 12. The breakdown voltage V _P1 determined by the effective base region is reached, and the conventional semiconductor device breaks down. At this time, the overall breakdown voltage of the conventional semiconductor device is V _P + V _P1 , which is lower than the breakdown voltage of the semiconductor device of the embodiment.

Further, it can be seen that the semiconductor device of the example has an improved breakdown voltage of the semiconductor device compared to the semiconductor device of the comparative example. This is because in the semiconductor device of the embodiment, the trench 16 is provided to suppress the influence of the p-type floating region 13 on the breakdown voltage, and the p base region 4, the n ⁻ drift region 3 a and the n buffer region 11, p ^This is because the effective base region of the pnp transistor including the ⁺ collector region 12 can be made longer than that of the semiconductor device of the comparative example. Further, in the semiconductor device of the example, the thickness of the n ⁻ drift region 3a and the depth of the trench 16 can be adjusted, and the size of the semiconductor device of the comparative example can be reduced while maintaining the withstand voltage.

  Next, voltage sensing using the semiconductor device according to the present invention will be described using, for example, a circuit for driving a capacitor as an example. FIG. 16 is a circuit diagram showing an example of a protection circuit using the semiconductor device according to the present invention. The output stage of the circuit shown in FIG. 16 has a so-called totem pole configuration. The circuit shown in FIG. 16 includes a first IGBT 51, a second IGBT 52, a capacitor 53, a resistor 54, a constant current source 55, a start switch 56, a high level power supply terminal 57, a gate control signal input terminal 58, and an output terminal 59. ing. The collector terminal of the first IGBT 51 is connected to the emitter terminal of the second IGBT 52 via the output terminal 59. The emitter terminal of the first IGBT 51 is grounded. The gate terminal of the first IGBT 51 is connected to the gate control signal input terminal 58. The collector terminal of the second IGBT 52 is connected to the high level power supply terminal 57 of the high voltage output stage. The gate terminal of the second IGBT 52 is connected to the capacitor 53 via a resistor 54 and a high voltage output terminal 59. One electrode of the capacitor 53 is grounded. A constant current source 55 and a start switch 56 are connected between the collector terminal and the gate terminal of the second IGBT 52. In such a circuit, the capacitor 53 is charged and discharged by adjusting the on / off states of the first IGBT 51, the second IGBT 52, and the start switch 56. The high level power supply terminal 57 corresponds to a second power supply terminal.

  Further, the first IGBT 51 and the second IGBT 52 shown in FIG. 16 are each provided with a protection circuit for detecting an overvoltage. 17 and 18 are circuit diagrams showing examples of the abnormality detection circuit of the semiconductor device according to the present invention. The circuit shown in FIG. 17 is a circuit that detects an overvoltage of the first IGBT 51, and includes a first switch 61, a second switch 62, and a first voltage dividing resistor 63. The first switch 61 and the second switch 62 are switches that control the gate voltage of the first IGBT 51 based on a detection signal from the first IGBT 51. The first switch 61 and the first voltage dividing resistor 63 have a function of converting a detection signal from the first IGBT 51 into a voltage value that can be input to the second switch 62 (hereinafter referred to as a first voltage dividing circuit). And). The first switch 61 corresponds to a first field effect transistor. The second switch 62 corresponds to a second field effect transistor. The first voltage dividing resistor 63 corresponds to a resistor.

  A second switch 62 is connected between the floating electrode (floating electrode 14 in FIG. 1) terminal of the first IGBT 51 and the gate terminal via a first voltage dividing circuit. The drain terminal of the second switch 62 is connected to the gate terminal of the first IGBT 51. The source terminal of the second switch 62 is grounded. In the first voltage dividing circuit, the source terminal of the first switch 61 and one end of the first voltage dividing resistor 63 are connected. The other end of the first voltage dividing resistor 63 is grounded. The gate terminal of the second switch 62 is connected to the source terminal of the first switch 61 and the intermediate node of the first voltage dividing resistor 63. The gate terminal of the first switch 61 is connected to the floating electrode terminal of the first IGBT 51. The drain terminal of the first switch 61 is connected to a low level power supply terminal having a circuit power supply potential. The potential (body potential) of the semiconductor substrate used for the first switch 61 and the second switch 62 is a ground potential. The low level power supply terminal corresponds to the first power supply terminal.

In the first voltage dividing circuit, a voltage (hereinafter referred to as a floating voltage) V _P detected from the floating electrode of the first IGBT 51 is converted into a voltage V _G2 that can be input to the second switch 62, The switch 62 is driven. When the second switch 62 is turned on, the gate terminal of the first IGBT 51 is grounded, and the gate voltage V _G1 of the first IGBT 51 can be reduced.

For example, MOSFETs are used for the first switch 61 and the second switch 62. In the first switch 61 directly connected to the first IGBT 51, the saturation voltage of the floating voltage V _P of the first IGBT 51 that is higher than the gate-emitter voltage (gate drive voltage) V _{GE of} the first IGBT 51. The gate threshold voltage should be set below the value. This is because the first switching 61 is not turned on when the first IGBT 51 is not in the saturation mode. The gate threshold voltage of the second switch 62 is preferably a gate threshold voltage lower than that of the first switch 61.

  The circuit shown in FIG. 18 is a circuit that detects an overvoltage of the second IGBT 52, and includes a third switch 71, a fourth switch 72, and a second voltage dividing resistor 73. The third switch 71 and the fourth switch 72 are switches that control the gate voltage of the second IGBT 52 based on the detection signal from the second IGBT 52. Further, the third switch 71 and the second voltage dividing resistor 73 have a function of converting the detection signal from the second IGBT 52 into a voltage value that can be input to the fourth switch 72 (hereinafter referred to as a second voltage divider). Pressure circuit). The third switch 71 corresponds to a first field effect transistor. The fourth switch 72 corresponds to a second field effect transistor. The second voltage dividing resistor 73 corresponds to a resistor.

  A fourth switch 72 is connected between the floating electrode (floating electrode 14 in FIG. 1) terminal of the second IGBT 52 and the gate terminal via a second voltage dividing circuit. The drain terminal of the third switch 71 is short-circuited to the gate terminal of the third switch 71. The source terminal of the fourth switch 72 and the other end of the second voltage dividing resistor 73 are short-circuited to the emitter terminal of the second IGBT 52. The body potentials of the third switch 71 and the fourth switch 72 are the emitter terminal potential of the second IGBT 52. Other configurations include the first IGBT 51, the first switch 61, the second switch 62, and the first voltage dividing resistor 63 in the circuit shown in FIG. 17, the second IGBT 52, the third switch 71, and the first switch, respectively. 4 switch 72 and the second voltage dividing resistor 73.

In the second voltage dividing circuit, the floating voltage V _P of the second IGBT 52 is converted into a voltage V _G4 that can be input to the fourth switch 72, and the fourth switch 72 is driven. When the fourth switch 72 is turned on, the gate terminal of the second IGBT 52 is grounded, and the gate voltage V _G3 of the second IGBT 52 can be reduced.

The third switch 71 and the fourth switch 72 are set in the same manner as the first switch 61 and the second switch 62, respectively. At this time, the third switch 71 uses the saturation voltage value of the gate-emitter voltage V _GE of the second IGBT 52 and the floating voltage V _P of the second IGBT 52 as a reference.

FIG. 19 is a characteristic diagram showing the relationship between the collector-emitter voltage and the floating voltage according to the semiconductor device of the present invention. Here, the protection circuit illustrated in FIG. 17 will be described as an example. When the collector-emitter voltage V _{CE of} the first IGBT 51 becomes high due to an abnormal cause (hereinafter referred to as an abnormal operation), an overvoltage is applied to the first IGBT 51 and an overcurrent flows, resulting in destruction. There is a fear. From the results shown in FIG. 19, it was found that, at this time, in the first IGBT 51, the floating voltage V _P also increased and became saturated as the collector-emitter voltage V _CE increased.

When the first IGBT 51 is turned off, that is, when the gate-emitter voltage V _GE is 0 V, the collector-emitter voltage V _CE is greater than about 20 V (measurement result C ₁ ), for example, 30 V or more, The saturation voltage of the floating voltage V _P is about 4V. On the other hand, when the first IGBT 51 is turned on, that is, when the gate-emitter voltage V _GE is 2.0 V or higher, when the collector-emitter voltage V _CE reaches about 20 V, the saturation voltage of the floating voltage V _P is reached. Becomes larger than the measurement result C ₁ (measurement result C ₂ ). For example, the gate-emitter voltage V _GE is at 6.0V, is approximately 7V.

The difference in the floating voltage V _P between the measurement result C ₁ and the measurement result C ₂ is that the p base region (p base region 4 in FIG. 1) and the p type floating region (p in FIG. 1) of the first IGBT 51 at the time of turn-on. This is due to a voltage drop that occurs between the mold floating region 13). Therefore, by detecting the floating voltage V _P , it is possible to determine the turn-off timing of the first IGBT 51 before the first IGBT 51 is destroyed, that is, before the collector-emitter voltage V _CE becomes too high. . That is, the gate threshold voltage value of the first switch 61 is higher than the gate-emitter voltage (gate drive voltage) V _{GE of} the first IGBT 51 and equal to or less than the saturation voltage value of the floating voltage V _P of the first IGBT 51. Set the voltage value of. Thereby, the first IGBT 51 can be driven, and the first IGBT 51 can be turned off before the first IGBT 51 is destroyed. For example, when the gate-emitter voltage V _GE is 5 V and the collector-emitter voltage V _CE > 20 V and the floating voltage V _P > 6 V are abnormal, the gate threshold value of the first switch 61 is set. What is necessary is just to set a voltage to 6V.

  Further, a field MOSFET in which a LOCOS oxide film is provided as a gate oxide film may be used for the first switch 61 and the third switch 71.

  H. Sumida et al. “Breakdown Characteristic of a High-Voltage Lateral PMOS with the LOCOS Gate on SOI” (Breakdown Characteristics of a High-Voltage Lateral PMOS with the LOCOS Gate) International Symposium on Semiconductor Wafer Bonding Science, Technology, and Applications, 203rd Meeting of the Electrochemical Society (The Seventh International Symposium on Semiconductor Bonding Sci ence, Technology, and Applications, 203rd Meeting of the Electrochemical Society), April 29, 2003, France), reported on a p-channel MOSFET having a high breakdown voltage with a gate oxide thickness of 400 nm. .

In the present invention, the gate threshold voltage V _th of the n-channel MOSFET includes the flat band voltage V _fb , the difference between Fermi level and mid gap ψ _B , dielectric constant ε _s , unit charge q, acceptor concentration N _a , gate oxide film capacitance C _{When ox} , it can be calculated as a value satisfying the following expression (3).

V _th = V _fb + 2Ψ _B + (4ε _s qN _a Ψ _B ) ^0.5 / C _ox (3)

From the formula (3), when the gate oxide film _Tox = 400 nm and the acceptor concentration N _a = 1 × 10 ¹⁶ cm ⁻³ , the gate threshold voltage V _th is about 6V.

  Next, the current-voltage characteristics of the first IGBT 51 and the second IGBT 52 will be described. 20 and 21 are characteristic diagrams showing simulation results on the relationship between the collector-emitter current and the voltage of each electrode of the semiconductor device according to the present invention. FIG. 20 shows current-voltage characteristics when the second IGBT 52 is operated and the capacitor 53 is charged. FIG. 21 shows current-voltage characteristics when the first IGBT 51 is operated and the capacitor 53 is discharged. In actually measuring each measured value, the circuits shown in FIGS. 16 to 18 are set as follows. In the circuit shown in FIG. 16, the upper limit (hereinafter referred to as current capability) of the current value that can be passed through the first IGBT 51 is set to 0.6A. The current capability of the second IGBT 52 was set to 0.2A. The capacity of the capacitor 53 was 200 pF. The resistance value of the resistor 54 was about 5 kΩ. The constant current value of the constant current source 55 was set to 0.1A. The voltage of the circuit power supply connected to the high level power supply terminal 57 was about 150V.

In the circuit shown in FIG. 17, the first switch 61 and the second switch 62 are n-channel MOSFETs. The gate threshold voltages V _th of the first switch 61 and the second switch 62 were 6 V and 1 V, respectively. The channel length L and channel width W of the first switch 61 were 2 μm and 50 μm, respectively. The channel length L and the channel width W of the second switch 62 were 2 μm and 15 μm, respectively. The resistance value of the first voltage dividing resistor 63 was set to 50 kΩ. The voltage of the circuit power supply connected to the low level power supply terminal was 5V.

In the circuit shown in FIG. 18, the third switch 71 and the fourth switch 72 are n-channel MOSFETs. The gate threshold voltage V _th of the third switch 71 and fourth switch 72, was 6V and 1V, respectively. The channel length L and the channel width W of the third switch 71 were 2 μm and 50 μm, respectively. The channel length L and the channel width W of the fourth switch 72 were 2 μm and 15 μm, respectively. The resistance value of the second voltage dividing resistor 73 was set to 50 kΩ. The channel length L is the length in the direction in which carriers flow between the source region and the drain region of the MOSFET. The channel width W is the length of the channel portion in the direction orthogonal to the channel length L.

When charging the capacitor 53, the first IGBT 51 is turned off and the start switch 56 is turned on, whereby a voltage is applied from the circuit power supply connected to the high-level power supply terminal 57 and the second IGBT 52 is turned on. The From the result of FIG. 20, it can be seen that in the second IGBT 52, the gate voltage V _G becomes higher by about 5V than the emitter voltage V _E due to the voltage from the high-level power supply terminal 57. It can also be seen that the floating voltage V _P is about 10 V higher than the emitter voltage V _E. At this time, the collector-emitter current I _CE increases to about 0.2 A and then decreases. Further, the time during which the floating voltage V _P becomes higher than the emitter voltage V _E (hereinafter referred to as “V _P high time during charging”) is because the gate threshold voltage V _th of the third switch 71 is set to 6V. It can be seen that the difference between the floating voltage V _P and the emitter voltage V _E is about 200 ns from about 12 ns to about 210 ns where the difference is 6 V or more. That is, it can be seen that the second IGBT 52 is turned on in 200 ns in a normal state where no overvoltage is applied to the second IGBT 52.

On the other hand, when discharging the capacitor 53, the second IGBT 52 is turned off, and the first IGBT 51 is turned on by applying a voltage from a circuit power supply connected to the low-level power supply terminal. From the results of FIG. 21, it can be seen that in the first IGBT 51, the gate voltage V _G and the collector-emitter current I _CE begin to increase due to the voltage from the low-level power supply terminal. It can also be seen that the collector voltage V _C begins to decrease as the floating voltage V _P increases. At this time, the floating voltage V _P is, the voltage value of the floating voltage V _P at the time when the gate voltage V _G = 0V (approximately 5V) becomes higher time than (hereinafter referred to as the discharge time of V _P high time), the gate voltage V _G is about 20ns to be 2.5V or higher to 70 ns, it is understood that between about 50 ns. That is, it can be seen that the first IGBT 51 is turned on in 50 ns in a normal state where no overvoltage is applied to the first IGBT 51.

Therefore, in such a circuit, in order to operate the output stage composed of the first IGBT 51 and the second IGBT 52 normally, the turn-on time of the first switch 61 and the second switch 62 used in the protection circuit Is preferably longer than the turn-on time of the first IGBT 51. Further, it is preferable that the turn-on time of the third switch 71 and the fourth switch 72 used in the protection circuit is longer than the turn-on time of the second IGBT 52. The reason why the turn-on time of the switch of the protection circuit is set to be longer than the time during which the floating voltage _VP is high during normal operation is to prevent the normal operation of the circuit as shown in FIG.

Next, the relationship between the turn-on time and the floating voltage of the semiconductor device of the present invention will be described. FIG. 22 is a characteristic diagram showing voltage characteristics of the semiconductor device according to the present invention. Here, FIG. 17 will be described as an example. FIG. 22 shows the gate voltage V _G1 of the first IGBT 51 when the gate capacitance of the first IGBT 51 is 24 pF and the capacitor 53 is discharged. When a voltage is applied to the gate voltage V _G1 of the first IGBT 51, the floating voltage V _P of the first IGBT 51 starts to rise. When the floating voltage V _P exceeds the gate threshold voltage of the first switch 61, the voltage is applied to the gate voltage V _G2 of the second switch 62 and the second switch 62 is turned on. The gate voltage V _{G1 of the} IGBT 51 starts to decrease.

From the results shown in FIG. 22, the abnormal operation of the first IGBT 51, for example, if you set the turn-on time of the first switch 61 to 340 ns, that is, when the discharge time of V _P high time is 340 ns, the first The gate voltage V _{G1 of the} IGBT 51 drops from 5V to 2V. In general, the short-circuit withstand capability of the IGBT varies depending on the gate voltage, and decreases when a certain gate voltage is exceeded. Therefore, since the short-circuit withstand capability of the first IGBT 51 can be increased by reducing the gate voltage V _G1 of the first IGBT 51, even if the time during which the floating voltage V _P becomes high during an abnormal discharge is long, the first The gate voltage V _G1 of one IGBT 51 can be controlled. Further, if the time during which the floating voltage V _P becomes high during abnormal discharge is longer, the value of the gate voltage V _G1 of the first IGBT 51 becomes lower than the threshold value of the first IGBT 51, and the first IGBT 51 is turned off. The

On the other hand, during normal operation of the first IGBT 51, the first IGBT 51 is pulled down by 50ns is discharged when V _P high time. At this time, the result shown in FIG. 22 shows that the drop of the gate voltage V _G1 of the first IGBT 51 is 0.5 V, and the influence on the normal operation of the circuit shown in FIG. 17 is small.

In the protection circuit shown in FIG. 18, the emitter terminal of the second IGBT 52 is short-circuited to the fourth switch 72, so that the voltage waveform is almost the same as the voltage waveform shown in FIG. Therefore, the voltage waveform of the gate voltage V _G3 of the second IGBT 52 when the capacitor 53 is charged will be described by taking the voltage waveform shown in FIG. 22 as an example. At this time, the first gate voltage shown in FIG. 22 corresponds to the gate voltage V _G3 of the second IGBT 52. The second gate voltage shown in FIG. 22 corresponds to the gate voltage V _G4 of the fourth switch 72. During the abnormal operation of the second IGBT 52, the gate voltage V _G3 of the second IGBT 52 can be lowered similarly to the first IGBT 51, and it is possible to prevent the second IGBT 52 from being destroyed. On the other hand, during normal operation of the second IGBT 52, although the second IGBT 52 becomes to be pulled down by 200ns is the discharge time of V _P high time, as shown in FIG. 22, the gate voltage V _G1 of the second IGBT 52 Drops from 5V to 3V in 200ns. Therefore, the gate voltage V _G3 of the second IGBT 52 can be controlled in the same manner as during abnormal operation.

  From the above results, in the semiconductor switch provided as the protection circuit of the IGBT, by setting the gate threshold voltage of the semiconductor switch higher than the gate-emitter voltage of the IGBT and below the saturation voltage value of the floating voltage of the IGBT, It was found that the turn-off time of the IGBT to be protected can be determined by the value of the floating voltage. Further, it has been found that by setting the turn-on time of the semiconductor switch to be longer than the turn-on time of the IGBT, for example, an output stage having a totem pole configuration can be operated normally. Further, it was found that by setting as described above, the gate voltage of the IGBT can be reduced before the IGBT is destroyed, and the substantial short-circuit withstand capability of the IGBT can be increased.

In the above, the structure relating to withstand voltage according to the present invention can be applied to a lateral LDMOS transistor or the like that requires high withstand voltage. In the present invention, the thickness of the n ⁻ drift region and the depth of the trench of the semiconductor device are not limited to the above-described numerical values and can be variously changed. In addition, the configuration of the circuit using the semiconductor device according to the present invention and the configuration of the protection circuit are not limited to the circuit configuration described above, and can be variously changed. It is desirable to change to suitable conditions according to the circuit configuration.

  As described above, the IGBT according to the present invention is useful for a high breakdown voltage switching element that requires a high short-circuit withstand capability, and particularly for a high breakdown voltage switching element used in an output stage of a driver IC or an in-vehicle IC of a flat panel display. Is suitable.

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating layer 3a 1st semiconductor region (drift region)
3b Second semiconductor region (well region)
4 Third semiconductor region (base region)
5a Low resistance region 5b Base contact region 6 Emitter region 7 Emitter electrode 8 Gate electrode 9 Gate insulating film 10 Collector electrode 11 Fourth semiconductor region (buffer region)
12 Collector region 13 Fifth semiconductor region (p-type floating region)
14 Floating electrode 15 Interlayer insulating film 16 Trench 17 Trench embedded insulating film 18 Gate sidewall spacer region 19 Insulating film cover layer

Claims (8)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a first conductivity type provided in a part of a surface layer of the first semiconductor region and having a resistivity lower than that of the first semiconductor region;
A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region;
A gate electrode provided on a part of the surface of the third semiconductor region via a gate insulating film;
A first conductivity type emitter region provided in a part of the third semiconductor region;
A first conductivity type having a lower resistivity than the first semiconductor region, which is provided apart from the second semiconductor region and the third semiconductor region in a part of the surface layer of the first semiconductor region. A fourth semiconductor region of
A second conductivity type collector region provided in a part of the fourth semiconductor region;
A trench provided between the second semiconductor region and the third semiconductor region and the fourth semiconductor region;
A trench buried insulating film buried in the trench;
Second conductivity provided between a part of the surface layer of the first semiconductor region and in contact with the first semiconductor region and the second semiconductor region and between the third semiconductor region and the trench. A fifth semiconductor region of the mold;
An emitter electrode in contact with the emitter region;
A collector electrode in contact with the collector region;
A floating electrode having a floating potential in contact with the fifth semiconductor region;
A semiconductor device comprising: The emitter electrode is grounded;
The floating electrode is connected to a gate terminal of a first field effect transistor having a first threshold voltage;
The gate electrode is connected to a drain terminal of a second field effect transistor having a second threshold voltage lower than the first threshold voltage;
The collector electrode is connected to a high voltage output terminal;
A drain terminal of the first field effect transistor is connected to a first power supply terminal having a circuit power supply potential;
A source terminal of the first field effect transistor is connected to a gate terminal of the second field effect transistor and one end of a resistor;
The body potential of the first field effect transistor and the body potential of the second field effect transistor are ground potentials;
The semiconductor device according to claim 1, wherein a source terminal of the second field effect transistor and the other end of the resistor are grounded. The emitter electrode is connected to a source terminal of a first field effect transistor having a first threshold voltage through a resistor,
The emitter electrode is further connected to a source terminal and a high voltage output terminal of a second field effect transistor having a second threshold voltage lower than the first threshold voltage,
The floating electrode is connected to a gate terminal of the first field effect transistor and a drain terminal of the first field effect transistor;
The gate electrode is connected to a drain terminal of the second field effect transistor;
The collector electrode is connected to the second power supply terminal of the high voltage output stage;
A source terminal of the first field effect transistor is connected to a gate terminal of the second field effect transistor and one end of the resistor;
The body potential of the first field effect transistor and the body potential of the second field effect transistor are kept at the potential of the emitter electrode,
The semiconductor device according to claim 1, wherein a source terminal of the second field effect transistor and the other end of the resistor are connected to an emitter electrode.   The semiconductor device according to claim 2, wherein the first field effect transistor and the second field effect transistor are field effect transistors having a metal oxide semiconductor structure. A first semiconductor region of a first conductivity type;
A second semiconductor region of a first conductivity type provided in a part of a surface layer of the first semiconductor region and having a resistivity lower than that of the first semiconductor region;
A third semiconductor region of a second conductivity type provided in part of a surface layer of the first semiconductor region in contact with the first semiconductor region and the second semiconductor region;
A gate electrode provided on a part of the surface of the third semiconductor region via a gate insulating film;
A first conductivity type source region provided in a part of the third semiconductor region;
A first conductivity type having a lower resistivity than the first semiconductor region, which is provided apart from the second semiconductor region and the third semiconductor region in a part of the surface layer of the first semiconductor region. A fourth semiconductor region of
A drain region of a first conductivity type provided in a part of the fourth semiconductor region;
A trench provided between the second semiconductor region and the third semiconductor region and the fourth semiconductor region;
A trench buried insulating film buried in the trench;
Second conductivity provided between a part of the surface layer of the first semiconductor region and in contact with the first semiconductor region and the second semiconductor region and between the third semiconductor region and the trench. A fifth semiconductor region of the mold;
A source electrode in contact with the source region;
A drain electrode in contact with the drain region;
A floating electrode having a floating potential in contact with the fifth semiconductor region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first semiconductor region is provided on a support substrate via an insulating layer.   The semiconductor device according to claim 1, wherein the first semiconductor region is provided on a support substrate.   The semiconductor device according to claim 1, wherein the fifth semiconductor region is in contact with the trench.

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