JP5195547B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Various digital circuits such as microprocessors (MPU: Micro Processing Unit), RAM (Random Access Memory), ROM (Read Only Memory) and other storage devices, and communication systems large scale integration (VLSI: Very Large Scale Integration). In a clock adjustment circuit such as a delay-locked loop (DLL: Delay-Locked Loop) or a phase-locked loop (PLL), a semiconductor element for performing access control or clock adjustment (hereinafter referred to as a delay element) Is provided).

  12 to 15 are circuit diagrams showing conventional delay circuits using delay elements. For example, the conventional delay circuit includes an even number of inverters as shown in FIG. 12, and a first inverter 1001 and a second inverter 1002 are connected in series between the IN terminal 1011 and the OUT terminal 1012, for example. It is the composition connected to. Each inverter has, for example, a configuration of a complementary MOS (CMOS: Complementary MOS) in which a high-potential side p-channel MOSFET (Metal Oxide Field Effect Effect Transistor) and a low-potential side n-channel MOSFET are complementarily connected. It has become.

  13 is the same as the delay circuit illustrated in FIG. 12 except that a resistor 1021 connected between the first inverter 1001 and the second inverter 1002 and a node between the resistor 1021 and the second inverter 1002 are used. The first capacitor 1022 connected between the capacitor 1013 and the ground is provided, and the delay time is mainly determined by the time constant of the resistor 1021 and the first capacitor 1022 (hereinafter referred to as RC element). (For example, refer to Patent Document 1 below).

  The delay circuit illustrated in FIG. 14 is a current-driven delay circuit, and includes a first inverter 1001 and a second inverter connected in series between an IN terminal 1011 and an OUT terminal 1012. An inverter 1002, a first capacitor 1022 connected between a first inverter 1001 and a node 1013 between the first inverter 1001 and the second inverter 1002, and the ground; a power terminal on the low potential side of the first inverter 1001; The variable resistor 1023 and the second capacitor 1024 are connected in parallel. The configuration of the delay circuit shown in FIG. 14 is substantially equivalent in function to the delay circuit shown in FIG. 13 (see, for example, Non-Patent Document 1 below).

In the delay circuit shown in FIGS. 13 and 14, the delay time τ _d is determined by the discharge time when the n-channel MOSFET of the first inverter 1001 is turned on and the first capacitor 1022 is discharged. For example, in the delay circuit shown in FIG. 13, the delay time τ _d includes the resistance value R of the resistor 1021, the channel resistance R _ch of the n-channel MOSFET of the first inverter 1001, the power supply voltage V _DD , and the inversion of the first inverter 1001. Assuming that the threshold value V _Ti and the capacitance C _L of the first capacitor 1022 are satisfied, the value satisfies the following expression (1).

_{τ d = (R + R ch} ) · C L · ln (V DD / V Ti) = (R + R ch) · C L · ln2 ··· (1)

In the delay circuit shown in FIG. 14, the resistance value R is the resistance value of the variable resistor 1023. In addition, the capacitance C _L is the total capacitance of the first capacitor 1022 and the second capacitor 1024.

Further, in the conventional CMOS process, for example, when a sheet resistance such as a well region of a semiconductor element or a polycrystalline silicon gate is used as the variable resistance 1023, the resistance value is about several tens of ohms / square. If a higher resistance value is required, the channel resistance of the active device of the semiconductor element is used. The resistance value R _p of the channel resistance formed by the p-channel MOSFET is expressed as follows, assuming that the parameter K _p representing the transconductance, the gate-source voltage V _gs , the threshold voltage V _th , the channel width W, and the channel length L: 2) A value that satisfies the equation.

R _p = 1 / (K _p · (V _gs −V _th ) · (W / L)) (2)

In the CMOS process technology with the design rule of 2 μm, the parameter K _p representing the transconductance is calculated as about 1.7 × 10 ⁻⁵ (A / V ² ) by the SPICE parameter for circuit design (for example, the following) (Refer nonpatent literature 2.).

The delay circuit shown in FIG. 15 is a current limiting type delay circuit, and has a configuration in which a variable current source 1025 is provided instead of the variable resistor 1023 and the second capacitor 1024 of the delay circuit shown in FIG. (For example, see Non-Patent Document 1, Non-Patent Document 3, and Non-Patent Document 4 below). In such a delay circuit, determines the delay time tau _d by adjusting the current value I flowing to the delay circuit, the delay time tau _d is the power supply voltage V _DD, inversion threshold V _Ti and the first first inverter 1001 Assuming that the capacitance C _L of the capacitor 1022 is, the value almost satisfies the following expression (3). The adjustment of the current value I is generally realized by a current mirror configuration that outputs a current in the same direction as the input current.

τ _d = (V _DD −V _Ti ) C _L / I (3)

  In the technique of Non-Patent Document 3 described above, a delay of 2.6 ns to 76.3 ms is realized in a CMOS process technology with a design rule of 0.8 μm. Such delay elements can be used for a wide range of applications, for example, in various protection circuits of high-power semiconductor devices (see, for example, Patent Document 2 below).

  For example, an insulated gate bipolar transistor (LIGBT) formed on an SOI (Silicon-on-Insulator) substrate, which is a horizontal power semiconductor device for integrated circuits, has poor heat dissipation and Due to structural elements, the short-circuit withstand capability is smaller than that of an individual semiconductor device formed on a bulk substrate. Since a semiconductor device may be destroyed when a short circuit time (a time during which a large current flows and a high voltage is applied) required for normal operation is exceeded, it is desirable to provide a protection circuit.

  Various methods as described below have been proposed for a protection circuit of a semiconductor device. As a method for protecting a semiconductor device from overvoltage, for example, a method of connecting an avalanche diode to an individual semiconductor device such as a transistor or an IGBT (Insulated Gate Bipolar Transistor) has been proposed (for example, see Non-Patent Document 5 below). ).

  Also, as a method for protecting the semiconductor device from overcurrent, there is a method in which a sense IGBT is provided in the main IGBT, the current flowing through the main IGBT is monitored, and the gate voltage is cut off when the overcurrent flows through the main IGBT. (For example, refer to the following non-patent document 6).

  As another method for protecting a semiconductor device from overcurrent, a voltage between the collector and the emitter of the IGBT is monitored, and when an overvoltage is applied between the collector and the emitter, a current flowing through the IGBT is controlled (hereinafter referred to as an “overcurrent”). , Voltage sensing) has been proposed (for example, see Non-Patent Document 7 to Non-Patent Document 9 below).

  In the technique of Non-Patent Document 6 described above, there is a problem that power consumption is large in addition to the question of good compatibility between the sense IGBT and the main IGBT. Further, there is a problem that the current waveform is likely to vibrate due to the feedback loop at the time of current detection. On the other hand, in voltage sensing, the current detection accuracy is lower than in the technique of Non-Patent Document 6 described above, but the detection current has less noise and the entire apparatus can be simplified.

  The voltage sensing described above is provided with a sensor (hereinafter referred to as a voltage sensor) for monitoring an overvoltage applied to the semiconductor device. This voltage sensor uses a diode or a MOSFET provided with a gate oxide film having a film thickness comparable to that of a LOCOS (Local Oxidation of Silicon) oxide film (hereinafter referred to as a field MOSFET). In some cases, a semiconductor region (hereinafter referred to as a floating region) that is formed integrally with the semiconductor device and independent of the power supply voltage of the semiconductor device is used.

Each of the voltage sensors described above will be described. Note that in this specification and the accompanying drawings, a semiconductor in which n or p is mentioned means that an electron or a hole is a carrier, respectively. Further, n ⁺ and n ^- as such, subjected to n or p ⁺ or ^- that is, a relatively high impurity concentration or a relatively low impurity concentration than the impurity concentration of the semiconductor which they are not attached, respectively Represent.

FIG. 16 is a circuit diagram showing an example of conventional voltage sensing. As shown in FIG. 16, in voltage sensing using a diode, a diode 2002, a sensing resistor 2003, a comparator 2004, and a gate control circuit 2005 are provided in the IGBT 2001 in order to protect the IGBT 2001. The collector terminal of the IGBT 2001 is connected to the cathode terminal of the diode 2002 and the external output terminal 2007. The emitter terminal of the IGBT 2001 is grounded. A gate control circuit 2005 is connected to the gate terminal of the IGBT 2001. A control voltage input terminal (sense input) 2008 is connected to the anode terminal of the diode 2002 via a sensing resistor 2003. When the external output voltage V _{OUT at the} external output terminal 2007 is higher than the voltage V _{S at the} control voltage input terminal 2008, the sense voltage V _SEN at the node 2006 between the diode 2002 and the sensing resistor 2003 is set in advance by the comparator 2004. Compared with the set voltage V _REF , the gate control circuit 2005 is driven. The gate control circuit 2005 functions to cut off or reduce the gate voltage of the IGBT 2001 (see, for example, Non-Patent Document 7 below).

FIG. 17 is a circuit diagram showing another example of conventional voltage sensing. As shown in FIG. 17, in voltage sensing using a field MOSFET, a field MOSFET 2102, a sensing resistor 2103, and a gate control circuit 2105 are connected to the MOSFET 2101 in order to protect the MOSFET 2101. The drain terminal of the MOSFET 2101 is connected to the external output terminal 2104 and the gate terminal of the field MOSFET 2102. The source terminal of the MOSFET 2101 is grounded. The gate terminal of the MOSFET 2101 is connected to the gate control circuit 2105. The drain terminal of the field MOSFET 2102 is connected to the power supply voltage terminal 2106. The source terminal of the field MOSFET 2102 is connected to the sensing resistor 2103 and the gate control circuit 2105. The sensing resistor 2103 and the gate control circuit 2105 are grounded. The voltage across the sensing resistor 2103 is controlled by the gate-source voltage-drain-source current (V _gs -I _ds ) characteristic of the field MOSFET 2102 and is input to the gate control circuit 2105. Then, the gate voltage of the MOSFET 2101 is controlled by the gate control circuit 2105 (see, for example, Non-Patent Document 10 below).

  For example, a semiconductor device in which a thick oxide film such as a field MOSFET 2102 is used as a gate oxide film has been proposed. In a p-channel MOSFET, the thickness of the gate oxide film is set to 400 nm (for example, see Non-Patent Document 11 below). .

The gate threshold voltage of the MOSFET can be calculated from the thickness of the gate oxide film. For example, the gate threshold voltage V _th of the n-channel MOSFET includes the flat band voltage V _fb , the Fermi level and the Fermi of intrinsic silicon (Si). difference level [psi _B, the dielectric constant epsilon _s, unit charge q, When acceptor concentration N _a and the gate oxide film capacitance C _ox, is calculated as a value that satisfies the following equation (4).

V _th = V _fb + 2Ψ _B + (4ε _s qN _a Ψ _B ) ^0.5 / C _ox (4)

FIG. 18 is a circuit diagram showing another example of conventional voltage sensing. As shown in FIG. 18, in voltage sensing in which a floating region is provided in a vertical main IGBT 3000, a switch 3017 made of a MOSFET for controlling the gate voltage of the main IGBT 3000 is provided. On the front surface of the main IGBT 3000, a p base region 3004, a p ⁺ low resistance region 3005, an n ⁺ emitter region 3006, an emitter electrode 3007, a gate electrode 3008, and a gate are formed on part of the surface layer of the n ⁻ drift layer 3003. An insulating film 3009 is provided. On the back surface of main IGBT 3000, n buffer layer 3011, p ⁺ collector layer 3012, and collector electrode 3010 are provided on the back surface of n ⁻ drift layer 3003. A gate terminal 3015, an emitter terminal 3016, and a collector terminal 3018 are connected to the gate electrode 3008, the emitter electrode 3007, and the collector electrode 3010.

A part of the surface layer of the n ⁻ drift layer 3003 is provided with a p-type floating region 3013 apart from the p base region 3004. A floating electrode 3014 is provided on part of the surface of the floating region 3013. The floating electrode 3014 is electrically insulated from the gate electrode 3008 by the gate insulating film 3009. The floating region 3013 is connected to the gate terminal of the switch 3017 through the floating electrode 3014.

  The source terminal of the switch 3017 is connected to the emitter electrode 3007 of the main IGBT 3000. The drain terminal of the switch 3017 is connected to the gate electrode 3008 of the main IGBT 3000. The gate threshold voltage of switch 3017 is set according to the limit value of the collector-emitter voltage of main IGBT 3000. When the collector-emitter voltage of the main IGBT 3000 exceeds the limit value, the switch 3017 is turned on to control the gate voltage of the main IGBT 3000 (see, for example, Non-Patent Document 12 below).

A semiconductor device having a structure in which a floating region is provided in a horizontal semiconductor device to which the technique described in Non-Patent Document 12 described above is applied will be described. FIG. 19 is a cross-sectional view showing an example of conventional voltage sensing. The main IGBT 3100 shown in FIG. 19 is provided with an insulating layer 3002 on the front surface of the p ⁺ low resistivity substrate 3001. An n ⁻ drift layer 3003 is provided on the surface of the insulating layer 3002. A p base region 3004 and an n buffer region 3011 are provided apart from each other on the surface layer of the n ⁻ drift layer 3003. An n ⁺ emitter region 3006 is provided in part of the surface layer of the p base region 3004. A p ⁺ low resistance region 3005 is provided adjacent to the n ⁺ emitter region 3006. A part of the p ⁺ low resistance region 3005 occupies a part of the region below the n ⁺ emitter region 3006. A p ⁺ collector region 3012 is provided in part of the surface layer of the n buffer region 3011.

An emitter electrode 3007 is provided from a part of the surface of the n ⁺ emitter region 3006 to the surface of the p ⁺ low resistance region 3005. That is, the n ⁺ emitter region 3006 and the p ⁺ low resistance region 3005 are short-circuited by the emitter electrode 3007. A gate electrode 3008 is provided through a gate insulating film 3009 from a part of the surface of the n ⁺ emitter region 3006 to a part of the surface of the n ⁻ drift layer 3003. A collector electrode 3010 is provided on part of the surface of the p ⁺ collector region 3012. A back electrode 3020 is provided on the back surface of the p ⁺ low resistivity substrate 3001. Further, a gate terminal, an emitter terminal, and a collector terminal (not shown) are connected to the gate electrode 3008, the emitter electrode 3007, and the collector electrode 3010.

On the surface layer of n ⁻ drift layer 3003, a floating region 3013 is provided between p base region 3004 and n buffer layer 3011. A floating electrode 3014 is provided on the surface of the floating region 3013. The floating electrode 3014 functions as a voltage sensor. The n ⁻ drift layer 3003 is connected to the gate terminal of the switch 3017 through the floating electrode 3014. The source terminal of the switch 3017 is connected to the emitter electrode 3007 of the main IGBT 3100. The drain terminal of the switch 3017 is connected to the gate electrode 3008 of the main IGBT 3100. The method for controlling the gate voltage of the main IGBT 3100 is the same as the example shown in FIG.

  In the technologies of Non-Patent Document 7 to Non-Patent Document 10 described above (see FIGS. 16 and 17), a high voltage device for voltage sensing is required in addition to the main IGBT. On the other hand, the technique shown in Non-Patent Document 12 described above (see FIGS. 18 and 19) does not require a high voltage device for voltage sensing.

  FIG. 20 is a circuit diagram illustrating an example of a circuit having an output stage. The circuit shown in FIG. 20 is a circuit that drives, for example, a capacitor having an output stage, and the output stage has a so-called totem pole configuration. The circuit shown in FIG. 20 includes a first IGBT 4001, a second IGBT 4002, a capacitor 4003, a resistor 4004, a constant current source 4005, a start switch 4006, a high voltage power supply terminal 4007, a gate control signal input terminal 4008, and an external output terminal 4009. I have. The first IGBT 4001 and the second IGBT 4002 are the semiconductor devices shown in FIG. 18 or FIG. 19, for example.

  The collector terminal of the first IGBT 4001 is connected to the external output terminal 4009 and the emitter terminal of the second IGBT 4002. The emitter terminal of the first IGBT 4001 is grounded. The gate terminal of the first IGBT 4001 is connected to the gate control signal input terminal 4008. The collector terminal of the second IGBT 4002 is connected to a high voltage power supply terminal 4007 having a high voltage. A resistor 4004 is connected between the gate terminal of the second IGBT 4002 and the high-voltage external output terminal 4009. A capacitor 4003 is connected between the high voltage external output terminal 4009 and the grounding point. Further, a constant current source 4005 and a start switch 4006 are connected between the collector terminal and the gate terminal of the second IGBT 4002. In the case of protecting the output stage, the first IGBT 4001 and the second IGBT 4002 are each provided with a protection circuit.

  In such a circuit, when the first IGBT 4001 is turned off and the start switch 4006 is turned on, a voltage is applied from the circuit power supply connected to the high voltage power supply terminal 4007 and the second IGBT 4002 is turned on. Thus, the capacitor 4003 is charged. On the other hand, when the second IGBT 4002 is turned off and a voltage is applied from a circuit power supply connected to the gate control signal input terminal 4008, the first IGBT 4001 is turned on and the capacitor 4003 is discharged.

Japanese Patent Laid-Open No. 10-340998 (FIG. 38) Japanese Patent Application Laid-Open No. 11-097679

M. Maymandi-Nejad, 1 other, A monotonic digitally controlled delay element (USA), I Triple E Journal of Solids State (IEEE Journal of Solid-State Circuits), November 2005, Vol. 40, No. 11, p. 2212-2219 By R.M.J. Baker, H.W.Li, D.E. Boyce, CMOS circuit design, layout, and simulation (CMOS) Circuit Design, Layout, and Simulation), (USA), 1st edition, Wiley-IEE Press, 1998, p. 1-904 GD Kim, 3 other names, Arrow-Voltage, Low-Power CMOS Delay Element (A Low-Voltage, Low-Power CMOS Delay Element), (USA), I Triple EJournal of Solid-State Circuits, July 1996, Vol. 31, No. 7, p. 966-971 Y. Watanabe, 3 others, A New CR-Delay Circuit Technology For High Density and High-Speed DRAM's (A New CR-Delay Circuit Technology Highness and High DRAM-Spe (USA), I.Journal of Solid-State Circuits, August 1989, Vol. 24, No. 4, p. 905-910 T. Yamazaki, 2 others, The IGBT with monolithic overvoltage protection circuit (The IGBT with protection protection circuit, United States) on Power Semiconductor Devices and ICs 1993), 1993, p. 41-45 Y. Seki, 3 others, A new IGBT with a monolithic over-current voltage protection circuit (A new IGBT with a monolithic over-current protection circuit), (Switzerland), Power Semiconductor Device Symposium (Swiss 19) ISPSD '94: Proceedings of International Symposium on Power Semiconductor Devices and ICs 1994), 1994, p. 31-35 R.Letor, 1 other, Short Circuit Behavior of IGBT's Correlated to the Intrinsic Device Structure and on the application in the circuit in the application circuit), (USA), I Triple E Transactions on Industry Applications, March-April 1995, Vol. 31, No. 2, p. 234-239. S. Musumeci, 2 others, A New Gate Circuit Performing Fault Protection of IGBTs, Duaring Short Circuit Transforms (200), 2nd, 2), A New Gate Circuit Performing Fraction of IGBTs I. Triple E Industry Applications Conference (IEEE Industry Applications Conference 2002), 2002, Vol. 4, p. 2614-2621 C. Caramel, 4 others, Interaction Analyzes and Insulation Techniques for Short-Circuit Integrated Protection Structure (Instruction Analysis for Short-Circuit Int. Of the 18th International Symposium on Power Semiconductor Devices and IC's (Proceedings of the 18th International Symposium on Power Semiconductor Dev ices & IC's), June 4-8, 2006, p6-46. T. Terashima, 3 others, 60V field NMOS and PMOS transistors for the multi-voltage system integration (60V field NMOS and PMOS transistors for the multi-voltage system integration, power semiconductor symposium 1) Proceedings of 2001, International Symposium on Power Semiconductor Devices & IC's), 2001, p. 259-262 H. Sumida, 1 other, Breakdown Characteristics of a High-Voltage Lateral PMOS with LOCOS Gate on SOI (Breakdown Characteristics of a High-Voltage Lateral PMOS with LOCO, France ), The 7th International Symposium on Semiconductor Wafer Bonding Science, Technology, and Applications, 203rd Meeting of the Electrochemical Society (The Seventh International Symposium on Semiconductor Wafer) ding Science, Technology, and Applications, 203rd Meeting of the Electrochemical Society), 2003 April 29, In-Hwan Ji, 7 others, Anew 1200V PT-IGBT with protection circuit Employing the lateral IGBT and floating p-well voltage sensing scheme (A new 1200V PT-IGBT with protection circuit L floating p-well voltage sensing scheme, Extended Abstracts of the 2006 International Conference on Solid State Devices of the 2006 International Institute Conference on Solid State Devices and Materials), 2006 years, p. 512-513

  In the technique of Non-Patent Document 1 described above (see FIG. 14), the power consumption increases due to the variable resistor 1023. Further, depending on the resistance value of the variable resistor 1023, the source potential of the n-channel MOSFET of the first inverter 1001 becomes high, and the threshold voltage of the n-channel MOSFET of the first inverter 1001 varies due to the body effect. Therefore, it adversely affects the driving capability of the n-channel MOSFET of the first inverter 1001 and, consequently, the operation of the entire first inverter 1001. When the variable resistor 1023 is formed of a MOSFET and variable delay is performed, the parasitic capacitance of the source terminal of the n-channel MOSFET of the first inverter 1001 varies depending on the resistance value according to the operating state of the MOSFET. Therefore, an undesirable charge distribution (charge sharing) occurs between the first capacitor 1022 and the second capacitor 1024, and the monotonicity of the variable delay is deteriorated.

  Further, when a protection circuit is provided in an individual semiconductor device (discrete device), for example, it is necessary even if the delay time of the delay circuit as shown in FIG. 15 is set to 10 μs or more, which is a general short-circuit tolerance of the individual power semiconductor device Since there is only one protection circuit, the power consumption of the entire protection circuit is small enough not to cause a problem compared to the power consumption of the individual semiconductor device. The same applies to the case where individual semiconductor elements are used as the resistor 1021 and the first capacitor 1022 in the delay circuit shown in FIG.

  However, in a circuit having an output stage such as a display driving IC as shown in FIG. 20, when a protection circuit is provided in the output stage, it is necessary to provide a protection circuit for each output stage, which increases power consumption. End up. Further, in the case where the delay circuit shown in FIG. 15 is provided in the protection circuit, for example, the timing of the signal input to the IN terminal 1011 is irregular, so the variable current source 1025 needs to be operated at all times, and power consumption is reduced. Further increase.

  In the circuit shown in FIG. 20, the upper limit of the current value that can be passed through the first IGBT 4001 (hereinafter referred to as current capability) is 0.6 A, the current capability of the second IGBT 4002 is 0.2 A, and the capacitor 4003 When the capacitance is 200 pF, the resistance value of the resistor 4004 is about 5 kΩ, the constant current value of the constant current source 4005 is 0.1 A, and the voltage of the circuit power supply connected to the high voltage power supply terminal 4007 is about 150 V, the capacitor 4003 is charged. When turned on, the turn-on time during normal operation of the second IGBT 4002 is about 200 ns.

  Therefore, when the second IGBT 4002 continues to be in an overvoltage state (hereinafter referred to as an abnormal operation), in order not to disturb the normal operation of the output stage of the circuit shown in FIG. The gate voltage of the second IGBT 4002 needs to be pulled down after a delay time of 200 ns or longer has elapsed since the region 3013 (see FIG. 19) has become a high potential. That is, the switch 3017 (see FIG. 18 or FIG. 19) for turning on and off the second IGBT 4002 does not disturb the normal operation of the output stage and does not affect the gate voltage of the second IGBT 4002. It is necessary to have a delay time that can be turned on after a time and the gate voltage of the second IGBT 4002 can be pulled down. Usually, the first IGBT 4001 and the second IGBT 4002 have the same structure and are manufactured by the same manufacturing process. In addition, since the current capability of the first IGBT 4001 is larger than that of the second IGBT 4002, the discharge time of the load capacity of the capacitor 4003 is shorter than the charge time through the second IGBT 4002 after the first IGBT 4001 is turned on during normal operation. Therefore, the delay time of the switch 3017 (see FIG. 18 or FIG. 19) provided in the floating region 3013 of the first IGBT 4001 for turning on / off the first IGBT 4001 is also the delay of the switch 3017 provided in the second IGBT 4002. It may be as much as time.

  However, in the delay circuit of the inverter chain as shown in FIG. 12, the delay time that can be realized by a single-stage inverter is about several ns. Therefore, in order to realize a delay of about 200 ns, a very large number of inverters are connected. It is necessary to increase power consumption.

Further, the delay circuit shown in FIGS. 13 and 14 has the following problems. FIG. 11 shows calculated values of the resistance value and capacitance of the RC element when the delay time of 250 ns is realized in the conventional delay circuit. The required resistance value R _eff of the resistor 1021 is a difference (R _eff = R−R _ch ) obtained by subtracting the charging resistance R _ch from the resistance R of the entire circuit. When the delay time τ _d of the switch 3017 is set to 250 ns, for example, the resistance value R _eff of the resistor 1021 and the capacitance C _L of the first capacitor 1022 are calculated from the above-described equation (1), as shown in FIG. In addition, when the resistance value R _eff is 50 kΩ, 100 kΩ, and 200 kΩ, the capacitance C _L is 7.2 pF, 3.6 pF, and 1.8 pF, respectively.

When the channel resistance of a p-channel MOSFET formed by CMOS process technology is used as the resistor 1021, the ratio (W / L) of the channel width W to the channel length L is 1, and the threshold voltage is determined from the gate-source voltage V _gs. When the difference (V _gs −V _th ) obtained by subtracting V _th is 4 V, the resistance value R _p of the channel resistance is about 14.7 KΩ from the above-described equation (2). That is, even if the channel resistance of the p-channel MOSFET is used, the resistance value is about several tens KΩ, and it is difficult to realize several hundreds KΩ to 1 MΩ as shown in FIG.

Further, when a gate oxide film formed by CMOS process technology is used as the first capacitor 1022, the gate oxide film thickness _{Tox is set} to 20 nm, for example, and the capacitance of 7.2 pF shown in FIG. 11 is realized, for example. Therefore, the surface area of the gate oxide film is 4000 μm ² or more (≈24 μm / pF × 24 μm / pF × 7.2 pF), and the surface area of the gate oxide film becomes too large. That is, when the RC element used in the conventional delay circuit is formed by CMOS process technology, it is difficult to realize the resistance value and the capacitance as shown in FIG.

  In addition, each numerical value shown in this specification is a result obtained from a mixed-mode (Mix-mode) simulation waveform. The simulation of the semiconductor device having the IGBT structure uses TCAD (Technology CAD) in which the structure of the semiconductor device is divided by a minute region (mesh), and simulation is performed by setting desired conditions. Further, the SPICE parameters for circuit design shown in Non-Patent Document 2 described above are used for the simulation of other elements.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reduce the power consumption of a protection circuit in order to eliminate the above-described problems caused by the prior art. It is another object of the present invention to provide a semiconductor device capable of reducing the size of a protection circuit. It is another object of the present invention to provide a semiconductor device capable of providing a desired delay time in a protection circuit.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a first inverter, a second inverter, a third inverter, and an output terminal of the first inverter. And a first resistor connected between the input terminals of the second inverter, an external signal input terminal connected to the input terminal of the first inverter and the input terminal of the third inverter, An external signal output terminal connected to the output terminal of the second inverter, a fourth p-type MOS transistor using the output signal of the third inverter as a gate drive signal, and the first resistor through the first resistor A fourth n-type MOS transistor using the output signal of the first inverter as a gate drive signal; and a capacitor connected between the gate and drain of the fourth n-type MOS transistor. The drain of the fourth p-type MOS transistor is connected to the drain of the fourth n-type MOS transistor, and the source of the fourth p-type MOS transistor is connected to the first power supply, A source of the fourth n-type MOS transistor is grounded, and the fourth n-type MOS transistor is biased by an applied voltage.

  According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the floating gate and a floating electrode having a potential of the floating region are formed in the drift region; A first field effect transistor having a gate insulating film having a breakdown voltage greater than the voltage and having a threshold voltage higher than the voltage of the first power supply; and an output signal from the external signal output terminal as a gate drive signal And a second resistor connected between the source of the first field effect transistor and the ground, and the floating electrode includes the first field effect transistor. And the gate of the insulated gate transistor is connected to the second electric field. A drain or a drain of the transistor, the collector or drain of the insulated gate transistor is connected to a high voltage external output terminal, the source of the insulated gate transistor is grounded, and the first transistor The drain of the field effect transistor is connected to the first power supply, and the external signal input terminal is connected between the source of the first field effect transistor and the second resistor, The body potential of the first field effect transistor and the body potential of the second field effect transistor are ground potentials, and the source of the second field effect transistor is grounded.

  According to a third aspect of the present invention, there is provided a semiconductor device including: a first inverter, a second inverter, a third inverter, and an output terminal of the first inverter and an input terminal of the second inverter. First resistor, an external signal input terminal connected to an input terminal of the first inverter and an input terminal of the third inverter, and an external signal connected to an output terminal of the second inverter An output terminal, a fourth p-type MOS transistor using the output signal of the third inverter as a gate drive signal, and an output signal of the first inverter via the first resistor as a gate drive signal A fourth n-type MOS transistor; and a capacitor connected between a gate and a drain of the fourth n-type MOS transistor; and a drain of the fourth p-type MOS transistor. Is connected to the drain of the fourth n-type MOS transistor, the low-potential-side power supply terminal of the first inverter, the low-potential-side power supply terminal of the second inverter, and the third inverter And a source of the fourth n-type MOS transistor are connected to a high-voltage external output terminal, the high-potential-side power supply terminal of the first inverter, and the second inverter The power source terminal on the high potential side, the power source terminal on the high potential side of the third inverter, and the source of the fourth p-type MOS transistor are connected between the first power source and the ground with respect to the potential of the external output terminal. It is characterized by being connected to a second power source having a potential that is higher by the potential difference.

  According to a fourth aspect of the present invention, there is provided a semiconductor device according to the third aspect of the invention, wherein the floating gate and a floating electrode having a potential of the floating region are formed in the drift region, and the floating electrode A first field effect transistor having a gate insulating film having a breakdown voltage greater than the voltage and having a threshold voltage higher than the voltage of the first power supply; and an output signal from the external signal output terminal as a gate drive signal And a second resistor connected between the source of the first field effect transistor and the external output terminal, and the floating electrode includes the first field effect transistor 1 is connected to the gate and drain of the field effect transistor, and the insulated gate transistor The gate is connected to the drain of the second field effect transistor, the collector or drain of the insulated gate transistor is connected to a third power source having a high voltage, and the source of the insulated gate transistor is The external signal input terminal is connected between the source of the first field effect transistor and the second resistor, and the external signal input terminal of the first field effect transistor is connected to the external output terminal. The body potential and the body potential of the second field effect transistor have the potential of the external output terminal, and the source of the second field effect transistor is connected to the external output terminal.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the second power source is connected to the external output terminal via a third resistor. A source and body of a third field effect transistor are connected between a power source and the third resistor, and the gate and drain of the third field effect transistor are connected to the anode of the first Zener diode and the third resistor. 2 is connected to the cathode of the Zener diode, the cathode of the first Zener diode is connected to the floating electrode, and the anode of the second Zener diode is connected to the external output terminal. It is characterized by that.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the second power source is connected to the external output terminal via a third resistor, and the second power source is connected to the second power source. A source and body of a third field effect transistor are connected between a power source and the third resistor, and the gate and drain of the third field effect transistor are connected to the cathode of the diode and the second Zener diode. The anode of the diode is connected to the floating electrode, the anode of the second Zener diode is connected to the external output terminal, and the diode is It is a diode or a plurality of diodes connected in series in the same direction.

  According to the invention of each claim described above, by providing a capacitor between the gate and the drain of the fourth n-type MOS transistor in a biased state, the capacitance between the gate and the drain of the fourth n-type MOS transistor ( By using the feedback capacitance, the capacitance of the capacitor provided between the first inverter and the second inverter can be made equivalently larger than the physical capacitance of the capacitor. Thereby, since the time constant of the RC element connected between the first inverter and the second inverter can be made larger than before, the external signal output terminal after the signal is input to the external signal input terminal The time (delay time) until the signal is output can be made longer than that of the conventional semiconductor device. Further, even if the physical time constant of the RC element is reduced by downsizing the capacitor, downsizing the first resistor, or not installing the first resistor, the same as in the conventional semiconductor device The above delay time can be set. As a result, the entire semiconductor device can be reduced in size. Further, by reducing the size of the RC element, power consumption can be reduced as compared with the conventional semiconductor device.

  According to the semiconductor device of the present invention, the power consumption of the protection circuit can be reduced. In addition, the protection circuit can be reduced in size. Further, the protection circuit can provide a desired delay time.

FIG. 3 is a circuit diagram showing a delay circuit according to the first exemplary embodiment; FIG. 3 is a circuit diagram showing a protection circuit using the delay circuit according to the first exemplary embodiment; 1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment; FIG. 4 is a circuit diagram showing a delay circuit according to a second embodiment; FIG. 5 is a circuit diagram showing a protection circuit using a delay circuit according to a second embodiment; FIG. 6 is a circuit diagram showing a power supply used in the delay circuit shown in FIG. 5. FIG. 6 is a circuit diagram showing another example of a power supply used in the delay circuit shown in FIG. 5. FIG. 6 is a characteristic diagram showing delay characteristics in the delay circuit according to the first embodiment; It is a characteristic view which shows the delay characteristic in the conventional delay circuit. It is a characteristic view which shows the delay characteristic in the conventional delay circuit. It is a figure which shows the calculated value of RC element when implement | achieving delay time 250ns in the conventional delay circuit. It is a circuit diagram which shows the conventional delay circuit using a delay element. It is a circuit diagram which shows the conventional delay circuit using a delay element. It is a circuit diagram which shows the conventional delay circuit using a delay element. It is a circuit diagram which shows the conventional delay circuit using a delay element. It is a circuit diagram which shows an example of the conventional voltage sensing. It is a circuit diagram which shows another example of the conventional voltage sensing. It is a circuit diagram which shows another example of the conventional voltage sensing. It is sectional drawing which shows an example of the conventional voltage sensing. It is a circuit diagram which shows an example of the circuit which has an output stage.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a circuit diagram of the delay circuit according to the first embodiment. 1 protects the output stage of a circuit having an output stage as shown in FIG. 20 (hereinafter referred to as a power IC circuit), for example, an overvoltage of a semiconductor device such as an IGBT provided as the output stage. A first inverter 101 having a CMOS structure in which a first p-channel MOSFET 1 and a first n-channel MOSFET 2 are connected so as to complement each other, and a second p-channel MOSFET 3. And a second inverter 102 having a CMOS structure in which the second n-channel MOSFET 4 and the second n-channel MOSFET 4 are connected so as to complement each other, and a second inverter 102 having a CMOS structure in which the third p-channel MOSFET 5 and the third n-channel MOSFET 6 are connected so as to complement each other. 3 inverters 103, a fourth p-channel MOSFET 7, and a fourth n-channel MOSFET 8 , Resistance to determine the delay time of the delay circuit 100 is configured with (hereinafter, a delay resistor to) 121 and the capacitor 122 and. Each p-channel MOSFET corresponds to a p-type MOS transistor. Each n-channel MOSFET corresponds to an n-type MOS transistor. The delay resistor 121 corresponds to a first resistor.

  In the first inverter 101, the source terminal of the first p-channel MOSFET 1 is kept at the power supply potential of the logic circuit (hereinafter referred to as logic circuit power supply). The source terminal of the first n-channel MOSFET 2 is grounded. Similarly, in the second inverter 102 and the third inverter 103, the source terminal of the p-channel MOSFET is kept at the logic circuit power supply potential, and the source terminal of the n-channel MOSFET is grounded. The logic circuit power supply corresponds to the first power supply.

  A delay resistor 121 is connected between the output terminal of the first inverter 101 (MOSFET drain terminal) and the input terminal of the second inverter 102 (MOSFET gate terminal). The input terminal (MOSFET gate terminal) of the first inverter 101 and the input terminal (MOSFET gate terminal) of the third inverter 103 are connected to the IN terminal 111. The output terminal (the drain terminal of the MOSFET) of the second inverter 102 is connected to the OUT terminal 112. The IN terminal 111 corresponds to an external signal input terminal. The OUT terminal 112 corresponds to an external signal output terminal.

  The output terminal (the drain terminal of the MOSFET) of the third inverter 103 is connected to the gate terminal of the fourth p-channel MOSFET 7. The drain terminal of the fourth p-channel MOSFET 7 is connected to the drain terminal of the fourth n-channel MOSFET 8. The source terminal of the fourth p-channel MOSFET 7 is connected to the logic circuit power supply.

  The gate terminal of the fourth n-channel MOSFET 8 is connected to a node 113 between the delay resistor 121 and the input terminal of the second inverter 102. A capacitor 122 is connected between the gate terminal and the drain terminal of the fourth n-channel MOSFET 8. The source terminal of the fourth n-channel MOSFET 8 is grounded.

  At least the first inverter 101, the second inverter 102, and the third inverter 103 that constitute the delay circuit 100 are connected to the protection circuit by the IN terminal 111 and the OUT terminal 112, and have a CMOS structure that is driven by a single power source. The configuration is a logic integrated circuit (hereinafter referred to as logic CMOS).

  In the first inverter 101, the gate width of the first n-channel MOSFET 2 is preferably larger than the gate width of the first p-channel MOSFET 1. The reason is that the gate threshold voltage of the first inverter 101 can be lowered. The second inverter 102 and the third inverter 103 are preferably set to have the same setting as the first inverter 101 for the same reason as the first inverter 101. Here, the gate width refers to the length of the gate electrode in the direction perpendicular to the direction of current flow.

  Further, the capacitance of the capacitor 122 is equivalent to a capacitance equivalent to the physical capacitance of the capacitor 122 (hereinafter, equivalent capacitance) by using the gate-drain capacitance (feedback capacitance) of the fourth n-channel MOSFET 8. And).

In such a delay circuit 100, when an input voltage is input to the IN terminal 111, while the potentials of the input terminal of the first inverter 101 and the input terminal of the third inverter 103 are close to the ground potential, the following is performed. To work. In the first inverter 101, the first p-channel MOSFET 1 is turned on, and the potential of the output terminal of the first inverter 101 becomes the logic circuit power supply potential V _DL . The charge from the power supply terminal on the high potential side of the first inverter 101 is charged into the gate-source capacitance of the fourth n-channel MOSFET 8 via the delay resistor 121. The gate voltage of the fourth n-channel MOSFET 8 becomes larger than the gate threshold voltage of the fourth n-channel MOSFET 8, and the fourth n-channel MOSFET 8 is turned on. Since the potential of the output terminal of the first inverter 101 is the logic circuit power supply potential V _DL , the potential of the input terminal of the second inverter 102 becomes the logic circuit power supply potential V _DL and the second n-channel MOSFET 4 is turned on. Become. Charge from the power supply terminal on the high potential side of the first inverter 101 is charged in the gate-drain capacitance of the second n-channel MOSFET 4 via the delay resistor 121. Further, in the third inverter 103, the third p-channel MOSFET 5 is turned on, and the potential of the output terminal of the third inverter 103 becomes the logic circuit power supply potential V _DL . The potential of the gate terminal of the fourth p-channel MOSFET 7 becomes the logic circuit power supply potential V _DL , and the fourth p-channel MOSFET 7 is turned off.

Then, the potentials of the input terminal of the first inverter 101 and the input terminal of the third inverter 103 exceed the inversion threshold value of the first inverter 101 and the inversion threshold value of the third inverter 103, respectively, and the logic circuit power supply potential V _DL. The delay circuit 100 operates as follows. In the first inverter 101, the first p-channel MOSFET 1 is turned off and the first n-channel MOSFET 2 is turned on. The gate charges of the fourth n-channel MOSFET 8 gate-drain capacitance and the second n-channel MOSFET 4 gate-drain capacitance are discharged to the ground via the delay resistor 121 and the first n-channel MOSFET 2. In the third inverter 103, the third p-channel MOSFET 5 is turned off and the third n-channel MOSFET 6 is turned on. The potential of the output terminal of the third inverter 103 is close to the ground potential, and the gate terminal of the fourth p-channel MOSFET 7 is grounded via the output terminal of the third inverter 103 and the third n-channel MOSFET 6. When the voltage between the source and gate of the fourth p-channel MOSFET 7 increases, the fourth p-channel MOSFET 7 is turned on, and the potential of the drain terminal of the fourth n-channel MOSFET 8 becomes the logic circuit power supply potential V _DL . While the potential at the node 113 is higher than the threshold voltage of the fourth n-channel MOSFET 8, the fourth n-channel MOSFET 8 is in a saturation region (drain-source voltage V _ds > gate-source voltage V _gs −threshold voltage V _th ). And the feedback capacitance of the fourth n-channel MOSFET 8 is amplified. Due to the feedback capacitance of the fourth n-channel MOSFET 8, the capacitance of the capacitor 122 becomes an equivalent capacitance C _{L that} is equivalently larger than the physical capacitance C _M of the capacitor 122 and satisfies the following equation (5). The voltage amplification factor A _V of the fourth n-channel MOSFET 8 and the capacitance C _M of the capacitor 122 are assumed.

C _L = A _V · C _M (5)

Then, electric charges from the logic circuit power supply are accumulated in the capacitor 122 via the fourth p-channel MOSFET 7. The electric charge accumulated in the capacitor 122 is discharged to the ground via the delay resistor 121 and the first n-channel MOSFET 2, and the potential of the input terminal of the second inverter 102 becomes a potential close to the ground potential. The potential of the output terminal of the second inverter 102 becomes close to the logic circuit power supply potential V _DL , and an output voltage is output from the OUT terminal 112.

  Thus, in the delay circuit 100, the time from when the input voltage is input to the IN terminal 111 and when the output voltage is output from the OUT terminal 112 is the delay time.

  Next, a protection circuit provided with the above-described delay circuit 100 will be described. FIG. 2 is a circuit diagram illustrating a protection circuit using the delay circuit according to the first embodiment. The protection circuit shown in FIG. 2 is a circuit that protects the IGBT 200 by a signal from a floating electrode provided in the IGBT 200, and includes a first switch 21, a voltage dividing resistor 22, a delay circuit 100, and a second switch 23. ing. The IGBT 200 includes a floating region and a floating electrode having a potential of the floating region, and is used as, for example, a first IGBT (see FIG. 20) that is a low-side output of an output stage in a power IC circuit. For example, n-channel MOSFETs are used for the first switch 21 and the second switch 23.

  In such a protection circuit, the gate terminal of the IGBT 200 is connected to the drain terminal of the second switch 23 and the gate control signal input terminal 24. The collector terminal of the IGBT 200 is connected to a high withstand voltage external output terminal (see FIG. 20). The floating electrode of the IGBT 200 is connected to the gate terminal of the first switch 21. The emitter terminal of the IGBT 200 is grounded. The IGBT 200 corresponds to an insulated gate transistor. The configuration of the IGBT 200 will be described later.

  The first switch 21 and the voltage dividing resistor 22 convert a detection signal from the floating electrode of the IGBT 200 into a voltage value that can be input to the delay circuit 100, that is, a voltage value that can be input to the logic circuit (hereinafter referred to as voltage dividing). Circuit). In the voltage dividing circuit, the source terminal of the first switch 21 and one end of the voltage dividing resistor 22 are connected. The other end of the voltage dividing resistor 22 is grounded. The drain terminal of the first switch 21 is connected to the logic circuit power supply. The potential (body potential) of the semiconductor substrate used for the first switch 21 is the ground potential. The first switch 21 corresponds to a first field effect transistor. The voltage dividing resistor 22 corresponds to a second resistor.

  The IN terminal of the delay circuit 100 is connected between the source terminal of the first switch 21 and the voltage dividing resistor 22. The OUT terminal of the delay circuit 100 is connected to the gate terminal of the second switch 23. The source terminal of the second switch 23 is grounded. The body potential of the second switch 23 is the ground potential. The second switch 23 corresponds to a second field effect transistor.

In the protection circuit, when an overvoltage is applied to the collector electrode of the IGBT 200, a signal of the floating electrode of the IGBT 200 is detected. This detection signal is converted into a signal that can be input to the logic circuit in the voltage dividing circuit and input to the delay circuit 100. Since the state in which overvoltage is applied to the floating electrode of the IGBT 200 continues (during abnormal operation), when the delay time preset in the delay circuit 100 has elapsed, the output voltage from the OUT terminal of the delay circuit 100 becomes the second voltage. Applied to the gate terminal of the switch 23, the second switch 23 is turned on. When the current capability of the second switch 23 is larger than the current capability at the gate control signal input terminal 24, the gate terminal of the IGBT 200 is grounded, and the gate voltage of the IGBT 200 is pulled down. The external output voltage V _OUT of the external output terminal 114 falls following the falling edge (Falling Edge) of the floating voltage V _P. Therefore, for example, when the abnormal operation of the IGBT 200 is set as a case where 200 ns or more has elapsed since the overvoltage was applied to the IGBT 200, the short-circuit withstand capability of the IGBT 200 itself may be about 300 ns, for example.

  The first switch 21 is preferably provided with a gate insulating film that is thicker than the gate insulating film of the logic CMOS and has a higher breakdown voltage than the voltage of the floating electrode of the IGBT 200 (hereinafter referred to as a floating voltage). The gate threshold voltage of the first switch 21 is preferably set to a voltage value larger than the logic circuit power supply voltage. This is because the floating voltage of the IGBT 200 is higher than the logic circuit power supply voltage. By setting the first switch 21 as described above, the floating voltage of the IGBT 200 can be converted into a voltage value that can be input to the second switch 23, that is, a voltage value that can be input to the logic circuit. . Note that a level shift circuit may be provided instead of the voltage dividing circuit. The first switch 21 may be a field MOSFET provided with a LOCOS oxide film as a gate oxide film.

Next, the configuration of the IGBT 200 described above will be described. FIG. 3 is a cross-sectional view illustrating an example of the semiconductor device according to the first embodiment. The lateral n-channel IGBT 200 shown in FIG. 3 is manufactured using an SOI substrate. The SOI substrate has a structure in which an insulating layer 202 made of an oxide film or the like and an n ⁻ drift region 203a are laminated on a p support substrate 201 in this order.

N well region 203b is provided in a part of the surface layer of n ⁻ drift region 203a. n-well region 203b is, n ^- are more heavily doped than the drift region 203a, n ^- have a lower resistivity than the drift region 203a. p base region 204, n ^- the part of the surface layer of the drift region 203a, n ^- is provided in contact with the drift region 203a and the n-well region 203b.

The gate electrode 208 is provided on a part of the p base region 204 and the surface of the n well region 203b via a gate insulating film 209. The n ⁺ emitter region 206 is provided in a part of the p base region 204 so as to be aligned with the end of the gate electrode 208 on the p base region side (the end on the n ⁺ emitter region 206 in FIG. 3). .

Some The p base region 204, and p ⁺ low resistance region 205a formed so as to occupy the lower n ⁺ emitter region 206, the p ⁺ base contact region 205b which is adjacent to the n ⁺ emitter region 206 is provided ing. The p ⁺ low resistance region 205a is desirably formed so as to occupy the lower side of the n ⁺ emitter region 206 in a range that does not affect the threshold as in the present embodiment.

Outside the end of the gate electrode 208 on the p base region side, a gate sidewall spacer region 218 made of an oxide film or a nitride film is provided in contact with the end. The p ⁺ low resistance region 205a is formed so as not to enter the region where the channel is formed by using the gate sidewall spacer region 218 so as not to affect the threshold value. A channel is formed at the interface between the gate insulating film 209 and the p base region 204 between the n ⁺ emitter region 206 and the n well region 203b when the gate voltage exceeds the gate threshold voltage.

Further, n buffer region 211 is provided in a part of the surface layer of n ⁻ drift region 203 a, apart from n well region 203 b and p base region 204. n buffer region 211, n ^- are more heavily doped than the drift region 203a, n ^- have a lower resistivity than the drift region 203a. The n buffer region 211, together with the n ⁻ drift region 203a and the n well region 203b, becomes a drift region that holds the breakdown voltage of the device. As described above, this device is a punch-through type IGBT having the n buffer region 211.

The p ⁺ collector region 212 is provided in a part of the n buffer region 211 and is isolated from the n ⁻ drift region 203 a by the n buffer region 211. A trench 216 is formed between n well region 203b and p base region 204 and n buffer region 211 so as to be separated from n well region 203b and n buffer region 211 so as not to penetrate n ⁻ drift region 203a. Yes. The trench 216 is filled with a trench buried insulating film 217 such as an oxide film.

The p-type floating region 213 is provided on a part of the surface layer of the n ⁻ drift region 203 a between the p base region 204 and the trench 216 in contact with the n ⁻ drift region 203 a and the n well region 203 b. .

The emitter electrode 207 is in contact with both the n ⁺ emitter region 206 and the p ⁺ base contact region 205b, and short-circuits the p ⁺ base contact region 205b and the n ⁺ emitter region 206. Collector electrode 210 is in contact with p ⁺ collector region 212. The floating electrode 214 is in contact with the floating region 213. In FIG. 3, reference numeral 219 denotes an insulating film cover layer such as an oxide film provided to reduce plasma etching damage to the gate insulating film 209 during manufacturing, and reference numeral 215 denotes an interlayer insulating film.

Note that the above-described lateral n-channel IGBT 200 may have a configuration in which the n ⁻ drift region 203 a is stacked on the p support substrate 201 without using the SOI substrate. Further, instead of a lateral IGBT structure, a lateral semiconductor device such as an LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor structure or a vertical IGBT structure may be used.

  As described above, according to the first embodiment, the gate of the fourth n-channel MOSFET 8 is provided by providing the capacitor 122 between the gate terminal and the drain terminal of the biased fourth n-channel MOSFET 8. -Capacitance of the capacitor 122 can be equivalently larger than the physical capacitance of the capacitor 122 due to the capacitance between the drains (feedback capacitance). As a result, the time constant of the RC element connected between the first inverter 101 and the second inverter 102 can be made larger than before, so that after the signal is input to the IN terminal 111, the OUT terminal 112 The time (delay time) from when the signal is output can be made longer than that of the conventional delay circuit. In addition, even if the physical time constant of the RC element is reduced by reducing the size of the capacitor 122, reducing the size of the delay resistor 121, or not installing it, the delay time equal to or longer than that of the conventional delay circuit is realized. can do. As a result, the entire delay circuit 100 can be reduced in size. Further, by reducing the size of the RC element, the power consumption can be reduced as compared with the conventional delay circuit. In each inverter, the gate threshold voltage of each inverter can be lowered by making the gate width of the n-channel MOSFET larger than the gate width of the p-channel MOSFET. Thereby, the power consumption in each inverter can be reduced. Further, by making the gate insulating film of the first switch 21 thicker than the gate insulating film of the logic CMOS, it is possible to prevent the gate oxide film of the first switch 21 from being destroyed. In addition, the breakdown of the first switch 21 can be prevented by setting the breakdown voltage of the gate insulating film of the first switch 21 to a breakdown voltage larger than the floating voltage of the IGBT 200. Further, by setting the gate threshold voltage of the first switch 21 to a voltage value larger than the logic circuit power supply voltage, it is possible to prevent the protection circuit from being driven when the overvoltage is not applied to the IGBT 200. . In the protection circuit, the short-circuit withstand capability of the IGBT 200 normally needs to be about several μs. However, the short-circuit withstand capability of the IGBT 200 can be made shorter than before by using the protection circuit configuration of the first embodiment. . Thereby, in the IGBT 200, it is possible to improve the low on-voltage characteristics that are in a trade-off relationship with the short-circuit tolerance.

(Embodiment 2)
FIG. 4 is a circuit diagram of the delay circuit according to the second embodiment. In the delay circuit illustrated in FIG. 1, the low-potential-side power supply terminal of the first inverter 101, the low-potential-side power supply terminal of the second inverter 102, the low-potential-side power supply terminal of the third inverter 103, and the fourth The source terminal of the n-channel MOSFET 8 may be connected to the high voltage external output terminal 114. The configuration of delay circuit 300 shown in FIG. 4 is a logic CMOS configuration as in the first embodiment. The logic CMOS according to the second embodiment corresponds to a second integrated semiconductor device.

In such a delay circuit 300, the power supply terminal on the high potential side of the fourth inverter 104 has a voltage larger than the external output voltage V _{OUT at} the external output terminal 114 by a potential difference between the logic circuit power supply and the ground (hereinafter referred to as delay). It is connected to a power source (hereinafter referred to as a delay circuit power source) having V _D (referred to as circuit voltage). The power terminal on the low potential side of the fourth inverter 104 is connected to the external output terminal 114. Similarly, in the fifth inverter 105 and the sixth inverter 106, the power terminal on the high potential side is connected to the delay circuit power supply, and the power terminal on the low potential side is connected to the external output terminal 114. The configuration of fourth inverter 104 to sixth inverter 106 is the same as that of first inverter 101 to third inverter 103 in Embodiment 1. The configuration and operation of the delay circuit 300 are the same as those in the first embodiment. The delay circuit power supply corresponds to a second power supply.

  Next, a protection circuit provided with the above-described delay circuit 300 will be described. FIG. 5 is a circuit diagram showing a protection circuit using the delay circuit according to the second embodiment. The protection circuit shown in FIG. 5 is a circuit for protecting the IGBT 400 used as the second IGBT (see FIG. 20) that is the high-side output of the output stage in the power IC circuit, for example. The configuration of IGBT 400 is the same as that of IGBT 200 in the first embodiment.

  In such a protection circuit, the collector terminal of the IGBT 400 is connected to the high voltage power supply terminal 25 of the power IC circuit having a high voltage. The emitter terminal of the IGBT 400 is connected to the external output terminal 114. The configuration of IGBT 400 is the same as that of the first embodiment. The high voltage power supply terminal 25 corresponds to a third power supply.

  The drain terminal of the first switch 21 is connected to the floating electrode of the IGBT 400. The body potential of the first switch 21 is kept at the potential of the external output terminal 114. The other end of the voltage dividing resistor 22 is connected to the external output terminal 114.

  The IN terminal of the delay circuit 300 is connected between the source terminal of the first switch 21 and the voltage dividing resistor 22. The OUT terminal of the delay circuit 300 is connected to the gate terminal of the second switch 23. The source terminal of the second switch 23 is connected to the external output terminal 114. The body potential of the second switch 23 is kept at the potential of the external output terminal 114. Other configurations and operations are the same as those of the delay circuit 200 of the first embodiment.

Next, a circuit for controlling the voltage value of the delay circuit power supply (hereinafter referred to as a voltage forming circuit) will be described. FIG. 6 is a circuit diagram showing a power supply used in the delay circuit shown in FIG. The voltage forming circuit shown in FIG. 6 is a circuit that controls the voltage value at the delay circuit power supply terminal 115 to be the delay circuit voltage V _D , and includes the first Zener diode 31, the second Zener diode 32, the MOSFET 33, and the control. The resistor 34 is configured. The control resistor 34 corresponds to a third resistor. The MOSFET 33 corresponds to a third field effect transistor.

  In such a voltage forming circuit, the delay circuit power supply terminal 115 is connected to one end of the control resistor 34. The other end of the control resistor 34 is connected to the external output terminal 114. A source terminal of the MOSFET 33 is connected between the delay circuit power supply terminal 115 and the control resistor 34. The gate terminal and drain terminal of the MOSFET 33 are connected to the anode terminal of the first Zener diode 31 and the cathode terminal of the second Zener diode 32. The body potential of the MOSFET 33 is kept at the potential of the delay circuit power supply terminal 115. The cathode terminal of the first Zener diode 31 is connected to the floating electrode terminal 116 of the IGBT 400. The anode terminal of the second Zener diode 32 is connected to the external output terminal 114. The reverse breakdown voltage of the first Zener diode 31 is set smaller than the reverse breakdown voltage of the second Zener diode 32. The breakdown voltage of the second Zener diode 32 is set lower than the sum of the breakdown voltage of the MOSFET 33 and the voltage drop generated across the control resistor 34. Further, it is set larger than the sum of the voltage between the source and drain during normal operation of the MOSFET 33 and the voltage drop generated at both ends of the control resistor 34.

The first Zener diode 31 converts the input voltage from the floating electrode terminal 116 into a voltage that can be controlled by the voltage forming circuit. By providing the first Zener diode 31, the drain voltage applied to the MOSFET 33 can be made a voltage (V _P −V _DZ1 ) that is smaller than the floating voltage V _P by the breakdown voltage V _{DZ1 of} the first Zener diode 31. Further, by providing the second Zener diode 32, the MOSFET 33 can be protected from destruction due to overvoltage.

The MOSFET 33 controls the current flowing through the control resistor 34, and the value of the current flowing through the control resistor 34 can be determined by the size of the MOSFET 33. The resistance value of the control resistor 34 is set so that the potential difference generated at both ends of the control resistor 34 due to the voltage drop of the control resistor 34 is approximately the same as the potential difference between the logic circuit power supply and the ground. Thereby, the voltage of the delay circuit power supply terminal 115 can be kept at the delay circuit voltage V _D. When the resistance value R of the control resistor 34 is the current value I flowing through the control resistor 34, the resistance value R satisfies the following equation (6).

R = (V _D −V _OUT ) / I (6)

In such a voltage generating circuit, when the high floating voltage V _P than the breakdown voltage of the first zener diode 31 is applied to the floating electrode terminal 116 of the IGBT 400, the floating voltage V _P is the first Zener diode 31 The voltage is _{reduced by the} breakdown voltage V _DZ1 (V _P −V _DZ1 ) and applied to the drain terminal of the MOSFET 33. When the voltage applied to the drain terminal of the MOSFET 33 becomes larger than the gate threshold voltage of the MOSFET 33, the first current I ₁ flows through the MOSFET 33. Then, the second current I ₂ flows through the control resistor 34. At both ends of the control resistor 34, a voltage drop comparable to the potential difference between the logic circuit power supply and the ground occurs. The second current I ₂ is limited by the size of the MOSFET 33. A current having a difference (I ₁ −I ₂ ) between the _first current I ₁ and the second current I ₂ is supplied as a power supply current from the delay circuit power supply terminal 115 to the delay circuit. In this way, a voltage (delay circuit) having a potential greater than the external output voltage V _OUT output from the external output terminal 114 is approximately equal to the potential difference between the logic circuit power source and the ground. Voltage) V _D is supplied.

  FIG. 7 is a circuit diagram showing another example of the power supply used in the delay circuit shown in FIG. In the voltage forming circuit shown in FIG. 7, the first Zener diode 31 may be a single diode or a plurality of diodes (hereinafter referred to as a diode chain) 35 connected in series in the same direction.

  In the voltage forming circuit shown in FIG. 7, the gate terminal and the drain terminal of the MOSFET 33 are connected to the cathode terminal of the diode on the cathode side of the diode chain 35. The anode terminal of the endmost diode on the anode side of the diode chain 35 is connected to the floating electrode terminal 116 of the IGBT 400. The forward voltage drop of the diode chain 35 is set to be smaller than the withstand voltage of the reverse voltage of the second Zener diode 32. The effect of the diode chain 35 is the same as that of the first Zener diode 31. Other configurations and operations are the same as those of the voltage forming circuit shown in FIG.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, by providing a voltage forming circuit connected to the floating electrode of the IGBT 400, the external output terminal 114 of the power IC circuit, and the delay circuit power supply of the delay circuit 300, a delay circuit voltage can be created from the floating voltage of the IGBT 400.

Next, the delay characteristics of the delay circuit according to the present invention will be described with reference to the first embodiment (hereinafter referred to as an example). FIG. 8 is a characteristic diagram showing delay characteristics in the delay circuit according to the first embodiment. In the protection circuit shown in FIG. 2, the current capability of the IGBT 200 is set to 0.6A. An n-channel MOSFET was used as the first switch 21 and its gate threshold voltage was 6V. In the case where a field MOSFET is used, the gate threshold voltage is calculated from the above equation (4) by setting the gate oxide film and the acceptor concentration of the first switch 21 to 400 nm and 1 × 10 ¹⁶ cm ⁻³ , respectively. Can be calculated. The ratio between the gate width and the gate length of the first switch 21 (= gate width (μm) / gate length (μm): hereinafter referred to as gate dimension ratio) was 40/2. An n-channel MOSFET was used as the second switch 23, and its gate threshold voltage was about 1V. The gate size ratio of the second switch 23 was 15/2. The resistance value of the voltage dividing resistor 22 was 50 kΩ. The gate input capacitance of the IGBT 200 was 24 pF. The logic circuit power supply voltage V _DL was set to 5V.

  Further, in the delay circuit 100 shown in FIG. 1, the first p-channel MOSFET 1, the first n-channel MOSFET 2, the second p-channel MOSFET 3, the second n-channel MOSFET 4, the third p-channel MOSFET 5, and the third n The gate dimensional ratios of the channel MOSFET 6, the fourth p-channel MOSFET 7 and the fourth n-channel MOSFET 8 are 5/2, 15/2, 4/2, 8/2, 3/2, 12/2, and 20/2, respectively. And 20/2. The resistance value of the delay resistor 121 was zero, and the capacitance of the capacitor 122 was 1.2 pF. Here, the gate width is as described above. The gate length refers to the length of the gate electrode in the direction in which the MOSFET current flows.

From the results shown in FIG. 8, since the detected floating voltage V _P of the IGBT 200, the time from the power IC circuit of the external output terminal 114 to the external output voltage V _OUT is output (delay time), it is a 205ns I found out that Further, it was found that the external output voltage V _OUT of the external output terminal 114 falls following the falling edge of the floating voltage V _P. The reason is as follows. Gate voltage V _G of the IGBT 200 becomes high as about 5V in association with the emitter potential, IGBT 200 is turned on. While the IGBT 200 is in the on state, the floating voltage V _{P of the} IGBT 200 is about 10 V higher than the emitter potential, and is in a high voltage state. At this time, the floating voltage V _P is detected by the protection circuit, and the input voltage V _IN converted into a signal that can be input to the delay circuit 100 by the voltage dividing circuit is applied to the IN terminal of the delay circuit 100. When a high voltage state of the floating voltage V _P of IGBT200 exceeds 200 ns, since the first switch 21 is turned on, the gate voltage V _G of IGBT200 is reduced by the output voltage at the OUT terminal of the delay circuit 100 .

  In addition, the delay characteristics of the conventional delay circuit were verified. 9 and 10 are characteristic diagrams showing delay characteristics in the conventional delay circuit. Here, the delay circuit shown in FIG. 13 will be described as an example. The results shown in FIG. 9 are the same as those of the example in the first inverter, the second inverter, the resistance value of the delay resistor, and the capacitance of the capacitor in the delay circuit shown in FIG. This is a delay characteristic when the conventional example is used. The results shown in FIG. 10 are the delay characteristics when the resistance value of the delay resistor is 50 kΩ (hereinafter referred to as the second conventional example) in the delay circuit of the first conventional example. From the results shown in FIG. 9 and FIG. 10, it was found that the delay times were about 77 ns and 135 ns, respectively.

  From the above results, it was found that the delay time of the embodiment can be made longer than that of the conventional delay circuit even when the delay resistor is not used. For example, in the embodiment in which the resistance value of the delay resistor 121 and the capacitance of the capacitor 122 are the same, and in the first conventional example, the delay times are 205 ns and 77 ns, respectively, and the embodiment has a delay time approximately three times that of the conventional example. It was found that can be realized.

  Note that when the IGBT 200 is used, for example, in the first IGBT 4001 and the second IGBT 4002 in the output stage in the power IC circuit (see FIG. 20), the upper limit of the current value that can be passed through the first IGBT 4001 (hereinafter, current capability) ) Is 0.6 A, the current capability of the second IGBT 4002 is 0.2 A, the capacitance of the capacitor 4003 is 200 pF, the resistance value of the resistor 4004 is about 5 kΩ, and the constant current value of the constant current source 4005 is 0.1 A and high. When the voltage of the circuit power supply connected to the voltage power supply terminal 4007 is about 150 V, the turn-on time during normal operation of the second IGBT 4002 when the capacitor 4003 is charged is about 200 ns. Further, when the capacitor 4003 is discharged, the time during which the floating voltage of the first IGBT 4001 is higher than the potential when the gate voltage of the first IGBT 4001 is zero is about 80 ns. As a protection circuit for the first IGBT 4001, a circuit having a delay time of 80 ns or more may be created. However, when the first IGBT 4001 and the second IGBT 4002 are formed by the same process and the same process, both have the same breakdown tolerance. Therefore, the protection circuits of the first IGBT 4001 and the second IGBT 4002 may be formed in accordance with the turn-on time of the second IGBT 4002.

  In the above description, the present invention is described as a circuit for protecting the output stage, but it can also be applied to an individual semiconductor. Further, the structure relating to the withstand voltage according to the present invention can be applied to a lateral LDMOS transistor or the like that requires a high withstand voltage. In addition, the configuration of the circuit using the semiconductor device according to the present invention and the configuration of the protection circuit are not limited to the above-described circuit configuration, and can be variously changed.The turn-on time of the switching element used as the protection circuit, the gate threshold voltage, etc. It is desirable to change to suitable conditions according to the circuit configuration.

  As described above, the IGBT according to the present invention is useful for a high breakdown voltage switching element that requires a high short-circuit withstand capability, and particularly for a high breakdown voltage switching element used in an output stage of a driver IC or an in-vehicle IC of a flat panel display. Is suitable.

1 p-channel MOSFET (first)
2 n-channel MOSFET (first)
3 p-channel MOSFET (second)
4 n-channel MOSFET (second)
5 p-channel MOSFET (third)
6 n-channel MOSFET (third)
7 p-channel MOSFET (4th)
8 n-channel MOSFET (4th)
101 Inverter (first)
102 Inverter (second)
103 Inverter (third)
111 IN terminal 112 OUT terminal 113 Node 121 Delay resistor 122 Capacitor 100 Delay circuit

Claims (6)

A first inverter;
A second inverter;
A third inverter;
A first resistor connected between an output terminal of the first inverter and an input terminal of the second inverter;
An external signal input terminal connected to an input terminal of the first inverter and an input terminal of the third inverter;
An external signal output terminal connected to the output terminal of the second inverter;
A fourth p-type MOS transistor using the output signal of the third inverter as a gate drive signal;
A fourth n-type MOS transistor having an output signal of the first inverter via the first resistor as a gate drive signal;
A capacitor connected between the gate and drain of the fourth n-type MOS transistor,
The drain of the fourth p-type MOS transistor is connected to the drain of the fourth n-type MOS transistor,
A source of the fourth p-type MOS transistor is connected to a first power source;
The source of the fourth n-type MOS transistor is grounded,
The semiconductor device, wherein the fourth n-type MOS transistor is biased by an applied voltage. An insulated gate transistor in which a floating region and a floating electrode having a potential of the floating region are formed in the drift region;
A first field effect transistor having a gate insulating film having a breakdown voltage greater than the voltage of the floating electrode and having a threshold voltage higher than the voltage of the first power supply;
A second field effect transistor having an output signal from the external signal output terminal as a gate drive signal;
A second resistor connected between the source of the first field effect transistor and ground;
The floating electrode is connected to a gate of the first field effect transistor;
A gate of the insulated gate transistor is connected to a drain of the second field effect transistor;
The collector or drain of the insulated gate transistor is connected to a high voltage external output terminal,
The source of the insulated gate transistor is grounded,
A drain of the first field effect transistor is connected to the first power source;
The external signal input terminal is connected between the source of the first field effect transistor and the second resistor,
The body potential of the first field effect transistor and the body potential of the second field effect transistor are ground potentials;
The semiconductor device according to claim 1, wherein a source of the second field effect transistor is grounded. A first inverter;
A second inverter;
A third inverter;
A first resistor connected between an output terminal of the first inverter and an input terminal of the second inverter;
An external signal input terminal connected to an input terminal of the first inverter and an input terminal of the third inverter;
An external signal output terminal connected to the output terminal of the second inverter;
A fourth p-type MOS transistor using the output signal of the third inverter as a gate drive signal;
A fourth n-type MOS transistor having an output signal of the first inverter via the first resistor as a gate drive signal;
A capacitor connected between the gate and drain of the fourth n-type MOS transistor,
The drain of the fourth p-type MOS transistor is connected to the drain of the fourth n-type MOS transistor,
The low potential side power supply terminal of the first inverter, the low potential side power supply terminal of the second inverter, the low potential side power supply terminal of the third inverter, and the source of the fourth n-type MOS transistor are Connected to the high voltage external output terminal,
The high potential side power supply terminal of the first inverter, the high potential side power supply terminal of the second inverter, the high potential side power supply terminal of the third inverter, and the source of the fourth p-type MOS transistor are The semiconductor device is connected to a second power source having a potential higher than the potential of the external output terminal by a potential difference between the first power source and the ground. An insulated gate transistor in which a floating region and a floating electrode having a potential of the floating region are formed in the drift region;
A first field effect transistor having a gate insulating film having a breakdown voltage greater than the voltage of the floating electrode and having a threshold voltage higher than the voltage of the first power supply;
A second field effect transistor having an output signal from the external signal output terminal as a gate drive signal;
A second resistor connected between a source of the first field effect transistor and the external output terminal;
The floating electrode is connected to a gate and a drain of the first field effect transistor;
A gate of the insulated gate transistor is connected to a drain of the second field effect transistor;
The collector or drain of the insulated gate transistor is connected to a high-voltage third power source,
A source of the insulated gate transistor is connected to the external output terminal;
The external signal input terminal is connected between the source of the first field effect transistor and the second resistor,
The body potential of the first field effect transistor and the body potential of the second field effect transistor have the potential of the external output terminal,
The semiconductor device according to claim 3, wherein a source of the second field effect transistor is connected to the external output terminal. The external output terminal is connected to the second power source via a third resistor,
A source and a body of a third field effect transistor are connected between the second power source and the third resistor,
The gate and drain of the third field effect transistor are connected to the anode of the first Zener diode and the cathode of the second Zener diode,
A cathode of the first Zener diode is connected to the floating electrode;
The semiconductor device according to claim 4, wherein an anode of the second Zener diode is connected to the external output terminal. The external output terminal is connected to the second power source via a third resistor,
A source and a body of a third field effect transistor are connected between the second power source and the third resistor,
The gate and drain of the third field effect transistor are connected to the cathode of the diode and the cathode of the second Zener diode;
The anode of the diode is connected to the floating electrode;
An anode of the second Zener diode is connected to the external output terminal;
The semiconductor device according to claim 4, wherein the diode is one diode or a plurality of diodes connected in series in the same direction.

Images