JP2010185931A - Manufacturing method for microelectronic mechanical system (mems) element and microelectronic mechanical system (mems) element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a microelectronic mechanical system (MEMS) element provided with a mirror array using a wall electrode easily. <P>SOLUTION: In this manufacturing method for the MEMS element, a groove part 113a is formed in a first electrode pattern 113, and a groove part is also formed in a second electrode pattern (not shown) in the same way. For example, etching can be performed by using SF<SB>6</SB>as etching gas by the DRIE etching technology being the well-known Si deep-digging processing technology. Here, in the etching forming the groove part 113, etching time is controlled to leave the first electrode pattern 113 (a silicon layer 103) in a bottom part of the formed groove part 113a. For example, etching rate is measured in advance by an experiment, processing time is calculated to leave the first electrode pattern 113 (the silicon layer 103) in the bottom part of the groove part 113a, and the result of calculation is applied to the etching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a MEMS device using wall electrodes.

  In the field of optical networks that serve as the foundation of Internet communication networks, optical MEMS (Micro Electro Mechanical Systems) technology is in the spotlight as a technology that realizes multi-channel, wavelength division multiplexing (WDM), and cost reduction. An optical switch using optical MEMS technology has been developed (see Patent Document 1). The most characteristic component of the MEMS optical switch is a mirror array in which a plurality of mirror elements are arranged.

  An optical switch enables path switching without converting light into an electrical signal. If an optical switch is used, even multiplexed light is demultiplexed for each wavelength. It is possible to switch the route without any problem. Such an optical switch is used, for example, to distribute a signal to another path when a failure occurs in the path being used and to maintain a state where communication is possible.

  In recent years, wavelength selective switches that demultiplex multiplexed light for each wavelength and switch the path for each demultiplexed wavelength have been researched and developed. Some of these switches use mirror elements (see Patent Document 2).

  Further, a mirror element has been proposed that enables a plurality of mirror elements to be arranged closer to each other (see Patent Document 3). Moreover, in order to suppress interference (crosstalk) between adjacent mirror elements, a configuration using wall electrodes has been proposed.

  Here, a mirror array in which the above-described wall electrode is used to suppress crosstalk will be described with reference to the perspective view of FIG. Although not shown in FIG. 6, this mirror array includes an electrode substrate and a mirror substrate disposed so as to face the electrode substrate, and is provided so as to surround a mirror array region where a plurality of mirror elements are disposed. The mirror substrate is fixed on the electrode substrate by a predetermined distance by the support structure. The electrode substrate and the mirror substrate are arranged in parallel with each other.

  As shown in FIG. 6, a movable beam drive electrode 601a, a movable beam drive electrode 601b, a mirror drive electrode 603a, and a mirror drive electrode 603b are provided on the electrode substrate for each mirror element. The movable beam drive electrode 601a, the movable beam drive electrode 601b, the mirror drive electrode 603a, and the mirror drive electrode 603b constitute one (one set) electrode unit.

  The mirror substrate includes a frame (not shown) in which the mirror array region is open, and the frame is connected to the support structure. In addition, a movable beam 613a and a movable beam 613b having one end fixed to the frame portion are provided inside the frame portion of the mirror substrate. One end of each of the movable beam 613a and the movable beam 613b is fixed to each of two opposing sides on the inner side of the frame portion, and is aligned with a predetermined distance apart on the same line in the opposing direction of the two sides. ing. Thus, the movable beam 613a and the movable beam 613b are fixed at one end and opposed to each other on the other end side, and are arranged in a line at a predetermined distance. In the example of FIG. 6, the movable beam 613a and the movable beam 613b are aligned on a line parallel to the y-axis direction. Further, the movable beam 613a and the movable beam 613b have a cantilever structure in which the other ends of the movable beam 613a and the movable beam 613b can be displaced in the normal direction of the mirror substrate.

  Further, a mirror 611 is disposed between the movable beam 613a and the movable beam 613b by being connected by a pair of bendable connecting portions 612a and 612b. The mirror 611 is arranged in a row with the movable beam 613a and the movable beam 613b, and is rotatably disposed between the movable beam 613a and the movable beam 613b. The connecting portions 612a and 612b connect the other end of each of the movable beam 613a and the movable beam 613b to the mirror 611. The movable beam 613a, the mirror 611, and the movable beam 613b are aligned in this order on the same line in the opposing direction of the two sides to which the movable beam 613a and the movable beam 613b are connected. The movable beam 613a, the mirror 611, the movable beam 613b, and the pair of connecting portions 612a and 612b constitute one (one set) reflecting portion.

  In this example, the movable beam 613a, the mirror 611, and the movable beam 613b are aligned on a line parallel to the y-axis direction. Further, the mirror 611 is rotatable around a first rotation axis that passes through the pair of connecting portions 612a and 612b. Further, it is rotatable about a first rotation axis that is parallel to the y-axis. In addition, a plurality of mirror elements are arranged along a direction perpendicular to the direction in which the movable beam 613a, the mirror 611, and the movable beam 613b are aligned (arranged) to form a mirror array. A reflective film 611a made of gold, aluminum, or the like is formed on the surface of the mirror 611 so that, for example, light in the infrared region can be reflected.

  In addition, this mirror element first includes a wall electrode 602a and a wall electrode 602b in each of the movable beam drive electrode 601a and the movable beam drive electrode 601b. Two wall electrodes 602a are arranged so as to sandwich at least a region where the movable beam 613a is displaced. Similarly, two wall electrodes 602b are arranged so as to sandwich at least a region where the movable beam 613b is displaced. The wall electrode 602a is electrically connected to the movable beam drive electrode 601a, and the wall electrode 602b is electrically connected to the movable beam drive electrode 601b.

  Here, the movable beam 613a facing each movable beam drive electrode 601a has a width within a range that can be displaced toward the movable beam drive electrode 601a in a region sandwiched between the wall electrodes 602a. Similarly, the width of the movable beam 613b facing each movable beam drive electrode 601b is set to a range that can be displaced toward the movable beam drive electrode 601b in the region sandwiched by the wall electrodes 602b. Therefore, the movable beam 613a and the movable beam 613b are formed to be narrower than the mirror 611, for example.

  The above-mentioned movable beam drive electrode 601a, movable beam drive electrode 601b, a pair of mirror drive electrodes 603a and 603b, a pair of movable beam 613a, mirror 611, movable beam 613b, and a pair of connecting portions 612a and 612b. Thus, one mirror element is configured. In one mirror element, the movable beam drive electrode 601a and the movable beam 613a are arranged facing the normal direction (z-axis direction) of the electrode substrate (mirror substrate), and the movable beam drive electrode 601b and the movable beam 613b are arranged. Are arranged, and a pair of mirror driving electrodes 603a and 603b and a mirror 611 are arranged.

  A drive voltage (drive signal) for driving the movable beam 613a and the movable beam 613b is supplied to the movable beam drive electrode 601a and the movable beam drive electrode 601b via wiring (not shown). In addition, a drive voltage for driving the mirror 611 is supplied to the mirror drive electrode 603a and the mirror drive electrode 603b via a wiring (not shown). Note that the movable beam 613a, the mirror 611, the movable beam 613b, and the pair of connecting portions 612a and 612b are equipotential. Here, the equipotential may be a ground potential, for example.

  Next, the operation of the mirror element will be described. First, when a predetermined driving voltage is applied to the movable beam driving electrode 601b to apply a force that attracts the movable beam 613b to the electrode substrate side by the generated electrostatic attraction, the movable beam 613b is supported by the frame portion. The other end of the movable beam 613b is displaced so as to be drawn toward the electrode substrate side with the one end being bent as a fulcrum. As a result, the mirror 611 is pulled toward the electrode substrate side with the connecting portion 612a as a fulcrum, and the mirror 611 is not parallel to the electrode substrate, but is inclined in the y-axis direction.

  This tilted state means that the mirror 611 rotates around the second rotation axis that passes through the center of the mirror 611 parallel to the arrangement direction (x-axis direction) of the mirror elements. This rotation operation can also be performed by applying a predetermined drive voltage to the movable beam drive electrode 601a to draw the other end of the movable beam 613a toward the electrode substrate as described above. In this case, the second rotation is performed. The mirror 611 is rotated around the axis in the direction opposite to that described above.

  Further, by controlling the voltage applied to the mirror drive electrode 603a and the mirror drive electrode 603b, the mirror 611 can be rotated around the first rotation axis passing through the pair of connecting portions 612a and 612b. For example, a higher voltage is applied to the mirror drive electrode 603a than the mirror drive electrode 603b, and the mirror 611 is controlled to tilt toward the mirror drive electrode 603b around the first rotation axis. it can. In this mirror element, biaxial rotation is realized by a pair of connecting portions by positively moving the connecting portions 612a and 612b.

  Since the wall electrode 602a and the wall electrode 602b are provided, as will be described below, it is possible to suppress crosstalk between adjacent mirror elements. Since the mirror element is arranged with a narrow interval between adjacent mirror elements, when the movable beam driving electrode 601a is a simple parallel plate electrode, the electrostatic attraction force is only applied to the movable beam of the mirror element. In addition, the movable beam of the adjacent mirror element is also affected, and its position may be displaced. As a result, electrical interference (crosstalk) may occur between adjacent mirrors 611.

  On the other hand, when the wall electrode 602a connected to the movable beam driving electrode 601a is provided, the electric field for driving the movable beam can be separated for each mirror element. The wall electrode 602a almost shields the electric lines of force from the movable beam drive electrode 601a toward the movable beam 613a adjacent thereto, so that the influence of crosstalk can be suppressed. The suppression of such crosstalk is most effective when the heights of the wall electrode 602a and the wall electrode 602b are the same as the positions of the movable beam 613a and the movable beam 613b in the initial state. .

  Further, by using the wall electrode, an effect of pulling back the movable beam in the direction opposite to that of the drive electrode can be obtained, and the displacement amount of the movable beam with respect to the increment of the voltage applied to the drive electrode can be suppressed to be small. It becomes like this.

JP 2003-057575 A JP 2007-140168 A JP 2007-240728 A

  However, there is a problem that it is not easy to form the above-described wall electrode. For example, the wall electrode is formed of a conductive material and is required to have a height of 30 μm or more. One method for forming such a structure is a plating method. However, in the plating method, when the wall electrode having the height as described above is formed, it is not easy to make the height constant. Moreover, it is not easy to make the width constant. In the plating method, it is difficult to control the height and width with high accuracy when forming the wall electrode structure having the dimensions as described above. On the other hand, it may be possible to control the height by applying a technique such as polishing or etchback after forming by plating, but this increases the number of manufacturing steps.

  In addition, when a manufacturing method in which a thick metal film is processed by a known photolithography technique and etching technique is applied, two or more components to be electrically separated may be electrically separated by reattachment of the etched metal film. The problem of becoming a short circuit condition is also likely to occur. In addition, when manufactured using metal, the temperature cannot be higher than the melting point of the metal used, and it is necessary to keep the temperature applied to the device at a low temperature in consideration of the influence of diffusion of metal particles. Tend to make manufacturing more complex.

  The present invention has been made to solve the above problems, and an object of the present invention is to make it easier to manufacture a MEMS element including a mirror array using wall electrodes.

  In a method for manufacturing a MEMS device according to the present invention, a first resist pattern is formed on a silicon layer of an SOI substrate including a base, a buried insulating layer on the base, and a silicon layer on the buried insulating layer. A first step, etching the silicon layer using the first resist pattern as a mask, and a plurality of sets of first electrode patterns and second electrode patterns arranged in a line at a predetermined interval; A second step of forming a first wiring pattern and a second wiring pattern connected to the two-electrode pattern; and a second step of providing an opening at the center of the first electrode pattern and the second electrode pattern after removing the first resist pattern A third step of forming a resist pattern; and etching the central portion of the first electrode pattern and the second electrode pattern using the second resist pattern as a mask A first electrode and a second electrode arranged in a row at a predetermined interval, two first wall electrodes electrically connected to side portions in the arrangement direction of the first electrodes, and a second electrode A fourth step of forming two second wall electrodes electrically connected to the side portions in the arrangement direction, the first wiring and the second wiring connected to the first electrode and the second electrode, and a second resist pattern After the removal, one end is fixed on the SOI substrate and the other end is displaceable, facing the other end side and spaced apart by a predetermined distance, and placed on top of the plurality of sets of the first electrode and the second electrode. Correspondingly, a plurality of sets of the first movable beam and the second movable beam arranged in a row and two adjacent sets of the first movable beam and the second movable beam are arranged. A mirror supported at four positions by the movable beam and the second movable beam, and a first movable beam and a mirror for supporting the mirror. Comprising at least a fifth step of forming a four connecting portions for connecting the other end mirror of each of the second movable beam.

  In the MEMS device manufacturing method, the SOI substrate includes a base, a first buried insulating layer on the base, a first silicon layer on the first buried insulating layer, and a second buried insulating on the first silicon layer. And a second silicon layer on the second buried insulating layer, and in the second step, the second silicon layer, the second buried insulating layer, and the first silicon layer are etched using the first resist pattern as a mask, In the fourth step, the second silicon layer and the second buried insulating layer may be etched using the second resist pattern as a mask.

  According to another aspect of the present invention, there is provided a method of manufacturing a MEMS device, wherein a first resist pattern is formed on a silicon layer of an SOI substrate including a base, a buried insulating layer on the base, and a silicon layer on the buried insulating layer. A first step of forming, and a second step of etching the silicon layer using the first resist pattern as a mask to form a plurality of sets of first opening patterns and second opening patterns arranged in a row at a predetermined interval And a third step of forming a second resist pattern covering the first opening pattern and the second opening pattern after removing the first resist pattern, and the first opening pattern and the second opening pattern using the second resist pattern as a mask. The silicon layer on which the first electrode is formed is etched, and the first electrode and the second electrode arranged in a row at a predetermined interval, and the arrangement direction of the first electrode Two first wall electrodes that are electrically connected to the first part, two second wall electrodes that are electrically connected to side parts in the arrangement direction of the second electrodes, and a first that is connected to the first electrode and the second electrode. After removing the second resist pattern after the fourth step of forming the wiring and the second wiring, one end is fixed on the SOI substrate and the other end can be displaced, and the other end faces A plurality of sets of first movable beams and second movable beams that are spaced apart by a predetermined distance and are arranged in a line corresponding to the tops of the plurality of sets of first electrodes and second electrodes, and two adjacent sets of first movable beams A mirror disposed between the beam and the second movable beam and supported at four locations by the two sets of the first movable beam and the second movable beam, and the first movable beam and the second movable beam for supporting the mirror. Less 5th step of forming four connecting portions connecting the other end of each of the two movable beams and the mirror Also it comprises.

  In the MEMS device manufacturing method, the SOI substrate includes a base, a first buried insulating layer on the base, a first silicon layer on the first buried insulating layer, and a second buried insulating on the first silicon layer. And a second silicon layer on the second buried insulating layer. In the second step, the second silicon layer and the second buried insulating layer are etched using the first resist pattern as a mask, and in the fourth step, the second silicon layer is etched. The second silicon layer, the second buried insulating layer, and the first silicon layer may be etched using the two resist pattern as a mask.

  The MEMS element according to the present invention is manufactured by the above-described method for manufacturing a MEMS element.

  As described above, according to the present invention, since the wall electrode is formed by processing the silicon layer of the SOI substrate, the MEMS device including the mirror array using the wall electrode can be more easily manufactured. An excellent effect is obtained.

It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 1 of this invention. It is a perspective view which shows a partial structure of the MEMS element produced with the manufacturing method in Embodiment 1 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 2 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 3 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is process drawing for demonstrating the manufacturing method in Embodiment 4 of this invention. It is explanatory drawing explaining the effect of a wall electrode. It is explanatory drawing explaining the effect of a wall electrode. It is explanatory drawing explaining the effect of a wall electrode. It is explanatory drawing explaining the effect of a wall electrode. It is a perspective view which shows the structure of the mirror array which suppressed the crosstalk using the wall electrode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, the first embodiment of the present invention will be described. First, as shown in the cross-sectional view of FIG. 1A, an SOI substrate including a base 101, a buried insulating layer 102 on the base 101, and a silicon layer 103 on the buried insulating layer 102 is prepared. The buried insulating layer 102 is made of silicon oxide.

  Next, as shown in the cross-sectional view of FIG. 1B, a first resist pattern 104 is formed on the silicon layer 103. As shown in the plan view of FIG. 1C, the first resist pattern 104 includes a pattern corresponding to a portion to be a movable beam driving electrode described later and a portion to be a wiring connected to the electrode. FIG. 1B shows a cross section taken along line aa in FIG. 1C.

  For example, a well-known positive photosensitive resist is applied on the silicon layer 103 to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity of the first resist pattern 104 and silicon when the silicon layer 103 is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the first resist pattern 104 can be formed on the silicon layer 103.

Next, as shown in the cross-sectional view of FIG. 1D, the silicon layer 103 is etched using the first resist pattern 104 as a mask, and a plurality of first electrode patterns 113 are formed at predetermined intervals. At this time, a pair of the first electrode pattern 113 and the second electrode pattern arranged in a row is formed in a region not shown, and the first wiring connected to the first electrode pattern 113 and the second electrode pattern A pattern and a second wiring pattern are also formed at the same time. In this step, the silicon layer 103 is etched until the buried insulating layer 102 is exposed. For example, in DRlE it is a deep engraving technique for Si which is a known technique, by using SF ₆ as an etching gas, can be performed above etching.

  Next, the first resist pattern 104 is removed (FIG. 1E), and the SOI substrate is washed to expose a clean surface on the substrate such as the first electrode pattern 113 and the exposed upper surface of the buried insulating layer 102.

  Next, as shown in the cross section of FIG. 1F, a second resist pattern 105 having an opening 105a at the center of the first electrode pattern 113 is formed. As shown in the plan view of FIG. 1G, the opening 105a has a vertical length equal to the length of the first electrode pattern 113 and a horizontal width smaller than the width of the first electrode pattern 113. To do. FIG. 1F shows a cross section taken along line aa in FIG. 1G. Here, the second resist pattern 105 is provided with an opening similar to the above in the center of the second electrode pattern (not shown). Moreover, you may make it provide an opening also in a wiring part.

  For example, a well-known positive photosensitive resist is applied on the buried insulating layer 102 including the first electrode pattern 113 to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the second resist pattern 105 and silicon when the first electrode pattern 113 and the like are etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the second resist pattern 105 can be formed.

Next, the central portion of the first electrode pattern 113 is etched halfway using the second resist pattern 105 as a mask to form a groove 113a in the first electrode pattern 113 as shown in FIG. 1H. Similarly, a groove is formed in the second electrode pattern (not shown). For example, in DRlE it is a deep engraving technique for Si which is a known technique, by using SF ₆ as an etching gas, can be performed above etching. Here, in the etching for forming the groove 113, the etching time is controlled so that the first electrode pattern 113 (silicon layer 103) remains at the bottom of the formed groove 113a. For example, an etching rate is measured in advance by an experiment, and a processing time in which the first electrode pattern 113 (silicon layer 103) remains at the bottom of the groove 113a is calculated based on the etching rate. It can be applied to.

  Thereafter, by removing the second resist pattern 105, as shown in the cross-sectional view of FIG. 1I and the plan view of FIG. 1J, the arrangement of the first electrode 141a, the second electrode (not shown), and the first electrode 141a Two first wall electrodes 142a electrically connected to the side portions in the direction, two second wall electrodes (not shown) electrically connected to the side portions in the arrangement direction of the second electrodes, and the first electrode 141a. A first wiring 143a and a second wiring (not shown) connected to the second electrode are formed. 1I shows a cross section taken along line aa in FIG. 1J.

  Here, as shown in the perspective view of FIG. 1K, the first electrode 141a and the second electrode 141b are arranged in a row at a predetermined interval. Further, in these arrangement directions, two first wall electrodes 142a are formed by being electrically connected to the side portion of the first electrode 141a. Similarly, two second wall electrodes 142b are formed by being electrically connected to the side portions of the second electrodes 141b in the arrangement direction. In addition, a first wiring 143a connected to the first electrode 141a is formed, and a second wiring 143b connected to the second electrode 141b is formed. In the present embodiment, the first wiring 143a and the second wiring 143b are formed at substantially the same height as each wall electrode.

  As shown in FIG. 1L, a mirror substrate including a mirror 183, a first movable beam 184a, a second movable beam 184b, a connecting portion 109a, and a connecting portion 109b on the SOI substrate on which each electrode is formed as described above. If this is arranged, a MEMS element as a mirror array in the present embodiment is formed. For example, the mirror substrate may be formed separately from the SOI substrate (electrode substrate) including the above-described electrodes, and may be attached and integrated after each formation. Further, the sacrificial film and the plating technique may be combined to form the mirror 183, the first movable beam 184a, the second movable beam 184b, the coupling portion 109a, the coupling portion 109b, and the like on the electrode substrate.

  Here, the first movable beam 184a and the second movable beam 184b have one end fixed to the mirror substrate and the other end displaceable. The first electrode 141a and the second electrode 141b are arranged in a row corresponding to the upper part. The mirror 183 is disposed between two adjacent sets of the first movable beam 184a and the second movable beam 184b and is supported at four locations by the two sets of the first movable beam 184a and the second movable beam 184b. ing. Further, in order to support the mirror 183, four connecting portions 109a and 109b for connecting the other end of each of the first movable beam 184a and the second movable beam 184b and the mirror 183 are provided.

  First, the mirror 183 causes the first movable beam 184a adjacent to be displaced simultaneously, or the second movable beam 184b adjacent to the first movable beam 184b to be simultaneously displaced, thereby causing the mirror 183 to rotate about the rotation axis in the x-axis direction. Can do. Further, the mirror 183 can be rotated about the rotation axis in the y-axis direction by simultaneously displacing one of the pair of the first movable beam 184a and the second movable beam 184b. In this case, no electrode is required below the mirror 183.

  Hereinafter, a method for manufacturing a mirror substrate will be briefly described. First, an SOl substrate is prepared. Since the mirror is formed in the SO1 layer, the thickness of the SO1 layer of the prepared SO1 substrate is the same as the thickness of the mirror. The thickness of the spring structure serving as the connecting portion for supporting the mirror is also equal to the thickness of the SO1 layer, and the designed spring constant and the realized thickness are defined as the thickness of the SOI layer.

  Next, a resist is applied to the surface of the silicon layer of the SOI substrate by using a known spin coating method to form a resist layer. Next, a known lithography technique is used for the formed resist layer to form a pattern corresponding to a portion that becomes a mirror, a connecting portion, and a movable beam. For example, a reticle (mask) having a light-shielding body having a shape corresponding to a pattern is held in alignment with an SOI substrate on which a resist layer is formed, and the reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist. The shadow of the light-shielding body is imaged on the resist layer to form a latent image, and the irradiation is performed after determining the light irradiation time so that a desired pattern can be obtained with a desired dimension.

  Next, the resist layer with the latent image printed thereon is immersed in the developer, and the time for immersing the SOI substrate in the developer is determined so that a desired pattern can be formed with a desired dimension. Then, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist pattern. Thus far, a resist pattern can be formed on the S01 substrate.

  Next, using the formed resist pattern as a mask, a structure serving as a mirror, a connecting portion, and a movable beam is formed on the silicon layer by using a DRlE etching technique which is a Si deep drilling technique. In this etching, an etching intermediate film may be used, or silicon may be directly processed using a resist as an etching mask. The photosensitive resist used for the mask is removed after the silicon etching. After removal, cleaning is performed to expose a clean silicon surface.

  Next, the base portion of the SOI substrate is processed. First, a protective organic film is applied to the silicon layer side. A photosensitive resist may be used, or a film with clear workability such as polyimide may be used. Since this film is finally removed, it is desirable to use a film that can be easily peeled off and removed. However, since the back surface is processed with the protective film attached, it is essential to select a material that does not cause a problem during the processing.

  After forming a protective film on the silicon layer side, a photosensitive resist film is formed on the back surface of the base by coating. In the case of the application of the photosensitive resist, the silicon layer side comes into contact with the sample stage of the coating apparatus. However, since the protective film is deposited, the structure formed on the silicon layer side is not damaged. After the resist film is formed, a reticle (mask) having a light shielding body having a shape corresponding to a desired pattern is aligned with the SOI substrate on which the resist film is formed, particularly with the structure on the silicon layer side. Hold.

  The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and the shadow of the light shielding body is formed on the resist film to form a latent image. Next, the irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The resist film with the latent image printed thereon is immersed in a developer, and the development time is determined so that a desired pattern can be formed with a desired dimension. The SOI substrate is immersed in the developer for the determined time. Thereafter, the entire SOI substrate is dried to cure the resist film. Thus far, a resist pattern is formed on the back surface of the base.

  Next, using the formed resist pattern as a mask, unnecessary base silicon corresponding to the portion where the mirror is formed on the silicon layer is removed by etching using the DRlE etching technique, which is a Si deep-drilling technique. At this time, an etching intermediate film such as a silicon oxide film may be used, or silicon may be directly processed using a resist as an etching mask. The photosensitive resist used for the mask is removed after the silicon etching. After removal, cleaning is performed to expose a clean silicon surface.

  Next, a metal film for reflecting light in the used wavelength band is formed on the surface of the structure functioning as a mirror. The mirror substrate thus formed is joined and integrated with an electrode substrate on which electrodes such as wall electrodes are formed, and this is die-bonded to PKG, and wire bonding is performed between the integrated element and PKG. The device is completed. Here, it is important to prevent a portion of the electrode substrate such as an electrode to which a driving potential is applied from being electrically connected to the mirror substrate.

  As described above, according to the present embodiment, a MEMS element including a mirror array using wall electrodes can be manufactured more easily. Usually, the distance between the movable beam and the electrode is about several microns to several hundred microns, and the height of the wall electrode is required to be the same. These values are determined by device design. When the wall electrode is formed of metal, a thick metal film is etched or a thick metal film is formed by a plating method. However, the deposition of a thick metal film and this etching are disadvantageous in terms of cost because it takes a long time to manufacture. Further, a more general plating method is disadvantageous because it is difficult to thicken a fine pattern and control the film thickness with high accuracy, and it is desired to make the characteristics of the element uniform.

  On the other hand, according to the present embodiment, a technique for deep etching of silicon and a halfway stop of etching is required, but the structure of the wall electrode can be realized more easily than the technique described above. Further, since silicon and silicon oxide are used, it has resistance to heat treatment exceeding 1000 ° C. In addition, since the SOI substrate is used, the height of the structure can be controlled with high accuracy. Further, a structure such as a wall electrode can be made of single crystal silicon having high rigidity.

  By the way, the resistance of the silicon layer of the SOI substrate can be lowered by impurity doping or the like, and it is important to use a silicon layer having a low resistance to such an extent that the processability is not hindered. A specific resistance of 10 Ωcm or less can be used satisfactorily. In this embodiment, the wiring for applying a voltage to the electrode is formed at the same height as the wall electrode as described above. However, the second resist described with reference to FIGS. 1F to 1H is used. By etching using the pattern 105, the wiring portion may also be etched halfway at the same time to form a thinner wiring. However, as described above, by forming the wiring thick, the cross-sectional area of the wiring can be increased, and the wiring resistance can be reduced. It is better to make the wiring thick as long as it does not hinder the operation of the movable part such as the movable beam.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. First, as shown in the cross-sectional view of FIG. 2A, the first buried insulating layer 202, the first silicon layer 203, the second buried insulating layer 204, and the second silicon layer 205 are purely stacked on the base 201. A two-layer SOI substrate is prepared.

  Next, as shown in the cross-sectional view of FIG. 2B, a first resist pattern 206 is formed on the second silicon layer 205. As shown in the plan view of FIG. 2C, the first resist pattern 206 includes a pattern corresponding to a portion to be a movable beam driving electrode, which will be described later, and a portion to be a wiring connected to the electrode. FIG. 2B shows a cross section taken along line aa in FIG. 2C.

  For example, a well-known positive photosensitive resist is applied on the second silicon layer 205 to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the first resist pattern 206 and silicon when the second silicon layer 205 is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on a two-layer SOI substrate on which a resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. Decide the time to immerse the two-layer SOI substrate on which the resist layer is formed in the developer so that the desired pattern can be formed with the desired dimensions by immersing the resist layer with the latent image printed thereon in the developer. The two-layer SOI substrate is soaked in the developer only for a predetermined time. Thereafter, the entire two-layer SOI substrate is dried to cure the resist. As described above, the first resist pattern 206 can be formed on the second silicon layer 205.

  Next, using the first resist pattern 206 as a mask, the second silicon layer 205, the second embedded insulating layer 204, and the first silicon layer 203 are etched, and a plurality of sets of the first silicon layer 205, as shown in the cross-sectional view of FIG. A stacked structure of the silicon pattern 231, the second embedded insulating pattern 241, and the second silicon pattern 251 is formed. This laminated structure corresponds to the first electrode pattern 113 in the above-described embodiment. Also in the present embodiment, a set of similar stone image structures arranged in a row with the above laminated structure is formed in a region not shown, and the wiring pattern connected to each laminated structure is simultaneously provided. It is formed.

In this step, etching is performed until the first buried insulating layer 202 is exposed. For example, in DRlE is a deep engraving technique for Si which is a known technique, it can be a layer of silicon etching by using SF ₆ as an etching gas, a silicon oxide (embedded by using CHF ₃ as the etching gas Insulating layer) can be etched.

  Next, the first resist pattern 206 is removed (FIG. 2E), and a two-layer SOI substrate is used to expose a clean surface on the substrate such as the second silicon pattern 251 and the exposed upper surface of the first buried insulating layer 202. Wash.

  Next, as shown in the cross section of FIG. 2F, a second resist pattern 207 having an opening 207a is formed at the center of the laminated structure by the first silicon pattern 231, the second embedded insulating pattern 241, and the second silicon pattern 251. To do. As shown in the plan view of FIG. 2G, the opening 207a is formed such that the vertical length is equal to the length of the first electrode pattern 113, and the horizontal width is smaller than the width of the first electrode pattern 113. To do. FIG. 2F shows a cross section taken along line aa in FIG. 2G. Here, the second resist pattern 207 is provided with an opening similar to the above in the center of a laminated structure (not shown).

  For example, a well-known positive type photosensitive resist is applied on the first buried insulating layer 202 including the laminated structure to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the second resist pattern 207 and silicon when the stacked structure or the like is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on a two-layer SOI substrate on which a resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. Decide the time to immerse the two-layer SOI substrate on which the resist layer is formed in the developer so that the desired pattern can be formed with the desired dimensions by immersing the resist layer with the latent image printed thereon in the developer. The two-layer SOI substrate is soaked in the developer only for a predetermined time. Thereafter, the entire two-layer SOI substrate is dried to cure the resist. As described above, the second resist pattern 207 can be formed.

Next, the central portion of the multilayer structure is etched using the second resist pattern 207 as a mask to form a groove 208a in the multilayer structure as shown in FIG. 2H. Similarly, a groove is formed in a laminated structure not shown. For example, with the DRlE etching technique that is a well-known Si deep drilling technique, first, the second silicon pattern 251 is etched by using SF ₆ as an etching gas. Next, the second embedded insulating pattern 241 is etched by using CHF ₃ as an etching gas. In this etching with CHF ₃ , the first silicon pattern 231 is hardly etched, so that the groove 208a can be formed using this layer as an etching stop layer.

  Thereafter, by removing the second resist pattern 207, as shown in the cross-sectional view of FIG. 2I and the plan view of FIG. 2J, the first electrode 281a, the second electrode (not shown), and the arrangement of the first electrode 281a Two first wall electrodes 282a electrically connected to the side portions in the direction, two second wall electrodes (not shown) electrically connected to the side portions in the arrangement direction of the second electrodes, and the first electrode 281a A first wiring 283a and a second wiring (not shown) connected to the second electrode are formed. 2I shows a cross section taken along line aa in FIG. 2J.

  In the present embodiment, the wall electrode in the first embodiment described above is formed by processing the second buried insulating layer 204 and the second silicon layer 205. Therefore, in the present embodiment, the structure serving as the wall electrode is insulated from the electrode. Therefore, the electrode and the upper part of the wall electrode are connected by wiring. Alternatively, a metal film may be formed by a well-known oblique sputtering method or the like to electrically connect the electrode and the upper portion of the wall electrode. Other configurations are the same as those in the first embodiment.

  As described above, also in the present embodiment, a MEMS element including a mirror array using wall electrodes can be more easily manufactured as in the first embodiment. Further, in this embodiment, since there is no process for stopping etching halfway, process control is easy.

[Embodiment 3]
Next, a third embodiment of the present invention will be described. First, as shown in the cross-sectional view of FIG. 3A, an SOI substrate including a base 301, a buried insulating layer 302 on the base 301, and a silicon layer 303 on the buried insulating layer 302 is prepared.

  Next, as shown in the cross-sectional view of FIG. 3B, a first resist pattern 304 is formed on the silicon layer 303. As shown in the plan view of FIG. 3C, the first resist pattern 304 includes a pattern corresponding to a portion that becomes a groove for forming a wall electrode to be described later. FIG. 3B shows a cross section taken along line aa of FIG. 3C.

  For example, a well-known positive photosensitive resist is applied on the silicon layer 303 to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity of the first resist pattern 304 and silicon when the silicon layer 303 is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the first resist pattern 304 can be formed on the silicon layer 303.

Next, as shown in the cross-sectional view of FIG. 3D, the silicon layer 303 is etched using the first resist pattern 304 as a mask to form a plurality of recesses 313a at predetermined intervals. At this time, a set of recesses 313a and recesses arranged in a row is formed in a region not shown. In this step, the silicon layer 303 is etched halfway so that the buried insulating layer 302 is not exposed. For example, in DRlE it is a deep engraving technique for Si which is a known technique, by using SF ₆ as an etching gas, can be performed above etching. For example, an etching rate is measured in advance by an experiment, and a processing time in which a part of the silicon layer 303 remains at the bottom of the recess 313a is calculated from the etching rate, and the calculation result is applied to the etching. That's fine.

  Next, the first resist pattern 304 is removed (FIG. 3E), and the SOI substrate is washed to expose a clean surface such as the recess 313a and the exposed upper surface of the buried insulating layer 302 on the substrate.

  Next, as shown in the cross section of FIG. 3F, a second resist pattern 305 is formed to cover the first opening pattern 313a and the second opening pattern (not shown). As shown in the plan view of FIG. 3G, the second resist pattern 305 is a pattern corresponding to a first electrode to be described later, a portion serving as a wall electrode connected thereto, and a wiring connected to the first electrode. FIG. 3F is a cross section taken along line aa in FIG. 3G.

  For example, a well-known positive photosensitive resist is applied on the buried insulating layer 302 including the recess 313a to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the second resist pattern 305 and silicon when the silicon layer 303 or the like is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the second resist pattern 305 can be formed.

Next, the silicon layer 303 is etched using the second resist pattern 305 as a mask (FIG. 3H), and then the second resist pattern 305 is removed. As a result, as shown in the cross-sectional view of FIG. 3I and the plan view of FIG. 3J, the first electrode 341a and the two first wall electrodes 342a electrically connected to the side portions in the arrangement direction of the first electrodes 341a, A first wiring 343a connected to the first electrode 341a is formed. For example, in DRlE it is a deep engraving technique for Si which is a known technique, by using SF ₆ as an etching gas, can be performed above etching. Here, etching is performed until the buried insulating layer 302 is exposed. FIG. 3I shows a cross section taken along line aa in FIG. 3J. Other configurations are the same as those in the first embodiment.

  As described above, also in the present embodiment, a MEMS element including a mirror array using wall electrodes can be more easily manufactured as in the first embodiment.

[Embodiment 4]
Next, a fourth embodiment of the present invention will be described. First, as shown in the cross-sectional view of FIG. 4A, the first embedded insulating layer 402, the first silicon layer 403, the second embedded insulating layer 404, and the second silicon layer 405 are purely stacked on the base 401. A two-layer SOI substrate is prepared.

  Next, as shown in the cross-sectional view of FIG. 4B, a first resist pattern 404 is formed on the second silicon layer 405. As shown in the plan view of FIG. 4C, the first resist pattern 404 has a pattern corresponding to a portion to be a groove for forming a wall electrode to be described later. FIG. 4B shows a cross section taken along line aa of FIG. 4C.

  For example, a well-known positive photosensitive resist is applied on the second silicon layer 405 to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the first resist pattern 404 and silicon when the second silicon layer 405 is etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the first resist pattern 404 can be formed on the second silicon layer 405.

  Next, the second silicon layer 405 and the second buried insulating layer 404 are etched using the first resist pattern 404 as a mask, and a plurality of recesses 413a arranged at predetermined intervals as shown in the sectional view of FIG. 4D. A laminated pattern 413 is formed. The laminated pattern 413 is obtained by forming a recess 413 a in a laminated structure of a first silicon layer 403, a second buried insulating layer 404, and a second silicon layer 405.

In this step, the second silicon layer 405 is first etched by using, for example, the DRlE etching technique, which is a well-known Si deep drilling technique, using SF ₆ as an etching gas. Next, the second buried insulating layer 404 is etched by using CHF ₃ as an etching gas. In this etching with CHF ₃ , the first silicon layer 403 is hardly etched, so that the recess 413a can be formed using this layer as an etching stop layer.

  Next, the first resist pattern 404 is removed (FIG. 4E), and the SOI substrate is cleaned to expose a clean surface such as the recess 413a and the exposed upper surface of the buried insulating layer 402.

  Next, as shown in the cross section of FIG. 4F, a second resist pattern 407 covering the recess 413a is formed. As shown in the plan view of FIG. 4G, the second resist pattern 407 is a pattern corresponding to a first electrode to be described later, a portion serving as a wall electrode connected thereto, and a wiring connected to the first electrode. 4F is a cross section taken along line aa in FIG. 4G.

  For example, a well-known positive photosensitive resist is applied on the buried insulating layer 402 including the recesses 413a to form a resist layer. The layer thickness of the resist layer is determined by the etching selectivity between the second resist pattern 407 and silicon when the second silicon layer 405 and the like are etched. Next, a reticle (mask) having a light-shielding body having a shape corresponding to a desired pattern is aligned and held on the SOI substrate on which the resist layer is formed. The reticle is irradiated with light having a photosensitive wavelength of the photosensitive resist, and a shadow (projected image) of the light shielding body is formed on the resist layer to form a latent image on the resist layer.

  Irradiation is performed after determining the irradiation time so that a desired pattern can be obtained with a desired dimension. The time for immersing the SOI substrate on which the resist layer is formed in the developer is determined so that the resist layer with the latent image printed thereon is immersed in the developer and a desired pattern can be formed with a desired dimension. During this period, the SOI substrate is immersed in the developer. Thereafter, the entire SOI substrate is dried to cure the resist. As described above, the second resist pattern 407 can be formed.

Next, the second silicon layer 405 is etched using the second resist pattern 407 as a mask (FIG. 4H), and then the second resist pattern 407 is removed. As a result, as shown in the cross-sectional view of FIG. 4I and the plan view of FIG. 4J, the first electrode 481a and the two first wall electrodes 482a electrically connected to the side portions in the arrangement direction of the first electrodes 481a, A first wiring 483a connected to the first electrode 481a is formed. For example, in DRlE it is a deep engraving technique for Si which is a known technique, by using SF ₆ as an etching gas, can be performed above etching. Here, etching is performed until the buried insulating layer 402 is exposed. 4I shows a cross section taken along line aa in FIG. 4J. Other configurations are the same as those in the first to third embodiments.

  As described above, also in the present embodiment, a MEMS element including a mirror array using wall electrodes can be more easily manufactured as in the first embodiment.

  Here, the wall electrode will be described with reference to FIGS. 5A to 5D. As shown in FIG. 5A, in a simple parallel plate type electrostatic drive type device, a plate-like electrode 502 is arranged to face a plate-like movable beam 501. In this case, regardless of the displacement of the movable beam 501, in the region where the movable beam 501 overlaps the electrode 502, an electric field as indicated by an arrow line is acting substantially perpendicular to the movable beam 501. On the other hand, the electric field is deformed to draw an arc at the end of the movable beam 501. Although the electric field at the end is deformed, the electric field at the end acts to attract the movable beam 501 to the electrode 502.

  In this case, as the voltage applied between the movable beam 501 and the electrode 502 is increased, the displacement of the movable beam 501 increases as shown in FIG. 5B, and finally the restoring force of the spring against the electrostatic attractive force. In this case, the movable beam 501 cannot collide with the electrode 502 and partly collides with the electrode 502.

  5C, when the wall electrode 512 is provided in addition to the electrode 511, when the displacement of the movable beam 501 is small, the movable beam 501 is connected to both the wall electrode 512 and the electrode 511. An electric field is formed in the direction of pulling down the lower side of the figure. On the other hand, as shown in FIG. 5D, when the displacement of the movable beam 501 structure increases and approaches the electrode 511 and the movable beam 501 structure enters between the two wall electrodes 512, the upper portion of the wall electrode 512 and the movable beam The electric field formed between the end portions of 501 forms an electrostatic force that acts in a direction (upward in the figure) that separates the movable beam 501 from the electrode 511 side.

  For this reason, when the wall electrode 512 is provided, even if the displacement of the movable beam 501 increases, the two wall electrodes 512 exert a large upward pulling effect, so that the above-described sudden collision does not occur. The movable beam 501 structure can be displaced, and the usable area of the MEMS device can be increased.

  Further, by using the wall electrode 512, there is a shielding effect for blocking the electric field from the adjacent electrode 502. Thereby, various interference between adjacent mirror elements can be suppressed, and a plurality of mirror elements can be placed closer to each other.

  DESCRIPTION OF SYMBOLS 101 ... Base part, 102 ... Embedded insulating layer, 103 ... Silicon layer, 104 ... 1st resist pattern, 105 ... 2nd resist pattern, 105a ... Opening, 109a, 109a ... Connection part, 113 ... 1st electrode pattern, 113a ... Groove part 141a ... first electrode, 141b ... second electrode, 142a ... first wall electrode, 142b ... second wall electrode, 143a ... first wiring, 143b ... second wiring, 184a ... first movable beam, 184b ... second Movable beam.

Claims (5)

A first step of forming a first resist pattern on the silicon layer of the SOI substrate including a base, a buried insulating layer on the base, and a silicon layer on the buried insulating layer;
The silicon layer is etched using the first resist pattern as a mask, and a plurality of sets of first electrode patterns and second electrode patterns arranged in a line at predetermined intervals, the first electrode patterns, and the second electrode patterns A second step of forming a first wiring pattern and a second wiring pattern connected to the electrode pattern;
After removing the first resist pattern, a third step of forming a second resist pattern having an opening at the center of the first electrode pattern and the second electrode pattern;
The first electrode pattern and the second electrode pattern are etched using the second resist pattern as a mask, and a central portion of the first electrode pattern and the second electrode pattern is etched, and the first electrode and the second electrode arranged in a row at a predetermined interval; Two first wall electrodes electrically connected to side portions in the arrangement direction of the electrodes, two second wall electrodes electrically connected to side portions in the arrangement direction of the second electrodes, the first electrode, and A fourth step of forming a first wiring and a second wiring connected to the second electrode;
After removing the second resist pattern, one end is fixed on the SOI substrate and the other end is displaceable. A plurality of sets of first movable beams and second movable beams arranged in a row corresponding to the upper portions of the electrode and the second electrode, and between two adjacent sets of the first movable beam and the second movable beam. And the mirrors supported at four positions by the two sets of the first movable beam and the second movable beam, and the first movable beam and the second movable beam for supporting the mirror. And a fifth step of forming each of the other ends and four connecting portions for connecting the mirrors. A method for manufacturing a MEMS device, comprising: In the manufacturing method of the MEMS element of Claim 1,
The SOI substrate includes a base, a first buried insulating layer on the base, a first silicon layer on the first buried insulating layer, a second buried insulating layer on the first silicon layer, and the second buried insulation. A second silicon layer on the layer,
In the second step, the second silicon layer, the second buried insulating layer, and the first silicon layer are etched using the first resist pattern as a mask,
In the fourth step, the second silicon layer and the second buried insulating layer are etched using the second resist pattern as a mask. A first step of forming a first resist pattern on the silicon layer of the SOI substrate including a base, a buried insulating layer on the base, and a silicon layer on the buried insulating layer;
A second step of etching the silicon layer using the first resist pattern as a mask to form a plurality of sets of first opening patterns and second opening patterns arranged in a row at a predetermined interval;
A third step of forming a second resist pattern covering the first opening pattern and the second opening pattern after removing the first resist pattern;
Etching the silicon layer in which the first opening pattern and the second opening pattern are formed using the second resist pattern as a mask, and a first electrode and a second electrode arranged in a row at a predetermined interval; Two first wall electrodes that are electrically connected to side portions in the arrangement direction of the first electrodes; two second wall electrodes that are electrically connected to side portions in the arrangement direction of the second electrodes; A fourth step of forming a first wiring and a second wiring connected to the first electrode and the second electrode;
After removing the second resist pattern, one end is fixed on the SOI substrate and the other end is displaceable. A plurality of sets of first movable beams and second movable beams arranged in a row corresponding to the upper portions of the electrode and the second electrode, and between two adjacent sets of the first movable beam and the second movable beam. And the mirrors supported at four locations by the two sets of the first movable beam and the second movable beam, and the first movable beam and the second movable beam for supporting the mirror. And a fifth step of forming each of the other ends and the four connecting portions for connecting the mirrors. In the manufacturing method of the MEMS element of Claim 3,
The SOI substrate includes a base, a first buried insulating layer on the base, a first silicon layer on the first buried insulating layer, a second buried insulating layer on the first silicon layer, and the second buried insulation. A second silicon layer on the layer,
In the second step, the second silicon layer and the second buried insulating layer are etched using the first resist pattern as a mask,
In the fourth step, the second silicon layer, the second buried insulating layer, and the first silicon layer are etched using the second resist pattern as a mask.   The MEMS element manufactured by the manufacturing method of the MEMS element of any one of Claims 1-4.

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