JP2010183617A - Transmission control signal receiver and terrestrial digital television broadcast receiver using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission control signal receiver for receiving a transmission control signal with use of a simple circuit structure, and to provide a terrestrial digital television broadcast receiver using the transmission control signal receiver. <P>SOLUTION: The transmission control signal receiver receives a transmission control signal carrier of terrestrial digital television broadcast and demodulates the transmission control signal carrier into a transmission control signal. The transmission control signal receiver includes an orthogonal demodulation circuit 42 for performing an orthogonal demodulation on a received signal using a frequency signal that is set to a center frequency of a plurality of transmission control signal carriers, a transmission control signal carrier receiving circuit 44 for simultaneously receiving the plurality of transmission control signal carriers from an output of the orthogonal demodulation circuit 42, and a detector circuit 46 for executing detection through diversity synthesis of the plurality of transmission control signal carriers received in the transmission control signal carrier receiving circuit 44. The transmission control signal includes a start-up flag for emergent alert broadcast. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission control signal receiver and a terrestrial digital television broadcast receiver using the transmission control signal receiver, and a transmission control signal receiver for receiving a transmission control signal of terrestrial digital television broadcast and a terrestrial digital television broadcast using the same. Regarding the receiver.

  At present, an OFDM (Orthogonal Frequency Division Multiplexing) transmission method called ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) has been put into practical use as a transmission method for terrestrial digital broadcasting.

  FIG. 1 shows a block diagram of an example of an analog television broadcast receiver that receives a conventional emergency alert broadcast. An antenna reception signal output from the reception antenna 1 is input to the analog television broadcast tuner 2. The video signal and audio signal output from the analog television broadcast tuner 2 are input to the receiver 3. The analog television broadcast tuner 2 is fed from a power source 4 through a feeder line 5.

  In order to receive the emergency alert broadcast, the demodulation system of the analog television broadcast tuner 2 needs to be in an operating state. On the other hand, the receiver 3 is supplied with power from the power source 4 through the power supply line 6 and through the switch 7. In the standby state, the power source of the receiver 3 is turned off by the switch 7.

  When the analog television broadcast tuner 2 receives the emergency warning broadcast start flag, the switch-on signal 8 is output from the analog television broadcast tuner 2 to the switch 7, the switch 7 is turned on, and the receiver 3 is supplied with power and operates. It becomes.

  As with analog television broadcasting, in order to activate a receiver by emergency warning broadcasting in terrestrial digital television broadcasting, the demodulation system of the digital terrestrial television broadcasting receiver can receive the emergency warning broadcasting activation flag of the transmission control signal. Must be kept in a powered state.

  FIG. 2 is a block diagram showing an example of a demodulation system of the terrestrial digital television broadcast receiver. The antenna reception signal received by the reception antenna is supplied to the channel selection unit 10 and the signal of the designated channel is selected. This signal is digitized, and then orthogonally demodulated by the orthogonal demodulation unit 11 and supplied to the synchronous reproduction unit 12 and the FFT unit 13.

  The synchronous reproduction unit 12 reproduces the OFDM symbol synchronization and the FFT sample frequency according to the mode and the guard interval length. The FFT unit 13 performs an FFT (Fast Fourier Transform) operation for the effective symbol period of the OFDM symbol. The frame extraction unit 14 extracts a frame synchronization signal from a TMCC (Transmission and Multiplexing Configuration Control: transmission control signal) signal output from the FFT unit 13. The TMCC decoding unit 15 extracts various control information including an emergency warning broadcast activation flag from the TMCC signal.

  The carrier demodulation unit 16 performs carrier demodulation according to the TMCC information and detects amplitude and phase information. The demapping section 17 performs QPSK, 16QAM and 64QAM demapping from the carrier demodulated information to extract bit information. The TS playback unit 18 performs processing for transport stream playback. The RS decoding unit 19 decodes the shortened Reed-Solomon code, and decodes baseband MPEG-TS (Transport Stream).

  As an emergency alert broadcast receiving system that receives an emergency alert broadcast that is broadcast superimposed on a BS television broadcast, for example, there is a system described in Patent Document 1.

JP 2004-23591 A

  In a conventional digital terrestrial television broadcast receiver, a signal of a designated channel is orthogonally demodulated, an FFT operation is performed, a frame synchronization signal is extracted, and a TMCC signal is extracted, and a TMCC signal (transmission control signal) is obtained. There is a problem that the circuit configuration for taking out is complicated.

  According to the format of the ISDB-T signal (ARIB STD-B31), there are a plurality of TMCC signals in one segment, and there are four TMCC carriers in one segment of mode 3. Above the TMCC carrier, all TMCC carriers are the same. For this reason, if the transmission control signal is extracted using a plurality of TMCC carriers, the reception sensitivity of the transmission control signal can be improved.

  For example, it is conceivable to extract a TMCC carrier having a predetermined frequency from a plurality of TMCC carriers with a bandpass filter, perform quadrature detection of the TMCC carrier, delay detect quadrature detection output, and extract a transmission control signal. When a transmission control signal is taken out from a plurality of circuits, a plurality of band filter circuits, quadrature detection circuits, and delay detection circuits are required, resulting in a complicated circuit configuration.

  The present invention has been made in view of the above points, and provides a transmission control signal receiver capable of receiving a transmission control signal with a simple circuit configuration and a terrestrial digital television broadcast receiver using the same. Objective.

The present invention relates to a transmission control signal receiver that receives a transmission control signal carrier for terrestrial digital television broadcasting and demodulates a transmission control signal from the transmission control signal carrier.
Orthogonal demodulation means for orthogonally demodulating a received signal using a frequency signal set to the center frequency of a plurality of transmission control signal carriers;
Transmission control signal carrier receiving means for simultaneously receiving the plurality of transmission control signal carriers from the output signal of the orthogonal demodulation means;
Detecting means for performing diversity combining of the plurality of transmission control signal carriers received by the transmission control signal carrier receiving means, and performing detection;
The transmission control signal includes an emergency warning broadcast activation flag. Thereby, a transmission control signal receiver can be made into a simple structure, and low power consumption can be achieved. The plurality of transmission control signal carriers may be a plurality of TMCC carriers and / or AC carriers.

The present invention is a terrestrial digital television broadcast receiver having the transmission control signal receiver,
When the transmission control signal receiver detects an emergency warning broadcast start flag in the transmission control signal, the digital terrestrial television receiver is powered by supplying power to the tuner of the terrestrial digital television broadcast receiver based on the detection result. The standby power in the broadcast receiver can be reduced.

  According to the present invention, standby power for receiving a transmission control signal can be reduced.

It is a block diagram of an example of the conventional analog television broadcast receiver. It is a block diagram of an example of a demodulation system of a terrestrial digital television broadcast receiver. It is a block diagram of one embodiment of a TMCC receiving circuit. It is a figure which shows the relationship of the frequency of two TMCC carriers. 2 is a block diagram of an embodiment of an orthogonal demodulation circuit. FIG. It is a block diagram of 1st Embodiment of a TMCC carrier receiving circuit. It is a block diagram of one embodiment of a DBPSK delay detection circuit. It is a block diagram of 2nd Embodiment of a TMCC carrier receiving circuit. It is a figure which shows two TMCC carrier arrangement | positioning. It is a block diagram of 1st Embodiment of a TMCC receiving circuit. It is a block diagram of 2nd Embodiment of a TMCC receiving circuit. It is a block diagram of 3rd Embodiment of a TMCC carrier receiving circuit. 2 is a block diagram of an embodiment of a diversity combining circuit. FIG. It is a block diagram of 3rd Embodiment of a TMCC receiving circuit. 1 is a block diagram of an embodiment of a digital terrestrial television broadcast receiver to which a transmission control signal receiver of the present invention is applied. It is a block diagram of one Embodiment of a TMCC receiving circuit and a power supply control circuit. It is a figure for demonstrating two intermittent reception modes. It is a figure for demonstrating the out-of-frame intermittent reception mode. It is a figure for demonstrating the intermittent reception mode in a frame.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 shows a block diagram of one embodiment of the TMCC receiver circuit 24. In the figure, the TMCC reception circuit 24 includes at least a frequency conversion circuit 40, an AD conversion circuit 41, an orthogonal demodulation circuit 42, a TMCC carrier reception circuit 44, a DBPSK delay detection circuit 46, a determination circuit 47, and a TMCC. A synchronization detection circuit 48 and an EWS detection circuit 49 are included. Furthermore, an AFC circuit including a complex multiplication circuit 43 and an adaptive phase control circuit 45 is used as necessary.

  A UHF band ISDB-T signal, which is a received signal received by the antenna, is supplied to the frequency conversion circuit 40 and converted into an intermediate frequency signal. The intermediate frequency signal is digitized by the AD conversion circuit 41 and then quadrature demodulated by the quadrature demodulation circuit 42, and the I signal (in-phase component) and the Q signal (quadrature component) are supplied to the TMCC carrier reception circuit 44. The TMCC carrier reception circuit 44 demodulates the TMCC carrier and supplies it to the DBPSK delay detection circuit 46.

  The adaptive phase control circuit 45 separates the frequency error of the sine wave oscillation circuit in the TMCC carrier reception circuit 44, and the complex multiplication circuit 43 performs complex multiplication so as to eliminate the frequency error.

  The TMCC carrier is subjected to delay detection by the DBPSK delay detection circuit 46, and then determined to 0 or 1 by the determination circuit 47, whereby a bit stream of the TMCC signal is obtained. This TMCC signal is supplied to the TMCC synchronization detection circuit 48 and the EWS detection circuit 49.

  The TMCC synchronization detection circuit 48 performs coincidence detection between the demodulated TMCC signal and a known TMCC differential demodulation reference 1 bit, a synchronization signal 16 bits, and a segment format identification 3 bits, a total of 20 bits. When the two coincide with each other, a TMCC synchronization signal is generated at the head timing of the demodulated TMCC signal. Further, TMCC synchronization establishment information indicating the presence / absence of TMCC synchronization establishment is generated based on the TMCC synchronization signal. The TMCC synchronization signal is supplied to the EWS detection circuit 49.

  The EWS detection circuit 49 monitors the presence / absence of the 26th bit emergency warning broadcast activation flag of the TMCC signal, and switches on when it detects that the value of the emergency warning broadcast activation flag is “1: with activation control”. Output a signal.

  Next, the TMCC receiving circuit 24 that performs simple demodulation using two TMCC carriers will be described.

  According to the format of the ISDB-T signal (ARIB STD-B31), there are a plurality of TMCC signals in one segment, and there are four TMCC carriers in one segment of mode 3. In the present invention, two of these TMCC carriers are demodulated simultaneously.

FIG. 4 shows the frequency relationship between two TMCC carriers. In the figure, the frequency interval between the first TMCC carrier (TMCC-N) and the second TMCC carrier (TMCC-P) is Δf, and the center frequency of the two TMCC carriers is the intermediate frequency f. Set to _IF .

Here, it is considered that the information of the two TMCC carriers TMCC-N and TMCC-P set in this way is demodulated. The two TMCC carriers r (t) converted to the intermediate frequency f _IF are expressed as in equation (1).

Here, the angular frequency Δω = 2πΔf and the angular intermediate frequency ω _IF = 2πf _IF . The DBPSK modulation signal Z is a complex number, and Z also has the meaning of undergoing DBPSK modulation of 0 degrees and 180 degrees according to the differential demodulation reference of bit 0 of the TMCC signal. The sign “±” in the first term on the right side of the equation (1) is based on the ARIB STD-B31 standard, and is assumed to be DBPSK modulation with opposite phases depending on the pair that selects two TMCC carriers. is there.

FIG. 5 shows a block diagram of an embodiment of the quadrature demodulation circuit 42. In the figure, two TMCC carriers r (t) converted to an intermediate frequency f _IF are supplied to a terminal 60, branched into two by a distributor 61, and supplied to multipliers 62 and 63. The multiplier 62 multiplies the signal r (t) by the sine wave generated by the sine wave oscillation circuit 64. The output of the multiplier 62 is output as an in-phase component (I signal) through a low-pass filter (LPF) 66.

  On the other hand, the multiplier 63 multiplies the signal r (t) by a signal obtained by shifting the sine wave generated by the sine wave oscillation circuit 64 by π / 2 by the π / 2 phase shifter 65. The output of the multiplier 63 is output as a quadrature component (Q signal) through the low-pass filter 67.

  In the following description, regarding the polarity of DBPSK modulation of this TMCC carrier, the polarity of DBPSK modulation between TMCC-N and TMCC-P is the same polarity, and the polarity of DBPSK modulation between TMCC-N and TMCC-P is opposite. Each of the different polarities is described separately.

When the two TMCC carriers r (t) converted to the intermediate frequency f _IF are multiplied by the sine wave cos (ω _IF t + δ) output from the sine wave oscillation circuit 64 including the frequency error δ, the output from the multiplier 62 is obtained. The in-phase component r ^ _I (t) is expressed by the following equation from the formula for converting the product derived from the addition theorem into a sum.

Further, when 2ω _IF is removed by the low-pass filter 66, the in-phase component r ^ _I (t) is expressed by the equation (2). Incidentally, LPF [] is meant the removal of double frequency component of the fundamental frequency omega _IF.

Similarly, the quadrature component r _Q (t) output from the low-pass filter 67 is expressed by equation (3).

FIG. 6 shows a block diagram of the first embodiment of the TMCC carrier reception circuit 44. In the figure, the in-phase component r ^ _I (t) output from the quadrature demodulation circuit 42 is supplied to the adder 71, and the quadrature component r ^ _Q (t) is phase-shifted by π / 2 by the π / 2 phase shifter 72. And supplied to the adder 71. The output signal of the adder 71 is branched into two and supplied to the multipliers 73 and 74.

  The multiplier 73 multiplies the output signal of the adder 71 by the cosine wave having the frequency Δf / 2 generated by the cosine wave oscillation circuit 75 and outputs the result. The output of the multiplier 73 is averaged for one effective symbol period by the average addition circuit 77 and output, and supplied to the subsequent DBPSK delay detection circuit 46.

  On the other hand, the multiplier 74 multiplies the output signal of the adder 71 by a sine wave obtained by shifting the cosine wave of the frequency Δf / 2 generated by the cosine wave oscillation circuit 75 by π / 2 by the π / 2 phase shifter 76. And output. The output of the multiplier 74 is output after being averaged for one effective symbol period by the average adding circuit 78 and supplied to the subsequent DBPSK delay detection circuit 46.

When the orthogonal component r _Q (t) represented by the above equation (3) is phase-shifted by Δf / 2, it is represented by the following equation (4).

  Therefore, the output signal of the adder 71 is expressed by equation (5) by the addition theorem.

  In the equation (5), a result that is not affected by a code that is assumed to be subjected to DBPSK modulation with opposite phases can be obtained. Further, when orthogonal synchronous detection is performed with Δf / 2 in equation (5), a DBPSK modulation signal Z including a frequency error δ is obtained. Here, the in-phase component output from the average addition circuit 77 is expressed by the following equation. LPF [] means that the Δωt component is removed by the low-pass filter function of the average addition circuits 77 and 78.

  Similarly, the orthogonal component output from the average addition circuit 78 is expressed by the following equation.

  As a result, the DBPSK modulation signal Z output from the multipliers 73 and 74 is expressed by equation (6).

From the equation (6), it can be seen that the phase of the DBPSK modulation signal Z rotates due to the frequency error δ. The term ^ejδ is a component removed by the subsequent DBPSK delay detection circuit 46. Here, DBPSK delay detection is the product of the current symbol and the complex conjugate of the previous symbol (one symbol past). Accordingly, in DBPSK delay detection, the term of e ^jδ is removed and Z / 2 is demodulated under the condition that the change in the error e ^jδ between symbols is sufficiently small.

  Assuming that the effective symbol of the ISDB-T modulation signal is N samples, assuming that the input signal of the average adder circuits 77 and 78 is SIN and the output signal is SOUT, the average adder circuits 77 and 78 perform the calculation of equation (7). .

  The TMCC carrier can be demodulated by averaging one effective symbol period for each of the real part and imaginary part of the signal subjected to quadrature synchronous detection at Δf / 2.

FIG. 7 shows a block diagram of an embodiment of the DBPSK delay detection circuit 46. In the figure, the in-phase component S _I (t) supplied to the terminal 81 is supplied to the multiplier 82 and the delay unit 83. The multiplier 82 multiplies the signal S _I (t) supplied from the terminal 81 by the signal S _I (t−T) delayed by one symbol period (T) by the delay unit 83 and supplies the product to the adder circuit 84.

Further, the orthogonal component S _Q (t) supplied to the terminal 85 is supplied to the multiplier 86 and the delay unit 87. The multiplier 86 multiplies the signal S _Q (t) supplied from the terminal 85 by the signal S _Q (t−T) delayed by one symbol period (T) by the delay unit 87 and supplies the product to the adder circuit 84. The adder circuit 84 outputs the detection result.

  Here, the signal supplied to the DBPSK delay detection circuit 46 is expressed by the following equation.

S (t) = S _I (t) + jS _Q (t)
However, t is arbitrary time. The delayed detection signal d (t) is expressed by the following equation.

d (t) = S (t) · S ^* (t−T)
= {S _I (t) + jS _Q (t)} · {S _I (t−T) −jS _Q (t−T)}
= [S _I (t) · S _I (t−T) + S _Q (t) · S _Q (t−T)]
+ J [S _Q (t) · S _I (t−T) −S _I (t) · S _Q (t−T)]
However, S ^* is a complex conjugate of S. In DBPSK modulation, since the modulation signal is not included on the imaginary axis side, the real axis side component Re [d (t)] is output from the adder circuit 84.

Re [d (t)] = S _I (t) · S _I (t−T) + S _Q (t) · S _Q (t−T)
The bit stream of the TMCC signal can be obtained by determining the sign of the signal Re [d (t)] by the determination circuit 47.

  Next, let us consider orthogonal detection of the equations (2) and (3) as they are at the frequency Δf / 2.

FIG. 8 shows a block diagram of a second embodiment of the TMCC carrier reception circuit 44. In the figure, an in-phase component r _I (t) output from the quadrature demodulation circuit 42 is supplied to a multiplier 91, and a quadrature component r _Q (t) is supplied to a multiplier 92.

  The cosine wave having the frequency Δf / 2 generated by the cosine wave oscillation circuit 93 is supplied to the a terminal of the selection circuit 94, and this cosine wave is phase-shifted by π / 2 by the π / 2 phase shifter 95 to be a sine wave. And supplied to the terminal b of the selection circuit 94. The selection circuit 94 selects either the a terminal or the b terminal and supplies it to the multipliers 91 and 92.

  The multiplier 91 multiplies the in-phase component by a sine wave or cosine wave having a frequency Δf / 2 and outputs the result. The output of the multiplier 91 is output after the average addition circuit 96 performs an average addition for one effective symbol period, and is supplied to the subsequent DBPSK delay detection circuit 46.

  The multiplier 92 multiplies the orthogonal component by a sine wave or cosine wave having a frequency Δf / 2 and outputs the result. The output of the multiplier 92 is output after being averaged for one effective symbol period by the average adder circuit 97 and supplied to the subsequent DBPSK delay detection circuit 46.

  Here, the average adder circuit 96 output is expressed by equations (8) and (9), and the average adder circuit 97 output is expressed by equations (10) and (11). Note that LPF [] means that the frequency component twice the fundamental frequency (Δωt) / 2 is removed by the low-pass filter function of the average addition circuits 96 and 97. When the selection circuit 94 selects the a side, that is, the cosine wave having the frequency Δf / 2, the equations (8) and (10) are expressed by the selection circuit 94. This represents a case where a sine wave is selected.

Here, in order for the DBPSK delay detection circuit 46 to correctly demodulate, it may be in the form of Z {cos (δ) + jsin (δ)} = Ze ^jδ . For this reason, Formula (12) is obtained. When the selection circuit 94 selects the a side, that is, the cosine wave having the frequency Δf / 2, the equations (9) and (11) are expressed by the selection circuit 94 in the b side, that is, the frequency Δf /. The case where 2 sine waves are selected is shown. Although the phase rotation direction due to the frequency error δ is different between the a side and the b side, there is no problem because the phase component is eliminated at the output of the DBPSK delay detection circuit 46.

  FIG. 9 shows an arrangement of two TMCC carriers in which the ISDB-T modulation signal is mode 3 and the intra-segment carrier numbers are # 101 and # 349 from one central segment. In addition, the carrier number seen from all the carriers is shown in parentheses.

  FIG. 10 shows a block diagram of a first embodiment of a TMCC receiving circuit that demodulates two TMCC carriers of carrier numbers # 101 and # 349.

In the figure, the received ISDB-T signal (center frequency f _IF = 124/63 MHz) passes through a band filter (BPF) that passes a band including two TMCC carriers of carrier numbers # 101 and # 349. 102. The AD converter 102 samples the signal with a clock having a frequency of 124/63 MHz and supplies the sampled signal to the distributor 103 in the quadrature demodulation circuit 42.

  The quadrature demodulation circuit 42 operates with a clock having a frequency of 124/63 MHz. The multiplier 104 adds “1, 0, −1, 0” from the coefficient sequence generation circuit 105 to the signal from the distributor 103 as the clock. After being multiplied by the coefficient sequence repeated in step (3), the result is supplied to the down-sampling circuit 107 through the low-pass filter 106. The downsampling circuit 107 downsamples the supplied signal at 4: 1 to extract an in-phase component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  Note that the multiplier outputs the signal as it is when it is multiplied by “1”, outputs the signal with the sign inverted when it is multiplied by “−1”, and omits the calculation when it is multiplied by “0”. As a result, the circuit can be simplified as compared with the FFT operation.

  The multiplier 108 multiplies the signal from the distributor 103 by the coefficient sequence that repeats “0, 1, 0, −1” from the coefficient sequence generation circuit 109 with the above clock, and then passes through the low-pass filter 110 to the down-sample circuit 111. To supply. The down-sampling circuit 111 down-samples the supplied signal at 4: 1, extracts the quadrature component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  The TMCC carrier reception circuit 44 operates with a clock having a frequency of 31/63 MHz, and the orthogonal component is delayed by one clock by the delay unit 120 and supplied to the multiplier 121. The multiplier 121 multiplies the supplied in-phase component by the delayed quadrature component and supplies the product to the multipliers 122 and 125.

  The multiplier 122 multiplies the signal from the multiplier 121 by the coefficient sequence in which “1, 0, −1, 0” from the coefficient sequence generation circuit 123 is repeated with the clock, and supplies the result to the average addition circuit 124. The average addition circuit 124 performs an average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent DBPSK delay detection circuit 46.

  The multiplier 125 multiplies the signal from the multiplier 121 by “0, 1, 0, −1” from the coefficient sequence generation circuit 126 by a coefficient sequence that repeats at the clock, and supplies the result to the average addition circuit 127. The average addition circuit 127 performs an average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent DBPSK delay detection circuit 46.

  FIG. 11 shows a block diagram of a second embodiment of a TMCC receiving circuit that demodulates two TMCC carriers of carrier numbers # 101 and # 349. In the figure, the same parts as those in FIG.

In FIG. 11, the received ISDB-T signal (center frequency f _IF = 124/63 MHz) passes through a band filter (BPF) that passes a band including two TMCC carriers of carrier numbers # 101 and # 349, and an AD converter. 102. The AD converter 102 samples the signal with a clock having a frequency of 124/63 MHz and supplies the sampled signal to the distributor 103 in the quadrature demodulation circuit 42.

  The quadrature demodulation circuit 42 operates with a clock having a frequency of 124/63 MHz. The multiplier 104 adds “1, 0, −1, 0” from the coefficient sequence generation circuit 105 to the signal from the distributor 103 as the clock. After being multiplied by the coefficient sequence repeated in step (3), the result is supplied to the down-sampling circuit 107 through the low-pass filter 106. The downsampling circuit 107 downsamples the supplied signal at 4: 1 to extract an in-phase component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  Note that the multiplier outputs the signal as it is when it is multiplied by “1”, outputs the signal with the sign inverted when it is multiplied by “−1”, and omits the calculation when it is multiplied by “0”. As a result, the circuit can be simplified as compared with the FFT operation.

  The multiplier 108 multiplies the signal from the distributor 103 by the coefficient sequence that repeats “0, 1, 0, −1” from the coefficient sequence generation circuit 109 with the above clock, and then passes through the low-pass filter 110 to the down-sample circuit 111. To supply. The down-sampling circuit 111 down-samples the supplied signal at 4: 1, extracts the quadrature component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  The TMCC carrier reception circuit 44 operates with a clock having a frequency of 31/63 MHz, and the multiplier 131 supplies “0, 1, 0, −1” supplied from the coefficient string generation circuit 133 on the b terminal side of the selection circuit 132. Is multiplied by the in-phase component supplied from the complex multiplier circuit 43 and then supplied to the average adder circuit 134. The average addition circuit 134 performs average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent DBPSK delay detection circuit 46.

  The multiplier 135 is an orthogonal unit supplied from the complex multiplier circuit 43 for a coefficient sequence that repeats “0, 1, 0, −1” supplied from the coefficient sequence generation circuit 133 on the b terminal side of the selection circuit 132 using the clock. After the components are multiplied, the result is supplied to the average addition circuit 136. The average addition circuit 136 performs average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent DBPSK delay detection circuit 46.

  The reason why the selection circuit 132 selects the coefficient sequence from the coefficient sequence generation circuit 133 on the b terminal side is that the two TMCC carriers of carrier numbers # 101 and # 349 have opposite polarities, In the case of the same phase, the selection circuit 132 selects the coefficient sequence “1, 0, −1, 0” from the coefficient sequence generation circuit 137 on the a terminal side.

  10 and 11, assuming that the sampling frequency of the quadrature demodulation circuit 43 by AD conversion and digital signal processing is 124/63 MHz, the sine wave oscillation circuit 64 and the π / 2 phase shifter 65 in the quadrature demodulation circuit shown in FIG. Can be replaced with two coefficient string generation circuits, and the circuit can be greatly reduced. Similarly, the sine wave oscillator and the π / 2 phase shifter in the TMCC carrier receiving circuit 44 can be replaced with two coefficient sequence generation circuits, and the circuit can be greatly reduced.

  Further, the π / 2 phase shifter 76 of the TMCC carrier receiving circuit in FIG. 6 can be realized and simplified by the delay unit 120 as shown in FIG.

  In the above description, the coefficient sequence “0, 1, 0, −1” is associated with the coefficient sequence “1, 0, −1, 0”. May be made to correspond.

  In this way, by using the two TMCC carriers and demodulating with the circuits shown in FIGS. 10 and 11, the power consumption of the digital demodulation circuit can be reduced and the circuit can be simplified.

  In FIG. 6, even if the oscillation frequency Δf / 2 of the cosine wave oscillator 75 changes, the amplitude of the output of the DBPSK delay detection circuit 46 is not affected. In FIG. 10, the clock of the frequency 31/63 MHz of the TMCC carrier reception circuit 44 is obtained. Even if it fluctuates, the amplitude of the output of the DBPSK delay detection circuit 46 is not affected. However, in FIG. 8, if the oscillation frequency Δf / 2 of the cosine wave oscillator 93 fluctuates, the amplitude of the output of the DBPSK delay detection circuit 46 varies. In FIG. 11, if the clock of the frequency 31/63 MHz of the TMCC carrier receiving circuit 44 fluctuates, the amplitude of the output of the DBPSK delay detection circuit 46 fluctuates. An embodiment for preventing such fluctuations in the amplitude of the output of the DBPSK delay detection circuit 46 will be described.

FIG. 12 shows a block diagram of a third embodiment of the TMCC carrier reception circuit 44. In the figure, the in-phase component r ^ _I (t) output from the quadrature demodulation circuit 42 is supplied to multipliers 141 and 144, and the quadrature component r ^ _Q (t) is supplied to multipliers 142 and 143.

  The cosine wave having the frequency Δf / 2 generated by the cosine wave oscillation circuit 145 is supplied to the multipliers 141 and 143, and the cosine wave is phase-shifted by π / 2 by the π / 2 phase shifter 146 to form a sine wave. And supplied to the multipliers 142 and 144.

  The multiplier 141 multiplies the in-phase component by a cosine wave having a frequency Δf / 2 and outputs the result. The output of the multiplier 141 is output after being average-added for one effective symbol period by the average adder circuit 147 and supplied to the subsequent diversity combiner circuit 152.

  The multiplier 142 multiplies the orthogonal component by a sine wave having a frequency Δf / 2 and outputs the result. The output of the multiplier 142 is averaged for one effective symbol period by the average addition circuit 148 and output, and is supplied to the subsequent diversity combining circuit 152.

  The multiplier 143 multiplies the orthogonal component by a cosine wave having a frequency Δf / 2 and outputs the result. The output of the multiplier 143 is output after the average addition circuit 149 performs an average addition for one effective symbol period, and is supplied to the subsequent diversity combining circuit 152.

  Multiplier 144 multiplies the in-phase component by a sine wave of frequency Δf / 2 and outputs the result. The output of the multiplier 144 is output after the average addition circuit 150 performs an average addition for one effective symbol period and is supplied to the subsequent diversity combining circuit 152.

  Here, each of the output signals I · i, Q · q, Q · i, and I · q of the average addition circuits 147 to 150 is expressed by equations (13) to (16). Note that Tu is an effective symbol length in the ISDB-T system, and ε represents an oscillation frequency error of the cosine wave oscillator 145.

  The average adder circuits 147 to 150 have a role of a low-pass filter, and remove frequency components other than TMCC-N and TMCC-P carriers and remove Δωt components of the equations (13) to (16). The signals I · i, Q · q, Q · i, and I · q that are output from the average adder circuits 147 to 150 are expressed by equations (17) to (20), respectively. LPF [] means that the Δωt component is removed by the low-pass filter function of the average addition circuits 147 to 150.

  FIG. 13 shows a block diagram of an embodiment of diversity combining circuit 152. In the figure, diversity combining circuit 152 includes a TMCC-N carrier detection circuit comprising subtractor 153, adder 154 and DBPSK delay detection circuit 155, and a TMCC comprising adder 157, subtractor 158 and DBPSK delay detection circuit 159. -P carrier detection circuit and adder 160.

The subtractor 153 supplies the signal S _I (t) obtained by subtracting the signal LPF [Q · q] from the signal LPF [I · i] to the DBPSK delay detection circuit 155. The adder 154 supplies a signal S _Q (t) obtained by adding the signal LPF [I · q] to the signal LPF [Q · i] to the DBPSK delay detection circuit 155. The TMCC-N carrier S _N (t) composed of the signals S _I (t) and S _Q (t) is expressed by equation (21).

The adder 157 supplies the signal S _I (t) obtained by adding the signal LPF [Q · q] to the signal LPF [I · i] to the DBPSK delay detection circuit 159. The subtractor 158 supplies a signal S _Q (t) obtained by subtracting the signal LPF [I · q] from the signal LPF [Q · i] to the DBPSK delay detection circuit 159. The TMCC-P carrier S _P (t) composed of the signals S _I (t) and S _Q (t) is expressed by the equation (22).

The DBPSK delay detection circuit 155 detects the TMCC-N carrier S _N from both signals, generates a signal d _N (t), and supplies it to the adder 160. Further, DBPSK delay detection circuit 159 supplies the generated adder 160 a signal _d P by detecting a TMCC-P carrier _{S P} from the two signals (t). If each of the DBPSK delay detection circuits 155 and 159 is delayed by one symbol period (T), the modulated signal is included only in the real part in the DBPSK modulation, so that the signals d _N (t) and d _P (t ) Each is expressed by equations (23) and (24). However, S ^* _N and S ^* _P are complex conjugates of S _N and S _P , respectively.

  The output of the diversity combining circuit 152 obtained by adding the expressions (23) and (24) is expressed by the expression (25), and it can be seen that the output fluctuation due to the influence of the oscillation frequency error ε of the cosine wave oscillator 145 does not occur.

Re [d _P (t)] + Re [d _N (t)] = (Z (t) · Z (t−T)) / 2
... (25)
Here, since the output of the diversity combining circuit 152 is the sum of the outputs of the DBPSK delay detection circuits 155 and 159, it becomes twice the output of the DBPSK delay detection circuit 46 shown in FIGS. The reception sensitivity of the machine can be increased. Of course, the influence of fading on the radio propagation path can be reduced.

  FIG. 14 shows a block diagram of a third embodiment of a TMCC receiving circuit that demodulates two TMCC carriers of carrier numbers # 101 and # 349. In the figure, the same parts as those in FIG.

In the figure, the received ISDB-T signal (center frequency f _IF = 124/63 MHz) passes through a band filter (BPF) that passes a band including two TMCC carriers of carrier numbers # 101 and # 349. 102. The AD converter 102 samples the signal with a clock having a frequency of 124/63 MHz and supplies the sampled signal to the distributor 103 in the quadrature demodulation circuit 42.

  The quadrature demodulation circuit 42 operates with a clock having a frequency of 124/63 MHz. The multiplier 104 adds “1, 0, −1, 0” from the coefficient sequence generation circuit 105 to the signal from the distributor 103 as the clock. After being multiplied by the coefficient sequence repeated in step (3), the result is supplied to the down-sampling circuit 107 through the low-pass filter 106. The downsampling circuit 107 downsamples the supplied signal at 4: 1 to extract an in-phase component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  Note that the multiplier outputs the signal as it is when it is multiplied by “1”, outputs the signal with the sign inverted when it is multiplied by “−1”, and omits the calculation when it is multiplied by “0”. As a result, the circuit can be simplified as compared with the FFT operation.

  The multiplier 108 multiplies the signal from the distributor 103 by the coefficient sequence that repeats “0, 1, 0, −1” from the coefficient sequence generation circuit 109 with the above clock, and then passes through the low-pass filter 110 to the down-sample circuit 111. To supply. The down-sampling circuit 111 down-samples the supplied signal at 4: 1, extracts the quadrature component, and supplies it to the TMCC carrier reception circuit 44 through the complex multiplication circuit 43.

  The TMCC carrier reception circuit 44 operates with a clock of a frequency of 31/63 MHz. The in-phase component output from the quadrature demodulation circuit 42 is supplied to the multipliers 161 and 164, and the quadrature component is supplied to the multipliers 162 and 163.

  The multiplier 161 multiplies the in-phase component by “1, 0, −1, 0” from the coefficient sequence generation circuit 165 by the coefficient sequence repeated at the clock, and supplies the result to the average addition circuit 167. The average addition circuit 167 performs average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies it to the subsequent diversity combining circuit 152.

  The multiplier 162 multiplies the orthogonal component by “0, 1, 0, −1” from the coefficient sequence generation circuit 166 by the coefficient sequence repeated with the clock, and supplies the result to the average addition circuit 168. The average addition circuit 168 performs average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent diversity combining circuit 152.

  The multiplier 163 multiplies the orthogonal component by “1, 0, −1, 0” from the coefficient sequence generation circuit 165 by the coefficient sequence repeated with the clock, and supplies the result to the average addition circuit 169. The average addition circuit 169 performs average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent diversity combining circuit 152.

  The multiplier 164 multiplies the in-phase component by “0, 1, 0, −1” from the coefficient sequence generation circuit 166 by the coefficient sequence repeated with the clock, and then supplies the result to the average addition circuit 170. The average addition circuit 170 performs an average addition of signals corresponding to the number of samples of one effective symbol (496 points) and supplies the result to the subsequent diversity combining circuit 152.

  In this embodiment, it is possible to prevent the amplitude of the output of the diversity combining circuit 152 from fluctuating even if the clock of the frequency 31/63 MHz of the TMCC carrier receiving circuit 44 fluctuates.

  In FIG. 14, when the sampling frequency of the quadrature demodulation circuit 43 by AD conversion and digital signal processing is 124/63 MHz, the sine wave oscillation circuit 64 and the π / 2 phase shifter 65 in the quadrature demodulation circuit shown in FIG. Two coefficient sequence generation circuits can be replaced, and the circuit can be greatly reduced. Similarly, the sine wave oscillator and the π / 2 phase shifter in the TMCC carrier receiving circuit 44 can be replaced with two coefficient sequence generation circuits, and the circuit can be greatly reduced.

  In the above description, the coefficient sequence “0, 1, 0, −1” is associated with the coefficient sequence “1, 0, −1, 0”. May be made to correspond.

  In the above embodiment, the emergency warning broadcast activation flag is received by the TMCC dedicated receiver as an example. However, transmission for receiving AC (Auxiliary Channel) that transmits additional information related to transmission control of the modulated wave and the like. The present invention may be applied to a control signal receiver and is not limited to the above embodiment. Further, the present invention can be applied to obtaining the probability of normal reception of a total of 20 bits including the TMCC differential demodulation reference 1 bit, the synchronization signal 16 bits, and the segment format identification 3 bits, and evaluating the reception state from the probability.

  FIG. 15 is a block diagram showing an embodiment of a digital terrestrial television broadcast receiver to which the transmission control signal receiver of the present invention is applied. In FIG. 15, the antenna reception signal from the receiving antenna 20 is distributed by the distributor 22, one is supplied to the TMCC receiving circuit 24 as a transmission control signal receiver, and the other is the terrestrial digital television broadcast tuner 26. To be supplied.

  The video signal and audio signal output from the terrestrial digital television broadcast tuner 26 are input to the receiver 28. The terrestrial digital television broadcast tuner 26 is supplied with power from a power supply circuit 30 via a switch 32. The receiver 28 is supplied with power from the power supply circuit 30 via the switch 34. In the standby state, the power of the digital terrestrial television broadcast tuner 26 is turned off by the switch 32 and the power of the receiver 28 is turned off by the switch 34.

  The TMCC receiving circuit 24 as a transmission control signal receiver is supplied with power from the power supply circuit 30 via the switch 36. The TMCC receiving circuit 24 detects a TMCC signal of a terrestrial digital television broadcast wave at the time of power supply, generates TMCC synchronization establishment information and a reset pulse, and supplies the information to the power supply control circuit 38.

  The power control circuit 38 is constantly supplied with power from the power circuit 30 via the switch 36. The power supply control circuit 38 generates a control signal based on the TMCC synchronization establishment information and the reset pulse, and controls on / off of the switch 36 that supplies power to the TMCC receiving circuit 24.

  Further, when the TMCC receiving circuit 24 detects an emergency warning broadcast activation flag included in the TMCC signal of the terrestrial digital television broadcast wave, it generates a switch-on signal and turns on the switch 32 to turn on the terrestrial digital television broadcast tuner 26. Start. The terrestrial digital television broadcast tuner 26 is in a state where it can receive an emergency warning broadcast for the first time. When the terrestrial digital television broadcast tuner 26 receives the emergency warning broadcast activation flag, it generates a switch-on signal and supplies it to the switch 34. As a result, the switch 34 is turned on, and the receiver 28 is supplied with power from the power supply circuit 30 and is in an operating state. Note that the switch 34 may be closed (turned on) together with the switch 32 by the switch-on signal generated by the TMCC receiving circuit 24.

  FIG. 16 shows a block diagram of an embodiment of the TMCC receiving circuit 24 and the power supply control circuit 38. In the figure, the same parts as those in FIG.

  The control circuit 50 and the synchronization holding circuit 51 of the power control circuit 38 are always supplied with power from the power circuit 30. The synchronization holding circuit 51 is composed of, for example, a clock generator and a counter, counts the clock generated by the clock generator with the counter, generates a frame pulse every time the count value reaches a predetermined value, and resets the count value. This frame pulse is supplied to the control circuit 50.

  The counter is reset when a reset pulse generated by the TMCC synchronization detection circuit 48 in the TMCC reception circuit 24 detecting the TMCC synchronization signal is supplied. As a result, the synchronization holding circuit 51 can generate a self-held frame pulse.

  The control circuit 50 determines the two intermittent reception modes shown in FIG. 17 from the frame pulse from the synchronization holding circuit 51 and the TMCC synchronization establishment information from the TMCC synchronization detection circuit 48, and turns on the switch 36 in each intermittent reception mode. Control off / off.

  The switch-on signal output from the EWS detection circuit 49 is supplied to the switch 32. This switch-on signal turns on the switch 32 and activates the digital terrestrial television broadcast tuner 26.

  The terrestrial digital television broadcast tuner 26 includes an orthogonal demodulation unit 11, a synchronous reproduction unit 12, an FFT unit 13, a frame extraction unit 14, a TMCC decoding unit 15, a carrier demodulation unit 16, a demapping unit 17, and a TS reproduction unit illustrated in FIG. 18, in addition to the RS decoding unit 19, the audio processing unit and the video processing unit are included. For this reason, the power consumption of the terrestrial digital television broadcast tuner 26 is about several hundreds mW or more.

  On the other hand, since the TMCC dedicated receiver 24 demodulates only the TMCC carrier, the circuit scale is approximately the same as that of the synchronous reproduction unit 12 and the TMCC decoding unit 15 of the terrestrial digital television broadcast tuner 26, and the circuit configuration is simplified. The power consumption can be reduced to about several mW.

  Further, even within the TMCC receiving circuit 24, the power consumption of a high frequency circuit such as the frequency conversion circuit 40 for converting the frequency from the UHF band frequency to an intermediate frequency to which the digital signal processing technology can be applied is digital using the digital signal processing technology. Although larger than the demodulation circuit, in the present invention, there are two types of the intermittent reception mode outside the frame used when the TMCC signal cannot be received and the synchronization is not established, and the intermittent reception mode within the frame used when the synchronization is established where the TMCC signal can be received. By preparing an intermittent reception mode and appropriately switching the mode according to the reception state, the power consumption during standby of the transmission control signal receiver can be significantly reduced.

  In FIG. 17, the out-of-frame intermittent reception mode is determined when TMCC synchronization establishment information indicating that TMCC synchronization is not established is supplied. In this case, the ON duration of the switch 36 that supplies power to the TMCC receiving circuit 24 is at least one frame as shown in FIG.

  When the transmission mode of terrestrial digital television broadcasting is mode 3 and the guard interval ratio (GI ratio) is 1/8, one frame is 231.336 msec. In the out-of-frame intermittent reception mode, the power-on timing of the TMCC receiving circuit 24 is not limited, and the on / off interval is set to a predetermined value (for example, every 10 seconds).

  As described above, by setting the power supply time to the TMCC receiving circuit 24 when TMCC synchronization is not established to be one frame or longer, it is possible to prevent the TMCC signal from being missed. Further, standby power consumption can be reduced by increasing the on / off interval.

  The in-frame intermittent reception mode is determined when TMCC synchronization establishment information indicating that TMCC synchronization is established is supplied. In this case, the ON duration of the switch 36 that supplies power to the TMCC receiving circuit 24 is, for example, 30.618 msec (= 27/204 frames) as shown in FIG. 19, and the power is turned on from the beginning of the TMCC signal frame. Then, when a required bit, for example, an emergency warning broadcast activation flag is received, the power is shut off. At least one frame. In the intra-frame intermittent reception mode, the power-on timing of the TMCC receiving circuit 24 is set to the head of the frame, and the ON / OFF interval is set to N frames (N is a natural number).

  As described above, by setting the power supply to the TMCC receiving circuit 24 when TMCC synchronization is established to be 30.618 msec from the beginning of the frame, it is possible to prevent the TMCC signal from being missed. Further, standby power consumption can be reduced by increasing the on / off interval.

  The TMCC reception circuit 24 corresponds to the transmission control signal reception circuit described in the claims, the switch 36 corresponds to the switch circuit, the TMCC carrier reception circuit 44 corresponds to the transmission control signal carrier reception circuit, and the DBPSK delay detection circuit 46 , Diversity combining circuit 152 corresponds to a detection circuit.

20 receiving antenna 22 distributor 24 TMCC receiving circuit 26 digital terrestrial television broadcasting tuner 28 receiver 30 power supply circuit 32, 34, 36 switch 38 power supply control circuit 40 frequency conversion circuit 41 AD conversion circuit 42 orthogonal demodulation circuit 43 complex multiplication circuit 44 TMCC carrier reception circuit 45 adaptive phase control circuit 46, 155, 159 DBPSK delay detection circuit 47 determination circuit 48 TMCC synchronization detection circuit 50 control circuit 51 synchronization holding circuit 61, 103 distributor 62, 63, 73, 74, 82, 86, 91, 92, 104, 108, 122, 125, 131, 135, 141 to 144, 161 to 164 Multiplier 64 Sine wave oscillation circuit 65, 72, 76, 95, 146 π / 2 phase shifters 66, 67, 106 , 110 Low-pass filter 71, 84, 121, 154, 157 Calculator 75, 93, 145 Cosine wave oscillation circuit 77, 78, 96, 97, 124, 127, 134, 136, 147 to 150, 167 to 170 Average adder circuit 83, 87, 120 Delay circuit 94, 132 Selection circuit 105 , 109, 123, 126, 133, 137, 165, 166 Coefficient sequence generation circuit 107, 111 Down-sampling circuit 152 Diversity combining circuit 153, 158 Subtractor

Claims (3)

In a transmission control signal receiver that receives a transmission control signal carrier of digital terrestrial television broadcasting and demodulates a transmission control signal from the transmission control signal carrier,
Orthogonal demodulation means for orthogonally demodulating a received signal using a frequency signal set to the center frequency of a plurality of transmission control signal carriers;
Transmission control signal carrier receiving means for simultaneously receiving the plurality of transmission control signal carriers from the output signal of the orthogonal demodulation means;
Detecting means for performing diversity combining of the plurality of transmission control signal carriers received by the transmission control signal carrier receiving means, and performing detection;
The transmission control signal receiver includes an emergency warning broadcast activation flag.   The transmission control signal receiver according to claim 1, wherein the plurality of transmission control signal carriers include a plurality of TMCC carriers and / or AC carriers. A digital terrestrial television broadcast receiver having the transmission control signal receiver according to claim 1 or 2,
When the transmission control signal receiver detects an emergency warning broadcast activation flag in the transmission control signal, power is supplied to the tuner of the digital terrestrial television broadcast receiver based on the detection result. Television broadcast receiver.

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