JP2010183533A - Semiconductor integrated device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated device of low power supply voltage, including a signal input circuit capable of reliably receiving data from a semiconductor integrated device of high power supply voltage via an I2C bus interface. <P>SOLUTION: The semiconductor integrated device includes: a voltage conversion circuit 12 which is connected to a signal line 11 for exchanging a first signal S1 having an amplitude of a first voltage V1 or of a second voltage V2 higher than the first voltage V1, converts the first signal S1 into a second signal S2 having an amplitude of a third voltage V3 lower than the first voltage V1 and outputs the second signal S2; a comparator 13 in which the second signal S2 is input to a first input terminal 13a, a reference voltage Vref is input to a second input terminal 13b, the second signal S2 is compared with the reference voltage Vref and an output voltage Vout is output; and a reference voltage-generating circuit 14 for generating a first reference voltage Vref1 and a second reference voltage Vref2, selecting either the first reference voltage Vref1 or the second reference voltage Vref2 in accordance with the output voltage Vout, and outputting the selected reference voltage as the reference voltage Vref. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated device.

The I2C (Inter-Integrated Circuit) bus interface is widely used for mutual data transfer and control between a plurality of ICs (Integrated Circuits) as a two-wire simple bus interface.
The I2C bus interface is composed of a bi-directional two-wire bus composed of a serial data line and a serial clock line. As a signal standard, the maximum signal voltage is 5 V, the low level input voltage VIL, the high level input voltage VIH, the hysteresis voltage Vhys, and the like. Therefore, a Schmitt trigger circuit having hysteresis characteristics is used for a signal input circuit in an I / O (Input / Output) circuit.

In recent years, with the high integration of semiconductor devices, the power supply voltage of IC has become mainstream from 5V to 3.3V. In an IC with a power supply voltage of 3.3 V, the signal input circuit is composed of a voltage conversion circuit using an NMOS transistor and a Schmitt trigger circuit so that the existing power supply voltage can be connected to an IC with an I2C bus interface via an I2C bus interface. It had been.

However, the sum of the maximum value VILmax of the low level input voltage standard + the maximum value Vhysmax of the hysteresis voltage standard and the high level input voltage due to a decrease in the output voltage of the voltage conversion circuit due to an increase in the threshold voltage of the NMOS transistor, a fluctuation in the power supply voltage, etc. There is a problem that it is difficult to satisfy both standards of the minimum value VIHmin of the standard.
Therefore, an IC having a power supply voltage of 3.3 V having a signal input circuit that can reliably receive data from an IC having a power supply voltage of 5 V has been demanded.

On the other hand, a data transfer system that transfers data between devices having different logic amplitudes is known (see, for example, Patent Document 1).
The data transfer system disclosed in Patent Document 1 includes a 5V power supply device using a 5V pull-up resistor and a 3.3V power supply device using a 3.3V pull-up resistor. The voltage level is converted by using a parasitic diode of the FET.
However, the data transfer system disclosed in Patent Document 1 adjusts the timing of data transfer by an inverter having a time constant circuit of a resistor and a capacitor. No signal input circuit is disclosed.

Further, a method for suppressing characteristic fluctuations of the input circuit depending on the threshold voltage, temperature, and power supply voltage is known (see, for example, Patent Document 2).
The input circuit disclosed in Patent Document 2 compares an input signal with a reference voltage when the input signal transitions from a High level to a Low level, and outputs an inverted signal when the input signal reaches almost the same voltage level as the reference voltage. A differential input circuit for outputting and a hysteresis generating unit for generating arbitrary hysteresis are provided.
However, the input circuit disclosed in Patent Document 2 connects ICs having the same power supply voltage. When ICs having different power supply voltages are connected to each other, an IC having a power supply voltage of 3.3V has a breakdown voltage failure. May occur.

JP 2008-16941 A JP 2005-303859 A

The present invention provides a low power supply voltage semiconductor integrated device including a signal input circuit that can reliably receive data from a high power supply voltage semiconductor integrated device via an I2C bus interface.

In order to achieve the above object, a semiconductor integrated device of one embodiment of the present invention is connected to a signal line through which a first signal having a first voltage or an amplitude of a second voltage higher than the first voltage is exchanged,
A voltage conversion circuit that converts the first signal into a second signal having a third voltage amplitude lower than the first voltage and outputs the second signal; the second input is input to a first input terminal; A reference voltage is inputted, the second signal is compared with the reference voltage, a comparison result is output, a first reference voltage and a second reference voltage higher than the first reference voltage are generated, and the comparison result The first reference voltage or the second reference voltage is selected according to the reference voltage, and the selected first reference voltage or the second reference voltage is output to the second input terminal of the comparator as the reference voltage. And a generation circuit.

According to the present invention, a low power supply voltage semiconductor integrated device including a signal input circuit capable of reliably receiving data from a high power supply voltage semiconductor integrated device via an I2C bus interface can be obtained.

1 is a circuit diagram showing a signal input circuit of a semiconductor integrated device according to an embodiment of the present invention. 4 is a diagram for explaining input / output characteristics of a comparator used in a signal input circuit of a semiconductor integrated device according to an embodiment of the present invention. Sectional drawing which shows the voltage conversion element of the voltage conversion circuit used for the signal input circuit of the semiconductor integrated device which concerns on the Example of this invention. The circuit diagram which shows the comparator used for the signal input circuit of the semiconductor integrated device which concerns on the Example of this invention. 1 is a circuit diagram showing a reference voltage generation circuit used in a signal input circuit of a semiconductor integrated device according to an embodiment of the present invention. 1 is a block diagram in which a semiconductor integrated device according to an embodiment of the present invention is connected to a semiconductor integrated device with a high power supply voltage via an I2C bus interface. FIG. 4 is a diagram for explaining specifications in a signal input circuit of a semiconductor integrated device according to an embodiment of the present invention. The circuit diagram which shows the signal input circuit of the semiconductor integrated device of the comparative example which concerns on the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

A semiconductor integrated device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a signal input circuit of a semiconductor integrated device of this embodiment, and FIG. 2 is a diagram for explaining input / output characteristics of a comparator used in the signal input circuit of the semiconductor integrated device.
The present embodiment is an example of a signal input circuit of a semiconductor integrated device having an operating voltage of 3.3V connected to a semiconductor integrated device having an operating voltage of 5V through an I2C bus interface.

As shown in FIG. 1, the signal input circuit 10a of the semiconductor integrated device 10 of the present embodiment is a signal to which a first signal S1 having an amplitude of a first voltage V1 or a second voltage V2 higher than the first voltage V1 is exchanged. A voltage conversion circuit 12 connected to the line 11 for converting the first signal S1 into a second signal S2 having an amplitude of a third voltage V3 lower than the first voltage V1, and a second input to the first input terminal 13a.
The signal S2 is input, the reference voltage Vref is input to the second input terminal 13b, and the second signal S2
Is compared with the reference voltage Vref, and the comparator 13 outputs the output voltage Vout as a comparison result from the output terminal 13c.

Further, the semiconductor integrated device 10 includes the first reference voltage Vref1 and the second reference voltage Vref2.
And the first reference voltage Vref1 or the second reference voltage Vre according to the output voltage Vout.
a reference voltage generation circuit 14 that selects f2 and outputs the selected first reference voltage Vref1 or second reference voltage Vref2 as a reference voltage Vref to the second input terminal 13b of the comparator 13.

The first signal S1 is, for example, serial data SDA having a logic amplitude (difference between a logic high level and a low voltage) of 5 V, and the signal line 11 is a serial data line of an I2C bus interface.
The voltage conversion circuit 12 is an open drain N-channel insulated gate field effect transistor M1 (hereinafter simply referred to as MOS transistor M1), the drain is connected to the signal line 11, and the source is connected to the first input terminal 13a of the comparator 13. , The gate is the power supply voltage Vdd
1 (3.3 V), and the back gate is connected to the source.

Since the gate of the MOS transistor M1 is connected to the power supply voltage Vdd1, the MOS transistor M1 is turned on when the signal line 11 is at the high level, and the power supply voltage Vdd1 and the MOS transistor M1 are turned on.
The third voltage V3 = Vdd1-Vth1 equal to the difference from the threshold value Vth1, for example, 0.5V
The second signal S2 having an amplitude of is output.

Since the back gate of the MOS transistor M1 is connected to the source, the so-called back gate effect in which the threshold value Vth shifts due to fluctuations in the semiconductor substrate potential does not occur.
As a result, the voltage conversion circuit 12 outputs the second signal S2 having the constant amplitude of the third voltage V3 even when the amplitude of the first signal S1 is the first voltage V1 (3.3 V) or the second voltage V2 (5 V). It can output stably.

The comparator 13 compares the voltage level between the input voltage Vin (second signal S2) and the reference voltage Vref by current control by the current mirror circuit and the current mirror circuit.
And an analog comparator having a second MOS transistor and an output voltage V
When the input voltage Vin is lower than the reference voltage Vref, a low level signal is output as out, and when the input voltage Vin is higher than the reference voltage Vref, a high level signal is output.

The reference voltage generation circuit 14 has a series circuit of resistors, and divides the power supply voltage Vdd1 to generate a first voltage.
A voltage dividing circuit for generating a reference voltage Vref1 and a second reference voltage Vref2, and an output voltage Vou
When t is low level, the second reference voltage Vref2 is selected and the output voltage Vout is High.
and a selection circuit that selects the first reference voltage Vref1 when the level is h.

FIG. 2 is a diagram for explaining the input / output characteristics of the comparator 13. As shown in FIG.
In the comparator 13, the output voltage Vout is at a low level as an initial state, and the second reference voltage Vref2 is selected as the reference voltage Vref.
This state is maintained when the input voltage Vin is smaller than the second reference voltage Vref2, and when the input voltage Vin becomes a higher level than the second reference voltage Vref2, the output voltage Vo
ut becomes High level, and the first reference voltage Vref1 is selected as the reference voltage Vref.
This state is maintained when the input voltage Vin is higher than the first reference voltage Vref1, and when the input voltage Vin becomes a low level lower than the first reference voltage Vref1, the output voltage Vou.
t becomes the Low level, and the second reference voltage Vref2 is selected as the reference voltage Vref.

As a result, the comparator 13 and the reference voltage generation circuit 14 are connected to the hysteresis Vhys.
= Vref2-Vref1 functions as an analog Schmitt trigger circuit 15.

Next, regarding the voltage conversion circuit 12, the comparator 13, and the reference voltage generation circuit 14,
This will be specifically described with reference to FIGS.
FIG. 3 is a cross-sectional view showing a MOS transistor M1 which is a voltage conversion element of the voltage conversion circuit 12. As shown in FIG. 3, the MOS transistor M1 has an N-type well region 21 formed in a P-type silicon substrate 20 and a P-type well region 22 formed in the N-type well region 21. A gate G, a source S, a drain D, and a back gate B are formed in the well region 22, respectively, and the P-type well region 22 is connected to the source S.

Since the P-type well region 22 of the MOS transistor M 1 is electrically insulated from the P-type silicon substrate 20 by the N-type well region 21, the potential of the P-type well region 22 varies with the potential of the P-type silicon substrate 20. Not affected.
Since the P-type well region 22 which is the back gate B is connected to the source S of the MOS transistor M1, a decrease in drain current due to the back gate effect is avoided.
As a result, the voltage drop due to the back gate effect is canceled, and no voltage loss due to the back gate effect occurs in the third voltage V3.

FIG. 4 is a circuit diagram showing the comparator 13. As shown in FIG. 4, the comparator 13 is a so-called current mirror including a pair of N-channel MOS transistor N1 and N-channel MOS transistor N2, and a current mirror circuit having P-channel MOS transistor P1 and P-channel MOS transistor P2. Type differential amplifier.
In the comparator 13, the gate of the MOS transistor N1 is an inverting input terminal (second input terminal) 13b, the gate of the MOS transistor N2 is a non-inverting input terminal (first input terminal) 13a, the drain of the MOS transistor P and the MOS A connection node with the drain of the transistor N1 is an output terminal 13c.
When the input voltage Vin becomes higher than the reference voltage Vref, the comparator 13
A high level output voltage Vout is output, and when the input voltage Vin becomes lower than the reference voltage Vref, the low level output voltage Vout is output.

FIG. 5 is a circuit diagram showing the reference voltage generation circuit 14. As shown in FIG. 5A, the voltage dividing circuit 31 in the reference voltage generating circuit 14 is a series circuit of resistors R1, R2, and R3 connected between the power supply voltage Vdd1 and the reference potential GND.
The voltage dividing circuit 31 divides the power supply voltage Vdd1 by resistors R1, R2, and R3, and resistors R1, R2
The first reference voltage Vref1 is output from the voltage dividing point N1 that is the connection node of the resistors R2, R3, and the second reference voltage Vref2 is output from the voltage dividing point N2 that is the connection node of the resistors R2 and R3.
The selection circuit 32 in the reference voltage generation circuit 14 is a double throw switch using a MOS transistor.

As shown in FIG. 5B, the double throw switch using the MOS transistor has, for example, transmission gates 33 and 34 in which an N channel MOS transistor and a P channel MOS transistor are connected in parallel, and an inverter 25. .
When the output voltage Vout is at a low level, the transmission gate 33 is turned on, the transmission gate 34 is turned off, and the contact a and contact c of the double throw switch are connected.
The second reference voltage Vref2 is selected.
When the output voltage Vout is at a high level, the transmission gate 33 is turned off.
The transmission gate 34 is turned on, the contact a and the contact b of the double throw switch are connected, and the first reference voltage Vref1 is selected.

Since the MOS transistor included in the semiconductor integrated device 10 described above only has to set the gate breakdown voltage or the like with respect to the power supply voltage 3.3V, the power supply voltage can be made lower than that of the semiconductor integrated device with 5V.

Next, between the semiconductor integrated device 10 of this embodiment and the semiconductor integrated device having a power supply voltage of 5 V, I
A case of connecting with a 2C bus interface will be described.
FIG. 6 is a block diagram in which the semiconductor integrated device 10 is connected to a semiconductor integrated device having a power supply voltage Vdd2 of 5 V via an I2C bus interface.
As shown in FIG. 6, the clock signal input circuit of the semiconductor integrated device 10 is connected to the serial clock signal line 41, and the serial data signal input circuit is connected to the serial data signal line 42. The same applies to the semiconductor integrated device 40 whose power supply voltage Vdd2 is 5V.

Serial clock signal line 41 and serial data signal line 4 of the I2C bus interface
2 is pulled up to the power supply voltage Vdd2 of 5V by the resistors R4 and R5, respectively, so that the first signal S1 having the amplitude of the second voltage V2 (5V) is exchanged.

FIG. 7 is a diagram for explaining the specifications in the signal input circuit of the semiconductor integrated device. As shown in FIG. 7, the standard values of the low level input voltage VIL, high level input voltage VIH, and hysteresis Vhys of the I2C bus interface are based on the power supply voltage Vdd.
The maximum value of the Low level input voltage is VILmax = 0.3 Vdd, and the minimum value of the High level input voltage is VIHmin = 0.7 Vdd. The minimum value of hysteresis is the power supply voltage Vd
Vhysmin = 0.05 Vdd when Vdd> 2V.

From now on, the semiconductor integrated device 10 is connected to the power supply voltage of 5 V via the I2C bus interface.
Assuming that the variation of the power supply voltage is ± 0.3V,
L = 1.41-1.59V, VIH = 3.29-3.71V, Vhys = 0.235-5
. 265V.
Further, the semiconductor integrated device 10 is connected to the power supply voltage 3.3V through the I2C bus interface.
Assuming that the variation of the power supply voltage is ± 0.3V,
L = 0.9 to 1.08V, VIH = 2.1 to 2.52V, Vhys = 0.15 to 0.18
V.

Therefore, in order to connect the semiconductor integrated device 10 to both the semiconductor integrated device having the power supply voltage 5V and the semiconductor integrated device having the power supply voltage 3.3V through the I2C bus interface, both ranges are satisfied. A maximum value of 1.59 V is selected as VIL, a minimum value of 2.1 V is selected as VIH, and a maximum value of 0.265 V is selected as Vhys.
Accordingly, it is appropriate that the first reference voltage Vref1 is set to VILmax = 1.59V, and the second reference voltage Vref2 is set to VILmax + Vhysmax = 1.855V lower than VIHmin.

FIG. 8 is a diagram showing a signal input circuit of a semiconductor integrated device of a comparative example. Here, the comparative example is a semiconductor integrated device having an N channel MOS transistor in a voltage conversion circuit and a signal input circuit having a digital Schmitt trigger circuit.

As shown in FIG. 8, the signal input circuit of the semiconductor integrated device 50 of the comparative example includes a voltage conversion circuit 51 having an N-channel MOS transistor M2 having a drain connected to the signal line 11 and a gate connected to the power supply voltage Vdd1. The digital Schmitt trigger circuit 52 has an input terminal 52a connected to the source of the MOS transistor M2.

The Schmitt trigger circuit 52 includes an N channel MOS transistor N3 and a P channel M
It has a hysteresis characteristic corresponding to the threshold value of the OS transistor P3.
The Schmitt trigger circuit 52 has a power supply voltage Vdd1 via a power supply voltage matching circuit 53 having an N-channel MOS transistor M3 whose drain and gate are connected to the power supply voltage Vdd1.
It is connected to the. The power supply voltage matching circuit 53 is provided to match the power supply voltage of the Schmitt trigger circuit 52 with the input voltage Vin, that is, the voltage V4.

The voltage conversion circuit 51 includes a power supply voltage Vdd1 and a threshold value Vth2 of the MOS transistor M2.
The second signal S2 having the amplitude of the voltage V4 = Vdd1−Vth2 equal to the difference between the second signal S2 and the second signal S2.
The power supply voltage matching circuit 53 includes a power supply voltage Vdd1 and a threshold value Vth of the MOS transistor M3.
A voltage V5 = Vdd1-Vth3 equal to the difference from 3 is output.

In the signal input circuit of the semiconductor integrated device 50 of the comparative example, the first reason is as follows.
There arises a problem that the first signal S1 having any amplitude of the power supply voltage V1 (3.3 V) and the second voltage V2 (5 V) cannot be received.

1) Since the back gate of the MOS transistor M2 of the voltage conversion circuit 51 is not connected to the source, the threshold value Vth2 increases under the influence of the fluctuation of the substrate potential, and the level of the voltage V4 decreases.
For example, when the power supply voltage Vdd1 is decreased from 3.3V to the standard minimum value Vdd1min = 3.0V and the threshold value of the MOS transistor M2 is increased from 0.5V to 1.0V, the input voltage Vin is 2.0V. However, since the margin is insufficient with respect to the second reference voltage Vref2 = 1.855V of the Schmitt trigger circuit 52, the second voltage V2 (5V) H
There is a possibility that the high level cannot be detected.

2) The power supply voltage V5 of the Schmitt trigger circuit 52 decreases to about 2V due to an increase in the threshold value Vth3 due to the back gate effect of the MOS transistor M3 of the power supply voltage matching circuit 53, a voltage drop due to resistance, and the like.
As a result, in the Schmitt trigger circuit 52, the first reference voltage Vref1 = 1.59V.
Therefore, it is difficult to obtain the second reference voltage Vref2 = 1.855V only by the logic circuit.

On the other hand, in the semiconductor integrated device 10 of the present embodiment, the first power supply voltage V1 is as follows.
The first signal S1 having any amplitude of (3.3V) and the second voltage V2 (5V) can be received without any problem.
1) Since the back gate of the MOS transistor M1 of the voltage conversion circuit 12 is connected to the source, the threshold voltage Vth1 is not affected by the fluctuation of the potential of the substrate, and the third voltage V3
The level of is stable.
2) Since the reference voltage generation circuit 14 is a resistance voltage dividing circuit, the first reference voltage Vref1 = 1 can be easily obtained.
. 59V and the second reference voltage Vref2 = 1.855V can be obtained.

As described above, in the signal input circuit 10a of the semiconductor integrated device 10 of this embodiment,
The voltage conversion circuit 12 includes a MOS transistor M1 having a bag gate connected to the source, an analog comparator 13, and a reference voltage generation circuit 14 that divides the power supply voltage Vdd1 and outputs a reference voltage Vref.

As a result, in the voltage conversion circuit 12, since the MOS transistor M1 is not affected by the substrate bias effect and has the constant threshold value Vth1, the amplitude of the first signal S1 is either the first voltage V1 or the second voltage V2. However, it is possible to output the second signal S2 having the stable third voltage V3.
The Schmitt trigger circuit 15 is easily connected to the first reference voltage Vre by the reference voltage generation circuit 14.
It is possible to obtain f1 = 1.59V and the second reference voltage Vref2 = 1.855V.

Therefore, a low power supply voltage semiconductor integrated device having a signal input circuit capable of reliably receiving data from the high power supply voltage semiconductor integrated device via the I2C bus interface can be obtained.

Although the case where the first signal S1 is the serial data SDA and the signal line 11 is the serial data line has been described here, the same applies to the case where the first signal S1 is the serial clock SCL and the signal line 11 is the serial clock line.
Although the case where the first signal S1 has the amplitude of the second voltage V2 (5V) has been described, the same applies to the case where the first signal S1 has the amplitude of the first voltage V1 (3.3V).

10, 40, 50 Semiconductor integrated device 10a Signal input circuit 11 Signal line 12, 51 Voltage conversion circuit 13 Comparator 14 Reference voltage generation circuit 15, 52 Schmitt trigger circuit 20 P-type silicon substrate 21 N-type well region 22 P-type well region 31 Voltage divider circuit 32 Selection circuit 33, 34 Transmission gate 35 Inverter 41 Serial clock line 42 Serial data line 53 Power supply voltage matching circuit S1 First signal S2 Second signals V1, V2, V3 First, second, third voltage M1, M2, M3, N1, N2, N3 N-channel MOS transistors P1, P2, P3 P-channel MOS transistors R1, R2, R3, R4, R5 Resistors N1, N2 Voltage dividing point

Claims (5)

A second signal having a third voltage amplitude lower than the first voltage is connected to a signal line through which a first signal having a first voltage or a second signal amplitude higher than the first voltage is exchanged.
A voltage conversion circuit for converting the signal into an output, and
The second signal is input to a first input terminal, a reference voltage is input to a second input terminal, and the second input terminal
A comparator that compares a signal with the reference voltage and outputs a comparison result;
Generating a first reference voltage and a second reference voltage higher than the first reference voltage, selecting the first reference voltage or the second reference voltage according to the comparison result, and selecting the selected first reference voltage or A reference voltage generation circuit that outputs the second reference voltage as the reference voltage to the second input terminal of the comparator;
A semiconductor integrated device comprising: The voltage conversion circuit is an N-channel insulated gate field effect transistor having a drain connected to the signal line, a source connected to the first input terminal of the comparator, and a gate connected to a power supply voltage. 2. The semiconductor integrated device according to claim 1, wherein the voltage is equal to a difference between the power supply voltage and a threshold value of the N-channel insulated gate field effect transistor. The N channel insulated gate field effect transistor is an insulated gate field effect transistor having a triple well structure in which an N type well region is formed in a P type substrate, and a P type well region is formed in the N type well region, 3. The semiconductor integrated device according to claim 2, wherein a P-type well region is connected to a source of the N-channel insulated gate field effect transistor. The comparator includes a current mirror circuit and first and second transistors that compare voltage levels of the second signal and the reference voltage by current control by the current mirror circuit;
2. A low level signal is output when the second signal is lower than the reference voltage as a comparison result, and a high level signal is output when the second signal is higher than the reference voltage. The semiconductor integrated device described in 1. The reference voltage generating circuit is
A voltage dividing circuit having a series circuit of resistors and dividing the power supply voltage to generate the first reference voltage and the second reference voltage;
The second reference voltage is selected when the comparison result is at a low level, and the comparison result is High
a selection circuit for selecting the first reference voltage when the level is h;
The semiconductor integrated device according to claim 1, comprising:

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