JP2010182956A - Method of manufacturing reference voltage generation circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve temperature characteristics of a reference voltage without increasing the area of a reference voltage generation circuit device formed by a depletion type MOS transistor and an enhance type MOS transistor. <P>SOLUTION: The concentration profile of the depletion type MOS transistor is controlled so that impurity concentration at the surface side of the substrate of a first-conductivity-type channel region is small and impurity concentration of the first-conductivity-type channel region near a PN junction to be formed becomes large at the first-conductivity-type channel region and the second-conductivity-type substrate region or a well region, thus improving temperature characteristics of a reference voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a reference voltage generation circuit device using a depletion type MOS transistor and an enhancement type MOS transistor.

  In recent years, the demand for ICs having good temperature characteristics has increased, and in order to improve the temperature characteristics of ICs, it is required that the reference voltage in the IC does not vary with temperature.

  Various circuits have been devised for the reference voltage generation circuit depending on the IC process and layout. One of the simple and commonly used circuits is a reference voltage that combines a depletion type MOS transistor and an enhancement type MOS transistor. Circuit.

  In the reference voltage circuit using the depletion type MOS transistor and the enhancement type MOS transistor, many ideas for improving the temperature characteristics by devising the circuit are disclosed as exemplified in the following patent document. Yes.

Japanese Patent Laid-Open No. 5-289760 JP-A-11-134051

  However, in the method as described above, the circuit structure becomes complicated by devising the circuit itself, and the area necessary for the reference voltage circuit increases. At present, the cost reduction of ICs has progressed, and the reduction of ICs has become a major issue, and it can be a major drawback that the ratio of the reference voltage circuit to the IC area is large.

  Therefore, the present invention aims to improve the temperature characteristics without increasing the area of the reference voltage circuit by applying a device ingenuity instead of an ingenuity on the circuit.

In order to solve the above problems, the present invention uses the following means.
(1) In a reference voltage generation circuit configured using an enhancement type MOS transistor and a depletion type MOS transistor formed on a first conductivity type semiconductor silicon substrate, a concentration profile is set to improve the temperature characteristics of the reference voltage. A method for manufacturing a controlled depletion type MOS transistor, wherein a depletion type MOS transistor is formed on the silicon substrate with a low concentration of about 1.0 to 2.0 × 10 ¹⁶ cm ^{−3 of} the second conductivity type. forming a well region, LOCOS method forming a (Loc al O xidation of S ilicon ) by a thickness of about 100~500nm isolation insulating film by thermal oxidation of the first conductivity type in the lower gate insulating film to form the channel region, 1.0 to 2.0 × 10 ¹ comparable to the second conductivity type well region by ion implantation to a concentration of approximately cm ^-3, a step of applying a low dose implantation, and forming a gate insulating film having a thickness of about about 5~30nm by thermal oxidation, of the order of 200~300nm on the gate insulating film multi A step of depositing crystalline silicon, a step of etching polycrystalline silicon to form a gate electrode, a step of doping impurities in regions serving as the source and drain of a MOS transistor using the gate electrode and the field insulating film as a mask, and silicon A method of manufacturing a reference voltage generating circuit device including a step of forming a contact hole on a substrate, a step of forming a metal wiring in the contact hole, and a step of forming a protective film is provided.
(2) The step of forming the channel region of the first conductivity type is a reference voltage generating circuit comprising a step of implanting impurities with high energy so that a junction can be formed at a portion of about 150 to 200 nm from the substrate surface by ion implantation. A method for manufacturing the apparatus was adopted.
(3) The step of forming the first conductivity type channel region is a method for manufacturing a reference voltage generating circuit device including a step of implanting a first conductivity type impurity having a large diffusion coefficient by ion implantation.
(4) The step of forming the first conductivity type channel region includes a step of implanting the first conductivity type impurity by an ion implantation method and a step of thermally diffusing the first conductivity type impurity. It was set as the manufacturing method of this.
(5) In the step of forming the first conductivity type channel region, the first conductivity type impurity is implanted with a low dose and high energy by an ion implantation method, and about 1.0 to 10.0 × 10 ¹⁵ cm ^−3. A reference voltage generation circuit device manufacturing method comprising a first step of forming a low-concentration second conductivity type well region and a second step of implanting a first conductivity type impurity.
(6) The step of forming the first conductivity type channel region includes a first step of implanting the first conductivity type impurity by ion implantation and a second step of implanting the second conductivity type impurity in the vicinity of the substrate surface. The method of manufacturing a reference voltage generating circuit device comprising the steps described above was adopted.

  According to the present invention described above, the temperature characteristics of the reference voltage can be improved without increasing the area of the IC, and the temperature characteristics of the IC can be improved.

Sectional view of a depletion type MOS transistor, which is the main part of the present invention, and a concentration profile of a channel region from the substrate surface to the substrate back surface direction The simplest ED type reference voltage generation circuit using depletion type MOS transistor and enhancement type MOS transistor The figure which shows the temperature characteristic of a reference voltage. Sectional drawing which showed the manufacturing method of the depletion type MOS transistor in Example 1 of this invention, and the figure which shows the density | concentration profile of the channel area | region along the substrate back surface direction from the substrate surface. Sectional drawing which showed the manufacturing method of the depletion type MOS transistor in Example 1 of this invention, and the figure which shows the density | concentration profile of the channel area | region along the substrate back surface direction from the substrate surface. Sectional drawing which showed the manufacturing method of the N type channel area | region of a depletion type MOS transistor in Example 2 of this invention, and the figure which shows the density | concentration profile of the channel area | region along the substrate back surface direction from the substrate surface. Sectional drawing which showed the manufacturing method of the N type channel area | region of a depletion type MOS transistor in Example 3 of this invention, and the figure which shows the density | concentration profile of the channel area | region along the substrate back surface direction from the substrate surface.

  The reference voltage generation circuit proposed in the present invention is based on a reference voltage generation circuit using a depletion type MOS transistor and an enhancement type MOS transistor, and improves the temperature characteristics of the reference voltage by controlling the concentration profile of the depletion type MOS transistor. It is something to try. The principle and examples are shown below.

  FIG. 1 shows a cross-sectional structure of a depletion type MOS transistor according to the present invention and a concentration profile of a channel region extending from the substrate surface to the substrate back surface direction. In FIG. 1, reference numeral 101 denotes a semiconductor silicon substrate. A well region 102 which is a low-concentration second conductivity type impurity region is formed in the silicon substrate, and a depletion type MOS transistor is formed in the well region. This MOS transistor is electrically insulated from the surroundings by a field insulating film 103, and a gate electrode 105 is formed through a gate insulating film 104. The channel region 106 under the gate electrode is a low-concentration first conductivity type impurity region and is in contact with the high-concentration first conductivity type source region 107 and the high-concentration first conductivity type drain region 108. On the right side of the cross-sectional view of the depletion type MOS transistor, the concentration profile of the channel region along the substrate back surface direction is shown. The solid line in the figure shows the density profile in the present invention, and the dotted line shows the conventional density profile. The concentration profile of the depletion type MOS transistor according to the present invention is such that the impurity concentration of the first conductivity type channel region on the substrate surface side is lower than the conventional concentration profile, and the first conductivity type channel region and the second conductivity type substrate region or well. The impurity concentration of the first conductivity type channel region near the junction of the regions is high.

  Next, the principle of the present invention will be described using the simplest ED type reference voltage generation circuit in a reference voltage generation circuit using a depletion type MOS transistor and an enhancement type MOS transistor.

  FIG. 2 shows a circuit diagram of a general ED type reference voltage generating circuit. The operating principle of the ED type reference voltage generating circuit is as follows. First, a constant current independent of the input voltage is generated by a depletion type MOS transistor in which a gate electrode is connected to a source electrode. Next, the constant current is passed through an enhancement type transistor in which saturation is connected, whereby the potential of the node indicated by the black circle in FIG. 2 rises, and finally the node potential indicated by the black circle is a constant voltage that does not depend on the input voltage. This is how it becomes.

  Here, a theoretical reference voltage equation is derived.

  First, assuming that the gate voltage of the depletion type MOS transistor is VGD, the threshold voltage is VTD, and the K value is KD, the constant current ID generated in the depletion type MOS transistor is expressed by the following equation.

Now, the gate electrode of the depletion type MOS transistor is connected to the source electrode, and VGD = 0V.

It becomes.

  Next, assuming that the gate voltage of the enhanced MOS transistor is VGE, the threshold voltage is VTE, and the K value is KE, the current IE flowing through the enhanced MOS transistor is given by the following equation.

Here, since the same current flows in the depletion type MOS transistor and the enhancement type MOS transistor, the formulas 2 and 3 become equal,

And when deformed

It becomes. Here, the enhancement type MOS transistor is saturated and the gate voltage and the drain voltage are equal to the reference voltage. Therefore, when the reference voltage is Vref,

Given in.

  FIG. 3 shows the temperature characteristics of the reference voltage by the ED type reference voltage generation circuit. Normally, the temperature characteristics of the reference voltage are generally inclined with respect to the temperature as indicated by a dotted line 301 in FIG. The reference voltage varies with temperature due to the overall slope and curvature with respect to temperature. In the temperature characteristics of this reference voltage, as shown by the broken line 302 in FIG. 3, the overall slope is adjusted by adjusting KD and KE, that is, by adjusting the L length and W length of the depletion type or enhancement type MOS transistor. It is possible to flatten the overall inclination. However, the curvature with respect to the temperature still remains as it is, and the reference voltage changes as the temperature changes. Therefore, the present invention shows a method for reducing the curve of the reference voltage with respect to the temperature so as to obtain an ideal temperature characteristic as indicated by a solid line 303 in FIG.

  In the above-described theoretical formula 6 of the reference voltage, the temperature characteristics of the reference voltage are VTE, VTD, KD and KE, that is, the temperature characteristics of the mobility of the depletion type MOS transistor and the enhancement type MOS transistor. Here, when KD and KE that make the overall slope of the reference voltage flat, that is, when the L length and W length of the MOS transistor are adjusted, the temperature characteristic of the K value appears so notably with respect to the reference voltage. Not come. Therefore, the temperature characteristics of VTE and VTD are curved with respect to temperature, but the effect of the temperature characteristics of VTD is greater when compared. This is because, in the case of a depletion type MOS transistor, a depletion layer generated by a PN junction formed by a first conductivity type channel region and a second conductivity type substrate region or well region, which does not exist in an enhancement type MOS transistor, affects the temperature. Because it receives. Therefore, if the temperature change of the threshold voltage of the depletion type MOS transistor is reduced, the temperature characteristic of the reference voltage is improved.

  Considering the threshold voltage in a depletion type MOS transistor, a depletion layer generated by a PN junction formed by a first conductivity type channel region and a second conductivity type substrate region or well region, and a gate voltage from the substrate surface side Due to the depletion layer, a part of the channel region of the first conductivity type is crushed by the depletion layer, and the gate voltage when it becomes electrically non-conductive becomes the threshold voltage. Therefore, in order to eliminate the temperature change of the threshold voltage of the depletion type MOS transistor, the temperature of the depletion layer generated by the PN junction formed by the first conductivity type channel region and the second conductivity type substrate region or well region is not changed as much as possible. In addition, even if the depletion layer formed by the PN junction changes in temperature, if the depletion layer from the substrate surface side due to the gate voltage extends with a small gate voltage, the threshold voltage does not change so much with temperature.

  Therefore, in order to improve the temperature characteristics of the threshold voltage of the depletion type MOS transistor, first, a PN junction formed by the first conductivity type channel region and the second conductivity type substrate region or well region is used. In order to suppress the temperature change of the generated depletion layer, it is preferable that the concentration of the deep portion of the first conductivity type channel region is high and the concentration of the substrate region or well region of the second conductivity type is low.

  Second, in order for the depletion layer from the substrate surface side due to the gate voltage to be easily extended with a small gate voltage, the concentration of the first conductivity type channel region on the substrate surface side should be low.

  FIG. 1 shows an ideal density profile based on the above two points.

  If a depletion type MOS transistor having the above concentration profile is manufactured, the temperature characteristic of the threshold voltage of the depletion type MOS transistor can be reduced, and the temperature characteristic of the reference voltage can be improved.

  Hereinafter, a method for manufacturing a depletion type MOS transistor having the above profile will be described with reference to the drawings, taking an N type MOS transistor as an example.

FIG. 4A is a diagram in which a P-type well region 102 of about 1.0 to 2.0 × 10 ¹⁶ cm ⁻³ is formed in a P-type silicon substrate 101 of about 5.0 × 10 ¹⁵ cm ⁻³ . There, FIG. 4 (b) is a diagram obtained by forming a field insulating film 103 having a thickness of about about 100~500nm using LOCOS (Loc al O xidation of S ilICon) method.

FIG. 4C is a diagram in which a low concentration N-type channel region is formed by ion implantation. On the substrate surface side of the low concentration N-type channel region, an N-type impurity such as arsenic is thinner than the conventional one by ion implantation, and the concentration is approximately the same as the concentration of the P-type well region, that is, 1.0 to 2.0 × 10. Doping is performed to be about ¹² cm ⁻³ . Here, there is a concern that the threshold voltage of the depletion type MOS transistor becomes shallow by reducing the impurity concentration of the implantation. However, when the threshold voltage is desired to be increased, the implantation energy is set to about 100 keV, which is higher than that of the prior art. It is preferable that the junction be formed at a depth of about 200 nm. Here, arsenic was used as the ion species of the N-type impurity. However, by using an impurity having a diffusion coefficient larger than that of arsenic, such as phosphorus, the concentration of the substrate surface of the N-type channel region can be made low and deep. Good. Further, after the formation of the N-type channel region, a thermal diffusion process may be performed to make the concentration of the substrate surface of the N-type channel region low and deep.

  5A is a diagram in which a silicon oxide film having a thickness of about 5 to 30 nm is formed as the gate insulating film 104, and FIG. 5B is a diagram in which a polycrystalline silicon layer 105 serving as a gate electrode is formed to a thickness of about 200 to 200 nm. It is the figure which deposited 300 nm and etched.

FIG. 5C is a diagram in which a high concentration N-type impurity such as arsenic is ion-implanted using the formed gate electrode 105 and field insulating film 103 as a mask to form a source region 107 and a drain region 108. The concentration of the source and drain regions is generally about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . Thereafter, an interlayer insulating film (not shown) is deposited, and the source region 107 and the drain region 108 are electrically connected to the gate electrode 105.

FIG. 6 shows a second embodiment of the present invention. As another method for forming the N-type channel region, in order to increase the concentration of the N-type channel region near the junction with the P-type substrate region or well region, FIG. Arsenic is ion-implanted, and a profile and a profile are shown in which a P-type well region 109 having a low concentration of about 1.0 to 10.0 × 10 ¹⁵ cm ⁻³ is produced. FIG. 6B is a diagram in which an N-type impurity such as arsenic is doped at a higher dose and lower energy than the first time by the second ion implantation. By using this method, a profile having a deep concentration in the deep portion of the N-type channel region is formed.

FIG. 7 shows a third embodiment of the present invention. As another method of forming the N-type channel region, FIG. 7A is a diagram in which the N-type channel region is doped with an N-type impurity such as arsenic by an ion implantation method. FIG. 7B is a diagram in which a P-type impurity such as BF ₂ is implanted in the vicinity of the substrate surface. By using this method, a profile is formed in which the concentration in the vicinity of the substrate surface of the N-type channel region is low and the concentration in the deep portion is high.

  The reference voltage generating circuit device according to the present invention can be used for a semiconductor integrated circuit using a reference voltage or a constant voltage.

101 Silicon substrate 102 Well region 103 Field insulating film 104 Gate insulating film 105 Polycrystalline silicon 106 Low concentration N-type channel region 107 High concentration N-type source region 108 High concentration N-type drain region 109 Low concentration P-type well region 301 Reference voltage Temperature characteristics 302 Temperature characteristics of reference voltage adjusted KE and KD 303 Temperature characteristics of ideal reference voltage

Claims (6)

In a reference voltage generation circuit configured using an enhancement type MOS transistor and a depletion type MOS transistor formed on a semiconductor silicon substrate of the first conductivity type, a reference in which a concentration profile is controlled in order to improve temperature characteristics of the reference voltage A method for manufacturing a voltage generating circuit device, comprising:
Forming a second conductivity type low concentration well region of about 1.0 to 2.0 × 10 ¹⁶ cm ⁻³ on the surface of the semiconductor silicon substrate;
Forming an element isolation insulating film by thermal oxidation with a thickness of about 100~500nm by LOCOS method (Loc al O xidation of S ilicon ),
In order to form a first conductivity type channel region under the gate insulating film, a concentration of about 1.0 to 2.0 × 10 ¹⁶ cm ^{−3, which is} about the same as that of the second conductivity type well region, is obtained by ion implantation. A step of performing low-dose ion implantation,
Forming a gate insulating film having a thickness of about 5 to 30 nm by thermal oxidation;
Depositing polycrystalline silicon of about 200 to 300 nm on the gate insulating film;
Etching the polycrystalline silicon to form a gate electrode;
Doping an impurity into regions serving as a source and a drain of a MOS transistor using the gate electrode and the field insulating film as a mask;
Forming a contact hole on the silicon substrate;
Forming a metal wiring in the contact hole;
Forming a protective film;
A method of manufacturing a reference voltage generating circuit device comprising:   2. The step of forming a channel region of the first conductivity type comprises a step of ion-implanting impurities with high energy so that a PN junction can be formed at a portion of about 150 to 200 nm from the substrate surface by an ion implantation method. Manufacturing method of the reference voltage generating circuit device.   3. The reference voltage generating circuit device according to claim 1, wherein the step of forming the first conductivity type channel region comprises a step of ion implanting a first conductivity type impurity having a large diffusion coefficient by an ion implantation method. Production method. Forming the channel region of the first conductivity type,
A step of ion-implanting a first conductivity type impurity by an ion implantation method;
Thermally diffusing impurities of the first conductivity type;
3. A method of manufacturing a reference voltage generating circuit device according to claim 1, comprising: Forming the channel region of the first conductivity type,
A first conductivity type impurity is ion-implanted with a low dose and high energy by an ion implantation method to form a second conductivity type well region having a low concentration of about 1.0 to 10.0 × 10 ¹⁵ cm ⁻³ . One process,
A second step of ion-implanting impurities of the first conductivity type at a lower energy than the dose in the first step;
The method for manufacturing a reference voltage generating circuit device according to claim 1, comprising: Forming the channel region of the first conductivity type,
A first step of ion-implanting a first conductivity type impurity by an ion implantation method;
A second step of ion-implanting a second conductivity type impurity in the vicinity of the substrate surface;
The method of manufacturing a reference voltage generating circuit device according to claim 1, comprising:

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