JP2010176537A - Semiconductor integrated circuit device, debugging device and debugging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, a debugging device and a debugging system, for performing high-speed real time trace. <P>SOLUTION: In the semiconductor integrated circuit device 1, an input signal separation part 11 separates signals input by the half cycle unit of clock signals CK through a parallel input I/F 120 into normal operation input signals a1 to be input to a processor 110 and a debugging control signals a2 to be input to a trace control part 140, and an output switching part 12 switches normal operation output signals c1 output from the processor 110 and trace information c2 output from the trace control part 140 by a half cycle of the clock signals CK and outputs them through a parallel output I/F 130. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, a debugging device, and a debugging system.

  In a semiconductor integrated circuit device whose operation is controlled by a program such as a microcomputer, the internal operation is monitored using a debugging device in order to verify the execution result of the program.

  For this purpose, conventionally, a trace event / run control circuit for controlling the running and stopping of a program and a trace memory for storing program data, its address and various status signals are provided inside the semiconductor integrated circuit device. A microcomputer development support apparatus has been proposed (see, for example, Patent Document 1).

  When performing real-time debugging of a semiconductor integrated circuit device provided with such a trace memory, it is necessary to transfer data stored in the trace memory to the debugging device at a high speed. Therefore, in the microcomputer development support apparatus described above, parallel trace data stored in the trace memory is converted into serial data and transferred to the debug apparatus via a serial interface provided exclusively for debugging. Yes.

  By converting to serial data, the increase in the number of dedicated debugging pins that can only be used for debugging can be suppressed. However, since the data transfer capacity per unit time is smaller than that of parallel transfer, the speed of the semiconductor integrated circuit device is increased. There was a problem that it was difficult to follow.

JP 2001-249823 A (page 3-4, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device, a debugging device, and a debugging system that can perform high-speed real-time tracing.

  According to one aspect of the present invention, the processor, the parallel input interface, the parallel output interface, the running and stopping of the program executed by the processor are controlled, and based on the instruction execution information output from the processor. A semiconductor integrated circuit device having trace control means for generating trace information, wherein the normal operation input signal and the debug control signal input alternately every half cycle of the clock signal via the parallel input interface, Input signal separation means for separating the normal operation input signal input to the processor and the debug control signal input to the trace control means, normal operation output signal output from the processor, and output from the trace control means The trace information is a half-cycle of the clock signal. The semiconductor integrated circuit device characterized by comprising an output switching means for outputting via the parallel output interface switches each are provided.

  According to another aspect of the present invention, a debugging device includes a debugging unit that generates a debug control signal for controlling debugging of a semiconductor integrated circuit device and analyzes trace information output from the semiconductor integrated circuit device. An output switching means for switching and outputting a normal operation input signal output from a peripheral device and the debug control signal output from the debug means every half cycle of the clock signal, and the semiconductor integrated circuit An input that separates the normal operation output signal and the trace information that are alternately input from the device every half cycle of the clock signal into the normal operation output signal that is output to the peripheral device and the trace information that is output to the debug means. There is provided a debugging device comprising a signal separation means.

  According to the present invention, high-speed real-time tracing can be performed.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device, a debugging device, and a debugging system according to an embodiment of the present invention. The wave form diagram which shows the example of operation | movement at the time of debug mode of the debug system of the Example of this invention. The wave form diagram which shows the example of operation | movement at the time of debug mode of the debug system of the Example of this invention. FIG. 4 is a waveform diagram showing an example of operation during normal operation of the semiconductor integrated circuit device according to the embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device, a debugging device, and a debugging system according to an embodiment of the present invention.

  The debugging system of the present embodiment includes a semiconductor integrated circuit device 1 to be debugged, and a debugging device 2 that controls debugging execution of the semiconductor integrated circuit device 1 and analyzes trace information.

  The semiconductor integrated circuit device 1 of this embodiment is, for example, a microcomputer, has a processor 110, and has a parallel input I / F 120 and a parallel output I / F 130 as general-purpose interfaces (I / F).

  The semiconductor integrated circuit device 1 is provided with a trace control unit 140 for executing debugging. The trace control unit 140 controls the running and stopping of the program executed by the processor 110 and generates the trace information c2 based on the instruction execution information b1 output from the processor 110.

  In the present embodiment, in such a semiconductor integrated circuit device 1, in the debug mode, the normal operation input signal input to the processor 110 and the debug control signal input to the trace control unit 140 receive the parallel input I / F 120. Are alternately input every half cycle of the clock signal CK.

  Therefore, the semiconductor integrated circuit device 1 separates the signal input from the parallel input I / F 120 into a normal operation input signal a1 input to the processor 110 and a debug control signal a2 input to the trace control unit 140. A separation unit 11 is provided.

  The input signal separation unit 11 is composed of, for example, a latch 11A that uses the clock signal CK as a latch signal, and a latch 11B that uses a signal obtained by inverting the clock signal CK by the inverter IV1.

  In such an input signal separation unit 11, the latch 11A latches the signal input from the parallel input I / F 120 at the rising edge of the clock signal CK, and outputs the normal operation input signal a1 input to the processor 110. To do.

  The latch 11B latches the signal input from the parallel input I / F 120 at the falling edge of the clock signal CK, and outputs the debug control signal a2 input to the trace control unit 140.

  As described above, in this embodiment, in the debug mode, the normal operation input signal a1 to the processor 110 and the debug control signal a2 to the trace control unit 140 are input via the parallel input I / F 120, and the trace control unit 140 is input. Thus, the program execution control of the processor 110 and the generation of the trace information c2 are performed.

  In the present embodiment, the trace information c <b> 2 generated by the trace control unit 140 is output from the parallel output I / F 130. At this time, the normal operation output signal c1 and the trace information c2 output from the processor 110 are alternately output from the parallel output I / F 130 every half cycle of the clock signal CK.

  For this purpose, the semiconductor integrated circuit device 1 switches between the normal operation output signal c1 output from the processor 110 and the trace information c2 output from the trace control unit 140 every half cycle of the clock signal CK. An output switching unit 12 for outputting via F130 is provided.

  The switching signal s1 for the output switching unit 12 is generated by an AND gate AN1 that receives a signal obtained by delaying the clock signal CK by the delay circuit D1 and a debug mode signal DBM that becomes '1' in the debug mode. .

  When the clock signal CK is '0' and the normal operation output signal c1 is output from the parallel output I / F 130 by the switching signal s1 with a delay by the delay circuit D1, the clock signal CK is '1'. Trace information c2 is output.

  Next, the debug device 2 according to the present embodiment includes a debug unit 210 that generates a debug control signal for controlling debugging and analyzes trace information output from the semiconductor integrated circuit device. An output switching unit 21 that switches and outputs the normal operation input signal d1 output and the debug control signal d2 output from the debug unit 210 every half cycle of the clock signal CK, and a half of the clock signal from the semiconductor integrated circuit device. An input signal separation unit 22 that separates a normal operation output signal and trace information that are alternately input every period into a normal operation output signal e1 that is output to the peripheral device 1000 and a trace information e2 that is output to the debug unit 210; Is provided.

  The output switching unit 21 uses the switching signal s2 generated by the AND gate AN1 that receives the signal obtained by delaying the clock signal CK by the delay circuit D2 and the debug mode signal DBM, with a delay by the delay circuit D2. When the signal CK is “0”, the normal operation input signal d1 is output, and when the clock signal CK is “1”, the debug control signal d2 is output.

  The input signal separation unit 22 includes, for example, a latch 22A that uses the clock signal CK as a latch signal and a latch 22B that uses a signal obtained by inverting the clock signal CK by the inverter IV2 as a latch signal.

  In such an input signal separation unit 22, the latch 22A latches a signal input from the semiconductor integrated circuit device at the rising edge of the clock signal CK and outputs a normal operation output signal e1 output to the peripheral device 1000. To do.

  The latch 22B latches a signal input from the semiconductor integrated circuit device at the falling edge of the clock signal CK, and outputs trace information e2 output to the debug unit 210.

  When debugging the program execution operation of the semiconductor integrated circuit device 1 using the debug device 2, the following signals are input / output between them.

  That is, a signal output from the input / output switching unit 21 of the debug device 2 is input to the input signal separation unit 11 via the parallel input I / F 120 of the semiconductor integrated circuit device 1, and the output switching unit 12 of the semiconductor integrated circuit device 1 is input. Is input to the input signal separation unit 22 of the debug device 2 via the parallel output I / F 130.

  2 and 3 are waveform diagrams showing signal input / output states between the debugging device 2 and the semiconductor integrated circuit device 1. FIG.

  FIG. 2 shows a state of signal output from the debug device 2 to the semiconductor integrated circuit device 1.

  The output switching unit 21 of the debugging device 2 uses the switching signal s2 obtained by delaying the clock signal CK to generate a normal operation input signal d1 output from the peripheral device 1000 and a debug control signal d2 output from the debugging unit 210. The clock signal CK is switched and output every half cycle.

  As a result, when the data of the normal operation input signal d1 is D1, D2, D3, D4,... And the data of the debug control signal d2 is DB1, DB2, DB3, DB4,. As the output signal d3, data D1, DB1, D2, DB2, D3, DB3, D4, DB4,... Are output in half-cycle units of the clock signal CK.

  The output signal d3 of the output switching unit 21 is input to the parallel input I / F 120 of the semiconductor integrated circuit device 1. Therefore, this output signal d3 is set as an input signal d3 for the semiconductor integrated circuit device 1.

  The input signal separation unit 11 of the semiconductor integrated circuit device 1 includes a built-in latch 11A and a latch 11B, and a normal operation input signal a1 that is input to the processor 110 and a debug control signal that is input to the trace control unit 140. a2.

  At this time, since the latch 11A latches the input signal d3 at the rising edge of the clock signal CK, the normal operation input signal a1 output from the latch 11A is the data D1, D2, D3 of the normal operation input signal d1 output from the peripheral device 1000. D4,...

  On the other hand, since the latch 11B latches the input signal d3 at the falling edge of the clock signal CK, the output debug control signal a2 becomes the data DB1, DB2, DB3, DB4,... Of the debug control signal d2.

  Thus, in the debug operation mode, the debug control signal d2 output from the debug unit 210 of the debug device 2 is input as it is to the trace control unit 140 of the semiconductor integrated circuit device 1 as the debug control signal a2.

  FIG. 3 shows a state of signal output from the semiconductor integrated circuit device 1 to the debug device 2.

  The output switching unit 12 of the semiconductor integrated circuit device 1 generates a normal operation output signal c1 output from the processor 110 and trace information c2 output from the trace control unit 140 based on the switching signal s1 obtained by delaying the clock signal CK. The clock signal CK is switched and output every half cycle.

  As a result, when the data of the normal operation output signal c1 is AD1, AD2, AD3, AD4,... And the data of the trace information c2 is TR1, TR2, TR3, TR4,. The data AD1, TR1, AD2, TR2, AD3, TR3, AD4, TR4,... Are output in half-cycle units of the clock signal CK to the output signal c3 of the output switching unit 12 output via. .

  This output signal c3 becomes the input signal c3 for the debugging device 2.

  The input signal separation unit 22 of the debug device 2 includes a normal operation output signal e1 that outputs the input signal c3 to the peripheral device 1000, trace information e2 that is output to the debug unit 210, and latches 22A and 22B built therein. To separate.

  At this time, since the latch 22A latches the input signal c3 at the rising edge of the clock signal CK, the output of the normal operation output signal e1 is the data AD1, AD2, AD3, AD4 of the normal operation output signal c1 output from the processor 110. ..

  On the other hand, since the latch 22B latches the input signal c3 at the falling edge of the clock signal CK, the output trace information e2 becomes data TR1, TR2, TR3, TR4 of the trace information c2.

  Thus, in the debug operation mode, the trace information c2 output from the trace control unit 140 of the semiconductor integrated circuit device 1 is input as it is to the debug unit 210 of the debug device 2 as the trace information e2.

  As described above, at the time of debugging, the debug device 2 is connected to the semiconductor integrated circuit device 1, the input of the debug control signal a 2 via the parallel input I / F 120, and the trace information c 2 via the parallel output I / F 130. Is done.

  On the other hand, during normal operation, the semiconductor integrated circuit device 1 is directly connected to the peripheral device 1000, receives the normal operation input signal a1 via the parallel input I / F 120, and passes through the parallel output I / F 130. The normal operation output signal c1 is output.

  FIG. 4 is a waveform diagram showing input / output states of the semiconductor integrated circuit device 1 in the normal operation mode (debug mode signal DBM = “0”).

  In the normal operation mode, the input data D1, D2, D3, D4,... From the peripheral device 1000 to the parallel input I / F 120 are latched by the latch 11A of the input signal separation unit 11 at the rising edge of the clock signal CK. The operation input signal a1 is input to the processor 110.

  On the other hand, the data AD1, AD2, AD3, AD4,... Of the normal operation output signal c1 output from the processor 110 is because the switching signal s1 is always “0” when the debug mode signal DBM = “0”. Are always output from the output switching unit 12 and output as data AD1, AD2, AD3, AD4,... Of the output signal c3 via the parallel output I / F 130.

  According to the present embodiment, the trace control unit in the semiconductor integrated circuit device 1 is not obstructed by the normal operation of the semiconductor integrated circuit device 1 and without adding a dedicated debug control signal input interface. The trace control unit 140 can be controlled by inputting a debug control signal to 140.

  Further, the trace information generated by the trace control unit 140 inside the semiconductor integrated circuit device 1 is externally transmitted without obstructing the normal operation of the semiconductor integrated circuit device 1 and without adding a dedicated trace information output interface. Can be output.

  Further, since the parallel output I / F 130 is used for outputting the trace information, the data transfer capacity per unit time can be increased as compared with the conventional serial signal output method. As a result, the trace information can be output in real time. As a result, it is possible to eliminate the need for the trace memory, which has been conventionally required for storing the output-waiting trace information.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 11 Input signal separation part 11A, 11B Latch 12 Output switching part 2 Debugging device 21 Output switching part 22 Input signal separation part 22A, 22B Latch IV1, IV2 Inverter AN1, AN2 AND gate D1, D2 Delay circuit

Claims (5)

A processor, a parallel input interface, a parallel output interface, trace control means for controlling the running and stopping of a program executed by the processor and generating trace information based on instruction execution information output from the processor; A semiconductor integrated circuit device comprising:
The normal operation input signal and the debug control signal, which are alternately input every half cycle of the clock signal via the parallel input interface, the normal operation input signal input to the processor and the debug control input to the trace control means. Input signal separating means for separating the signal into a signal;
Output switching means for switching the normal operation output signal output from the processor and the trace information output from the trace control means for each half cycle of the clock signal and outputting via the parallel output interface. A semiconductor integrated circuit device. The input signal separating means is
A first latch for latching a signal input via the parallel input interface at a rising edge of a clock;
The semiconductor integrated circuit device according to claim 1, further comprising a second latch that latches a signal input via the parallel input interface at a falling edge of a clock. A debug apparatus that generates a debug control signal for controlling debugging of a semiconductor integrated circuit device and has a debugging unit that analyzes trace information output from the semiconductor integrated circuit device,
An output switching means for switching and outputting a normal operation input signal output from a peripheral device and the debug control signal output from the debug means for each half cycle of the clock signal;
A normal operation output signal that is alternately input from the semiconductor integrated circuit device every half cycle of the clock signal and the trace information; the normal operation output signal that is output to the peripheral device; and the trace information that is output to the debugging means. A debugging device comprising: an input signal separation means for separating the input signal into The input signal separating means is
A first latch for latching a signal input from the semiconductor integrated circuit device at a rising edge of a clock;
The debugging apparatus according to claim 3, further comprising a second latch that latches a signal input from the semiconductor integrated circuit device at a falling edge of a clock. A debug system having the semiconductor integrated circuit device according to claim 1 or 2 and the debug device according to claim 3 or 4,
A signal output from the output switching means of the debug device is input to the semiconductor integrated circuit device via the parallel input interface;
A debugging system for outputting a signal output from the output switching means of the semiconductor integrated circuit device to the debugging device via the parallel output interface.

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