JP2010161378A - Semiconductor integrated circuit device, signal processing apparatus, and semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, capable of reducing the effect due to clock noise, and to provide a signal processing apparatus with the semiconductor integrated circuit device mounted thereon, and to provide a semiconductor module. <P>SOLUTION: The semiconductor integrated circuit device 4 includes a semiconductor substrate 10a; integrated circuit blocks 17, 19 formed thereon; a first electrode pad 11, where a first clock BPFCLK1 is inputted through a first lead terminal 61 and a first bonding wire 11a; wiring lines 23, 24 that connect the integrated circuit blocks 17, 19 and the first electrode pad 11; and a second electrode pad 12 where a second clock BPFCLK2 is inputted that is provided, at a position adjacent to the first electrode pad 11 on the semiconductor substrate 10a, is not connected to the integrated circuit blocks 17, 19, and has identical frequency as in the first clock BPFCLK1, as well as, a period where polarity is reversed through a second lead terminal 62 and a second bonding wire 12a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a signal processing device such as an FM multiplex data processing device used in, for example, a VICS (VEHICLE INFORMATION AND COMMUNICATION SYSTEM) FM multiplex broadcast receiver, and a semiconductor mounted on the device. The present invention relates to an integrated circuit device, and more particularly to reduction of clock noise in a semiconductor integrated circuit device such as an analog filter LSI.

  FIG. 6 is a diagram showing a configuration of a conventional FM multiplex broadcast receiver that decodes VICS-FM multiplex data. An FM multiplex data processing device 31 shown in FIG. 6 extracts an analog filter for extracting a VICS digital signal BPFO from an FM baseband signal (FM multiplex signal) including multiplex data received by the FM antenna 2 and the FM tuner 3. The IC 34 includes a VICS logic IC 35 that receives and decodes the digital signal BPFO output from the analog filter IC 34, and a microcontroller (microcomputer) 36 that extracts and processes the VICS data from the VICS logic IC 35. A VICS-FM multiplex broadcast receiver is disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 11-234153).

  FIG. 7 is a diagram showing a configuration of the analog filter IC 34 of FIG. As shown in FIG. 7, the analog filter IC 34 includes a semiconductor integrated circuit element (IC chip) 40, a plurality of lead terminals (signals BPFCLK, AIN, SG, and BPFO are input or output), and these lead terminals. And bonding wires 41a, 43a, 44a, and 52a for connecting the electrode pads 41, 43, 44, and 52 of the IC chip 40 to each other. A single-phase clock (for example, 2 MHz) from the VICS logic IC 35 is supplied to the electrode pad 41 of the analog filter IC 34. The IC chip 40 includes various integrated circuit blocks formed on a semiconductor substrate, such as a low-pass filter (LPF) 45, an amplifier circuit (Amp) 46, and a band-pass filter constituted by a switched capacitor (SC) filter. (BPF) 47, amplification circuit (Amp) 48, delay detection circuit (1 / T) 49, low-pass filter (LPF) 50, and amplification circuit (Amp) 51. The low-pass filter 45, the amplifier circuit 46, the band-pass filter 47, and the amplifier circuit 48 are filter units for extracting, for example, a 76 kHz ± 4 kHz LMSK (Level Controlled Minimum Shift Keying) digital signal from the FM multiplexed signal AIN. As a function. The delay detection circuit 49, the low-pass filter 50, and the amplification circuit 51 function as a delay detection unit that reproduces, for example, a 16 kbit / s digital signal BPFO from the LMSK-modulated digital signal.

Japanese Patent Laid-Open No. 11-234153 (FIG. 1, paragraphs 0017-0019) JP 2001-125744 A (paragraph 0013) JP 2000-269793 A (paragraph 0030)

  However, in the analog filter IC 34 to which the single-phase clock BPFCLK supplied from the VICS logic IC 35 is input, the parasitic capacitance between the electrode pad 41 of the IC chip 40 and each of the integrated circuit blocks 45, 47, 49, 50 (see FIG. 8 is represented by reference numerals Cp1, Cp2, Cp3, and Cp4.), The operating characteristics of the low-pass filters 45 and 50 and the band-pass filter 47 are adversely affected. In particular, there is a problem in that the characteristics of a circuit having a capacitor that is temporarily in a floating state and that has a capacitor having a relatively small capacitance value has a great influence. For example, Patent Document 2 (Japanese Patent Application Laid-Open No. 2001-125744) discloses a reduction in the influence of a noise signal, and Patent Document 3 (Japanese Patent Application Laid-Open No. 2000-269793) discloses a stray capacitance. There is disclosure.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a semiconductor integrated circuit device, a signal processing device, and a semiconductor capable of reducing the influence of clock noise. To provide a module.

  A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate, a plurality of integrated circuit blocks formed on the semiconductor substrate, a first electrode pad provided on the semiconductor substrate and to which a first clock is input. A wiring line that is provided on the semiconductor substrate and connects the plurality of integrated circuit blocks and the first electrode pad; and a position adjacent to the first electrode pad on the semiconductor substrate; A second electrode pad that is not connected to a plurality of integrated circuit blocks and that receives a second clock having the same frequency as the first clock and having a period in which the polarity is reversed. One of the integrated circuit blocks is a first integrated circuit block having a band-pass filter function.

  The signal processing apparatus according to the present invention includes a first semiconductor integrated circuit device having the same configuration as the semiconductor integrated circuit device, and a second semiconductor integrated circuit device that outputs the first clock and the second clock. A first clock wiring for supplying the first clock output from the second semiconductor integrated circuit device to the first lead terminal of the first semiconductor integrated circuit device; And a second clock wiring for supplying the second clock output from the second semiconductor integrated circuit device to the second lead terminal of the first semiconductor integrated circuit device.

  Further, the semiconductor module of the present invention includes a first semiconductor integrated circuit device that generates a first clock and a second clock having the same frequency as the first clock and having a period in which the polarity is reversed, An analog filter circuit having an integrated circuit block; a first electrode pad to which the first clock is input; a wiring line connecting the plurality of integrated circuit blocks and the first electrode pad; A second electrode pad that is provided in a position adjacent to the plurality of electrode pads, is in non-contact with the plurality of integrated circuit blocks, and receives the second clock; the analog filter circuit; and the first electrode pad And a second semiconductor integrated circuit device arranged in the vicinity of the first semiconductor integrated circuit device. It is.

  According to the semiconductor integrated circuit device, the arithmetic processing unit, and the semiconductor module of the present invention, the noise generated in the integrated circuit block by the first clock input to the first electrode pad and the same frequency as the first clock are generated. The noise generated in the integrated circuit block due to the second clock input to the second electrode pad cancels each other, and has a period in which the polarity is reversed, so that the noise of the digital signal output from the integrated circuit block The effect that can be reduced can be obtained.

  Further, according to the semiconductor module of the present invention, noise of the output digital signal can be reduced, so that an effect of improving the reception sensitivity (reception range) of the FM signal can be obtained.

It is a figure which shows the structure of the FM multiplex broadcast receiver which concerns on embodiment of this invention. It is a figure which shows the structure of the analog filter IC of FIG. FIG. 2 is a diagram schematically showing a part of the layout of the analog filter IC of FIG. 1. FIG. 3 is an explanatory diagram of parasitic capacitance of the analog filter IC of FIG. 2. It is a wave form diagram for demonstrating the influence reduction of a clock noise. It is a figure which shows the structure of the conventional FM multiplex broadcast receiver. It is a figure which shows the structure of the analog filter IC of FIG. It is explanatory drawing of the parasitic capacitance of the analog filter IC of FIG.

  FIG. 1 is a diagram showing a configuration of an FM broadcast receiver according to an embodiment of the present invention that decodes VICS-FM multiplexed data. An FM multiplex data processing apparatus 1 shown in FIG. 1 is an analog filter for extracting a VICS digital signal from an FM baseband signal (FM multiplex signal) AIN including multiplex data received by an FM antenna 2 and an FM tuner 3. IC 4, VICS logic IC 5 that receives and decodes digital signal BPFO output from analog filter IC 4, and microcontroller (microcomputer) 6 that extracts and processes VICS data from VICS logic IC 5. In FIG. 1, reference numeral 7 denotes a first clock for supplying the first clock BPFCLK1 output from the VICS logic IC5 to the first lead terminal (reference numeral 61 in FIGS. 2 and 3) of the analog filter IC4. Reference numeral 8 denotes a second wiring for supplying the second clock BPFCLK2 output from the VICS logic IC5 to the second lead terminal (reference numeral 62 in FIGS. 2 and 3) of the analog filter IC4. This is a clock wiring.

  FIG. 2 is a diagram showing a configuration of the analog filter IC 4 of FIG. As shown in FIG. 2, the analog filter IC 4 includes a semiconductor integrated circuit element (IC chip) 10, a plurality of lead terminals 61 to 65, these lead terminals 61 to 65, and electrode pads 11, 12, IC chip 10. Bonding wires 11a, 12a, 13a, 14a, and 22a for connecting 13, 14, and 22 are provided. The analog filter IC4 receives the first clock BPFCLK1 (for example, 2 MHz) from the VICS logic IC5 and the second clock BPFCLK2 having the same frequency as the first clock BPFCLK1 and having a period in which the polarity is reversed. The The second clock BPFCLK2 is normally an inverted signal of the first clock BPFCLK1.

  In the analog filter IC4 of FIGS. 1 and 2, AIN indicates an FM multiplexed signal input from the lead terminal 63, and SG indicates an analog reference voltage at the lead terminal 64 in which a noise preventing capacitor 66 is connected between the grounds. Show. 1 and FIG. 2, BPFCLK1 indicates a first clock input to the first lead terminal 61, and BPFCLK2 indicates a second clock input to the second lead terminal 62. BPFO represents a digital signal output from the lead terminal 65.

  In the VICS logic IC 5 of FIG. 1, BPFCLK1 indicates a first clock output from the VICS logic IC5, BPFCLK2 indicates a second clock output from the VICS logic IC5, and BPFO is input to the VICS logic IC5. The digital signal to be displayed. Further, in the VICS logic IC 5 and the microcomputer 6 in FIG. 1, Addr indicates an address signal to an internal register (not shown) in the VICS logic IC 5, and Data indicates an internal register (not shown) in the VICS logic IC 5. Data bus signals to are shown. In the VICS logic IC 5 and the microcomputer 6 of FIG. 1, WRN indicates a write signal to an internal register (not shown) in the VICS logic IC 5, and RDN is an internal register (not shown) in the VICS logic IC 5. The INTN indicates an interrupt signal to the microcomputer 6.

  The IC chip 10 includes various integrated circuit blocks formed on a semiconductor substrate, such as a low-pass filter (LPF) 15, an amplifier circuit (Amp) 16, and a band-pass filter (BPF) configured by a switched capacitor (SC) filter. ) 17, an amplifier circuit (Amp) 18, a delay detection circuit (1 / T) 19, a low-pass filter (LPF) 20, and an amplifier circuit (Amp) 21. The first clock BPFCLK 1 is supplied to the band pass filter 17 and the delay detection circuit 19 through the wiring lines 23 and 24. The low-pass filter 15, the amplifier circuit 16, the band-pass filter 17, and the amplifier circuit 18 have a function as a filter unit for extracting, for example, a 76 kHz ± 4 kHz LMSK-modulated digital signal from the FM multiplexed signal AIN. The delay detection circuit 19, the low-pass filter 20, and the amplification circuit 21 function as a delay detection unit that reproduces, for example, a 16 kbit / s digital signal BPFO from the LMSK-modulated digital signal.

  FIG. 3 is a diagram schematically showing a layout of a part of the analog filter IC4 of FIG. As shown in FIG. 3, the semiconductor integrated circuit device 4 includes a semiconductor substrate 10a, an integrated circuit block 17 (or 19) formed on the semiconductor substrate 10a, a first lead terminal 61, and a first bonding wire. The first electrode pad 11 to which the first clock BPFCLK1 is input through 11a, the wiring line 23 (or 24) connecting the integrated circuit block 17 (or 19) and the first electrode pad 11, and the semiconductor substrate 10a It is provided at a position adjacent to the upper first electrode pad 11, is not connected to the integrated circuit blocks 17 and 19, and is the same as the first clock BPFCLK1 through the second lead terminal 62 and the second bonding wire 12a. A second electrode pad 12 to which a second clock BPFCLK2 having a frequency and a polarity reversal period is input. To. The first lead terminal 61, the second lead terminal 62, the first bonding wire 11a, the second bonding wire 12a, the semiconductor substrate 10a, and the configuration on the semiconductor substrate 10a (first The electrode pad 11, the second electrode pad 12, the wiring lines 23 and 24, the integrated circuit blocks 17 and 19) are packaged with a sealing resin. Further, it is desirable that the distance from the integrated circuit block 17 (or 19) to the first electrode pad 11 and the distance to the second electrode pad 12 are substantially equal. The interval between the first lead terminal 61 and the second lead terminal 62 is determined by the package terminal pitch (terminal interval), and is generally within a range of 0.3 mm to 1.3 mm. is there. Further, the distance between the first electrode pad 11 and the second electrode pad 12 is generally in the range of 40 μm to 1.3 mm. In LSI, the pad shape is basically a square. Each of the first electrode pad 11 and the second electrode pad 12 is generally a quadrangle of about 100 square μm. Furthermore, the layout of the analog filter IC4 is not limited to the example of FIG. 3, and various modifications are possible.

  FIG. 4 is an explanatory diagram of the parasitic capacitance of the analog filter IC of FIG. In the analog filter IC4 to which the first clock BPFCLK1 supplied from the VICS logic IC5 is input, the parasitic capacitance between the electrode pad 11 of the IC chip 10 and each integrated circuit block 15, 17, 19, 20 (FIG. 4). The noise generated by the symbols Cp1, Cp2, Cp3, and Cp4) adversely affects the operating characteristics of the low-pass filters 15 and 20 and the band-pass filter 17. In particular, a circuit that temporarily has a floating state and has a capacitor having a relatively small capacitance value has a great influence. Therefore, in the present invention, it is provided at a position adjacent to the first electrode pad 11 on the semiconductor substrate 10a, is not connected to the integrated circuit block, has the same frequency as the first clock BPFCLK1, and the polarity is reversed. A second electrode pad 12 to which a second clock BPFCLK2 having a period is input is provided. The second electrode pad 12 receives the second clock BPFCLK2 from the VICS logic IC 5 through the second lead terminal 62 and the second bonding wire 12a. In the analog filter IC4 to which the second clock BPFCLK2 is input, the parasitic capacitance between the second electrode pad 12 of the IC chip 10 and each of the integrated circuit blocks 15, 17, 19, 20 (references Cn1, Cn2, Cn3, and Cn4) generate noise. In the present invention, the noise generated in the integrated circuit block by the first clock BPFCLK1 input to the first electrode pad 11 and the noise generated in the integrated circuit block by the second clock BPFCLK2 are added and cancel each other. Therefore, the noise of the digital signal BPFO output from the integrated circuit block can be reduced.

  FIG. 5 is a waveform diagram for explaining the reduction of the influence of clock noise. The waveform shown in the upper part of FIG. 5 is the first clock BPFCLK1 having a period T (or a noise waveform generated by the first clock BPFCLK1), and the waveform shown in the middle part of FIG. This is a clock BPFCLK2 (or a noise waveform generated by the second clock BPFCLK2). The waveform shown in the lower part of FIG. 5 cancels each other by adding the noise caused by the first clock BPFCLK1 shown in the upper part of FIG. 5 and the noise caused by the second clock BPFCLK2 shown in the middle part of FIG. This is the noise model waveform that results from the fitting. In FIG. 5, Tw is a delay time from the rise of the first clock BPFCLK1 to the fall of the second clock BPFCLK2. The delay time Tw is a delay time that occurs when the first clock BPFCLK1 is inverted by the inverting circuit to generate the second clock BPFCLK2.

The signal waveform shown in FIG.
= Σ 2 * sin (2π * n * a / T) / (2π * n) * exp (j * n * ω ₀ * t)
Can be expressed as Here, exp (j * n * ω ₀ * t) represents a cycle, and the cycle of the first clock BPFCLK1 and the second clock BPFCLK2 in FIG. 5 is the same. It is not necessary to calculate this term when comparing the lower waveform of FIG.

Here, regarding the waveform shown in the upper part of FIG.
T = 500 ns (when the frequency is 2 MHz)
a = T / 2/2 = 500/2/2
n = 1 (when the frequency is 2 MHz)
Then,
2 * sin (2π * n * a / T)
= 2 * sin (2π * 1 * (500/2/2) / 500)
= 2 * sin (π / 2)
= 2
It becomes.

In addition, regarding the waveform shown in the lower part of FIG.
T = 500ns (when the frequency is 2MHz)
a = 20/2 (in the case of 20 ns deviation)
n = 1 (when the frequency is 2 MHz)
Then,
2 * sin (2π * n * a / T)
= 2 * sin (2π * 1 * (20/2) / 500)
= 0.125
It becomes.

  Therefore, the noise when the second clock BPFCLK2 is not input and the noise when the second clock BPFCLK2 is input are 1: 0.125 with respect to the 2 MHz component, and when the second clock BPFCLK2 is input. It can be seen that the noise level has been reduced.

  As described above, according to the semiconductor integrated circuit device 4 and the FM multiple data processing device 1 according to the embodiment of the present invention, the integrated circuit block 15 is received by the first clock BPFCLK1 input to the first electrode pad 11. , 17, 19 and 20 and an integrated circuit block by the second clock BPFCLK2 having the same frequency as the first clock BPFCLK1 and having a period in which the polarity is reversed and inputted to the second electrode pad 12 Since the noises generated at 15, 17, 19, and 20 cancel each other, the noise of the digital signal BPFO output from the integrated circuit block can be reduced.

  Further, according to the FM multiplex data processing apparatus 1 according to the embodiment of the present invention, the noise of the output digital signal can be reduced, so that the reception sensitivity (reception range) of the FM signal can be improved.

  Furthermore, according to the FM multiplex broadcast receiver using the FM multiplex data processing apparatus 1 according to the embodiment of the present invention, noise can be reduced, so that an FM tuner 3 mounted on a VICS board (not shown). It is possible to dispose the analog filter IC4 in the vicinity of, and there is an advantage that the degree of freedom of disposition of the IC on the VICS substrate is improved. Further, there is an advantage that the FM tuner IC (FM tuner 3) and the analog filter IC 4 can be integrated into one IC.

  In the above description, the case where the semiconductor integrated circuit device is the analog filter IC 4 has been described. However, the present invention can also be applied to other ICs to which a clock is input from the outside. The present invention can also be applied to signal processing apparatuses other than the FM multiplex data processing apparatus 1.

  DESCRIPTION OF SYMBOLS 1 FM multiplex data processing apparatus, 2 FM antenna, 3 FM tuner, 4 Analog filter IC, 5 VICS logic IC, 6 Microcontroller (microcomputer), 7 1st clock wiring, 8 2nd clock wiring, 10 IC A chip (semiconductor integrated circuit element), 10a a semiconductor substrate, 11 a first electrode pad to which a first clock is input, 11a a first bonding wire, 12 a second electrode pad to which a second clock is input, 12a Second bonding wire, 13, 14, 22 electrode pad, 15 low-pass filter (LPF), 16, 18, 21 amplifier circuit (Amp), 17 band-pass filter (BPF), 19 delay detection circuit (1 / T), 20 Low-pass filter (LPF), 23, 24 Wiring line IN, 61 first lead terminal, 62 second lead terminal, BPFCLK1 first clock, BPFCLK2 second clock, BPFO digital signal.

Claims (20)

A semiconductor substrate;
A plurality of integrated circuit blocks formed on the semiconductor substrate;
A first electrode pad provided on the semiconductor substrate and receiving a first clock;
A wiring line provided on the semiconductor substrate and connecting the plurality of integrated circuit blocks and the first electrode pad;
The first electrode pad on the semiconductor substrate is provided adjacent to the first electrode pad, is not connected to the plurality of integrated circuit blocks, has the same frequency as the first clock, and has a period in which the polarity is reversed. A second electrode pad to which two clocks are input,
One of the plurality of integrated circuit blocks is a first integrated circuit block having a bandpass filter function. A semiconductor integrated circuit device, wherein: 2. The semiconductor integrated circuit device according to claim 1, wherein another one of the plurality of integrated circuit blocks is a second integrated circuit block having a delay detection function.   The semiconductor integrated circuit device according to claim 1, wherein the second clock is an inverted signal of the first clock.   4. The semiconductor integrated circuit device according to claim 1, wherein a distance from the integrated circuit block to the first electrode pad is substantially equal to a distance from the second electrode pad. A first lead terminal;
A first bonding wire for electrically connecting the first lead terminal and the first electrode pad;
A second lead terminal;
A second bonding wire for electrically connecting the second lead terminal and the second electrode pad;
The first clock is input to the first electrode pad via the first lead terminal and the first bonding wire;
5. The device according to claim 1, wherein the second clock is input to the second electrode pad through the second lead terminal and the second bonding wire. 6. Semiconductor integrated circuit device. A first semiconductor integrated circuit device having the same configuration as the semiconductor integrated circuit device according to claim 5;
A second semiconductor integrated circuit device for outputting the first clock and the second clock;
A first clock wiring for supplying the first clock output from the second semiconductor integrated circuit device to the first lead terminal of the first semiconductor integrated circuit device;
And a second clock wiring for supplying the second clock output from the second semiconductor integrated circuit device to the second lead terminal of the first semiconductor integrated circuit device. A signal processing device. A first semiconductor integrated circuit device that generates a first clock and a second clock having the same frequency as the first clock and having a period in which the polarity is reversed;
An analog filter circuit having a plurality of integrated circuit blocks; a first electrode pad to which the first clock is input; a wiring line connecting the plurality of integrated circuit blocks and the first electrode pad; A second electrode pad provided adjacent to the first electrode pad, in contact with the plurality of integrated circuit blocks, to which the second clock is input, and the first semiconductor integrated circuit; A second semiconductor integrated circuit device disposed in the vicinity of the circuit device;
A semiconductor module comprising: The semiconductor module according to claim 7, wherein the analog filter circuit extracts digital data from an FM baseband signal including multiplexed data. The semiconductor module according to claim 7, wherein the first semiconductor integrated circuit device includes a decoding circuit that performs a decoding process on the digital data extracted by the analog filter circuit. The second semiconductor integrated circuit device comprises:
A first lead terminal;
A first bonding wire for electrically connecting the first lead terminal and the first electrode pad;
A second lead terminal;
A second bonding wire for electrically connecting the second lead terminal and the second electrode pad;
The first clock is input to the first electrode pad via the first lead terminal and the first bonding wire;
The said 2nd clock is input into the said 2nd electrode pad via the said 2nd lead terminal and the said 2nd bonding wire. The any one of Claim 7 to 9 characterized by the above-mentioned. Semiconductor module. A first clock wiring for supplying the first clock output from the first semiconductor integrated circuit device to the first lead terminal of the second semiconductor integrated circuit device;
And a second clock wiring for supplying the second clock output from the first semiconductor integrated circuit device to the second lead terminal of the second semiconductor integrated circuit device. The semiconductor module according to claim 10.   The semiconductor module according to claim 7, wherein the second clock is an inverted signal of the first clock.   13. The semiconductor module according to claim 7, wherein a distance from the integrated circuit block to the first electrode pad is substantially equal to a distance from the second electrode pad. The semiconductor module according to any one of claims 7 to 13, wherein one of the plurality of integrated circuit blocks is a first integrated circuit block having a band-pass filter function. The semiconductor module according to any one of claims 7 to 14, wherein the other one of the plurality of integrated circuit blocks is a second integrated circuit block having a delay detection function. The semiconductor module according to claim 7, further comprising an FM tuner in the vicinity of the second semiconductor integrated circuit device. The semiconductor module according to claim 16, wherein an antenna is connected to the FM tuner. The semiconductor module according to claim 7, wherein the second semiconductor integrated circuit device further includes an integrated circuit having an FM tuner function. The semiconductor module according to claim 18, wherein an antenna is connected to the integrated circuit having the FM tuner function. 20. The semiconductor module according to claim 7, wherein a circuit formed in the second semiconductor integrated circuit device is not connected to the second electrode pad.

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