JP2010154720A - Secondary battery device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a secondary battery device for properly performing charge control and discharge control even when a plurality of secondary batteries are connected in series to be used as a power source for a high power load. <P>SOLUTION: The secondary battery is divided into a plurality of battery blocks, and a first sensing resistor for detecting a charging current is embedded for each block. In charging, the plurality of battery blocks are connected in parallel, and charging the secondary battery is controlled on the basis of a charging current to be detected via the first sensing resistor for each of the battery blocks. Meanwhile, in discharging, the plurality of battery blocks are connected in series while bypassing the first sensing resistor, and a second sensing resistor for detecting a discharging current is interposed in the discharge path. In addition, discharging from the plurality of secondary batteries is controlled on the basis of a discharge current to be detected via the second sensing resistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a secondary battery device that is used as a power supply source for a high voltage load by connecting a plurality of secondary batteries in series.

A secondary battery device used as a power source that requires a large amount of electric power such as an electric vehicle has a plurality of secondary batteries composed of lithium ion batteries, nickel metal hydride batteries, etc., in series, in parallel, or in parallel, or Connected in series and parallel. Specifically, the required output voltage is secured by connecting a plurality of secondary batteries in series, and the required output current is secured by connecting a plurality of secondary batteries in parallel. Yes. In addition, it detects the fully charged state by detecting the charging current of the secondary battery, and controls the charge, or manages the charge amount (remaining battery capacity) of the secondary battery based on the discharge current to reach the deep discharge state. The discharge is also controlled to stop before (see, for example, Patent Document 1).
JP 2003-168488 A

  By the way, in the secondary battery device used by connecting a plurality of secondary batteries in series or in parallel as described above, there is a variation in characteristics (battery performance) due to the individuality of the secondary battery. It is important to accurately detect the charge / discharge current of each secondary battery in order to properly control the battery. Incidentally, the charge / discharge current of the secondary battery is detected by inserting a sensing resistor (shunt resistor) for current detection in series in the charge / discharge path and measuring the voltage drop at the resistor. However, when a sensing resistor (shunt resistor) is inserted in series in each of a plurality of secondary batteries used in series, a plurality of sensing resistors (shunt resistors) are also connected in series as a whole. Therefore, the voltage drop at these sensing resistors (shunt resistors) cannot be ignored.

  The present invention has been made in view of such circumstances, and its purpose is to control charging and discharging even when a plurality of secondary batteries are connected in series and used as a power source for a large power load. It is an object of the present invention to provide a secondary battery device having a simple configuration capable of appropriately performing the above.

In order to achieve the above-described object, the secondary battery device according to the present invention includes a plurality of secondary batteries and is suitable for use as a power source of a large power load,
Dividing a plurality of secondary batteries into a plurality of battery blocks, and incorporating a first sensing resistor for detecting a charging current for each battery block,
At the time of charging the plurality of secondary batteries, the plurality of battery blocks are connected in parallel, and the charging to the secondary battery is controlled based on the charging current detected for each battery block via the first sensing resistor,
On the other hand, when discharging a plurality of secondary batteries, the plurality of battery blocks are connected in series by bypassing the first sensing resistors in the plurality of battery blocks, and a discharge current is detected in a discharge path formed by these battery blocks. The second sensing resistor is inserted in series, and discharge from the plurality of secondary batteries is controlled based on the discharge current detected through the second sensing resistor.

  Preferably, each of the battery blocks is realized as an individual CPU unit for charge / discharge management. The charging / discharging control for the plurality of secondary batteries is performed by connecting the plurality of battery blocks in parallel under the control of a host CPU unit that communicates information with the CPU unit of each battery block. This is done by setting the CPU unit of the block to the charge management mode, or connecting the plurality of battery blocks in series and setting the CPU unit of each battery block to the discharge management mode.

Incidentally, in the charging control for the plurality of secondary batteries, the charging of each battery block is individually stopped by detecting the full charge from the change in the charging current detected through the first sensing resistor for each battery block. Control is performed by stopping power supply to each battery block when the secondary batteries of all the battery blocks have reached full charge.
The discharge control for the plurality of secondary batteries is performed by notifying the discharge current detected via the second sensing resistor from the host CPU unit to the CPU unit of each battery block, and for each battery block. This is done by managing the remaining battery capacity and stopping the discharge from all the battery blocks collectively under the instruction from the host CPU unit when the remaining battery capacity reaches the lower limit. .

  According to the secondary battery device having the above configuration, a plurality of battery blocks are connected in parallel at the time of charging, and each current block is determined according to the charging current detected by the first sensing resistor incorporated in each power block. Since the charging of the secondary battery is individually controlled, the charging can be appropriately controlled regardless of the individuality of the secondary battery. When discharging (when supplying power to a large power load), the plurality of battery blocks are connected in series by bypassing the first sensing resistor in each battery block, and a second sensing resistor is connected to the discharge path. Since the discharge current is detected by being inserted in series, power can be supplied without being affected by the first sensing resistor. Moreover, overall, a plurality of sensing resistors (shunt resistors; first sensing resistors) are not individually connected in series to each battery block.

Hereinafter, a secondary battery device according to an embodiment of the present invention will be described with reference to the drawings.
In this secondary battery device, for example, as shown in FIG. 1, a plurality of secondary batteries are divided into a plurality (n) of battery blocks 1a, 1b to 1n, and when charging, these battery blocks 1a, 1b to 1n are connected in parallel, while the plurality of battery blocks 1a and 1b to 1n are connected in series during discharging. The secondary battery is made of, for example, a nickel metal hydride battery, and each of the battery blocks 1a, 1b to 1n has a required battery voltage and current capacity by connecting a predetermined number of battery cells (unit batteries) in series and parallel. It consists of the thing which secured. The secondary battery may be a lithium ion battery or the like.

  Each of the battery blocks 1a, 1b to 1n is individually incorporated with CPU units 2a, 2b to 2n for controlling charging and discharging, and a first sensing resistor for detecting a charging current. (Shunt resistor R1) 3a, 3b to 3n are respectively inserted in series in the charging path and unitized as described later. In particular, each of the battery blocks 1a, 1b-1n is connected in parallel to a pair of charging terminals 5p, 5n via charge switches (SW) 4a, 4b-4n and the first sensing resistors 3a, 3b-3n, respectively. ing. These charging switches (SW) 4a, 4b to 4n are connected to the respective battery blocks 1a, 1b to 1n through the first sensing resistors 3a, 3b to 3n individually by their conduction (ON). The battery blocks 1a and 1b to 1n are individually charged with power supplied from a DC power source (not shown).

  The plurality of battery blocks 1a, 1b to 1n are connected in series between a pair of discharge terminals 7p and 7n via a plurality of discharge switches (SW10) 6a and 6b to 6n, respectively. These discharge switches (SW10) 6a, 6b to 6n are collectively turned on / off, and the first sensing resistors 3a, 3b to 3n are bypassed by the conduction (on), respectively. The battery blocks 1a, 1b to 1n are connected in series between the pair of discharge terminals 7p, 7n to form a discharge path for supplying power to a load (not shown) connected to the discharge terminals 7p, 7n. Take on. Further, a second sensing resistor (shunt resistor R2) 8 for detecting a discharge current is provided in a discharge path formed by connecting a plurality of battery blocks 1a, 1b to 1n in series between the pair of discharge terminals 7p, 7n. It is inserted in series.

  Further, the secondary battery device is provided with a host CPU unit 9 that controls charge control and discharge control for the plurality of battery blocks 1a, 1b to 1n. The host CPU unit 9 basically connects the battery blocks 1a and 1b to 1n in parallel by turning on the charge switches (SW1 to 7) 4a and 4b to 4n described above when charging, and the above-described charging switches (SW1 to 7b) when discharging. The discharge switches (SW10) 6a and 6b to 6n are turned on to play a role of connecting the battery blocks 1a and 1b to 1n in series.

  The host CPU unit 9 has a function of detecting a discharge current via the second sensing resistor 8, and is mutually connected with the CPU units 2a, 2b-2n of the battery blocks 1a, 1b-1n. Has a function of communicating information. As will be described later, the host CPU unit 9 notifies the CPU units 2a, 2b to 2n of the information on the discharge current detected through the second sensing resistor 8 at the time of discharging, as well as each CPU unit 2a, The battery blocks 1a and 1b to 1n managed by 2b to 2n sequentially collect charge / discharge state information and play a role of controlling the overall operation of the secondary battery device. Information that the host CPU unit 9 collects from each of the CPU units 2a, 2b to 2n is information on whether or not each of the battery blocks 1a, 1b to 1n has reached full charge during charging, as will be described later. Sometimes it consists of information on whether or not the battery capacity (remaining charge capacity) of the secondary battery in each of the battery blocks 1a, 1b to 1n has reached a preset capacity lower limit value before reaching the deep discharge state. The host CPU unit 9 obtains such information from each of the CPU units 2a, 2b to 2n, thereby controlling the overall charge / discharge.

  2 (a) and 2 (b) show an equivalent configuration at the time of charging and discharging of the secondary battery device configured as described above. That is, when charging, the plurality of battery blocks 1a, 1b-1n are connected in parallel via the first sensing resistors 3a, 3b-3n, respectively, by turning on the charging switches (SW1-7) 4a, 4b-4n. And connected between the pair of charging terminals 5p and 5n. At this time, the discharge switches (SW10) 6a, 6b to 6n are kept in the cut-off (off) state, and the plurality of battery blocks 1a, 1b to 1n are separated from the pair of discharge terminals 7a and 7b.

  The CPU units 2a, 2b-2n incorporated in the battery blocks 1a, 1b-1n are respectively detected by the battery blocks 1a, 1b individually detected via the first sensing resistors 3a, 3b-3n, respectively. The charging current to ˜1n is detected, and the current is integrated in the CPU units 2a, 2b to 2n of the battery blocks 1a, 1b to 1n. Moreover, in the CPU units 2a, 2b-2n of the battery blocks 1a, 1b-1n, when the battery voltage is monitored and a peak voltage is detected or a voltage drop of ΔV is detected, this is detected as a full charge. (When the secondary battery is a nickel metal hydride battery) When the secondary battery is a lithium ion battery, the charging currents to the battery blocks 1a, 1b to 1n, which are individually detected through the first sensing resistors 3a, 3b to 3n, respectively, Monitoring is performed, and when the charging current decreases to a preset current value, this may be detected as a full charge.

  The full charge detection state is notified to the host CPU unit 9, and the charge switches (SW1 to SW7) 4 for connecting the battery blocks 1 (1a, 1b to 1n) reaching the full charge to the charging terminals 5p and 5n. (4a, 4b to 4n) are cut off (off), whereby charging to the battery block 1 (1a, 1b to 1n) is stopped. As a result, when the battery block 1 (1a, 1b to 1n) that has reached full charge is stopped in order, and all the battery blocks 1 (1a, 1b to 1n) are charged to full charge, the charge is performed. Control ends.

  On the other hand, at the time of discharging, the charge switches (SW1-7) 4a, 4b-4n are cut off (off), and instead, the discharge switches (SW10) 6a, 6b-6n are turned on (on). The plurality of battery blocks 1a, 1b-1n are connected in series via the second sensing resistor 8 by the conduction (ON) of the discharge switches (SW10) 6a, 6b-6n, and a pair of discharge terminals 7a, 7b. At this time, the first sensing resistors 3a, 3b-3n are disconnected from the battery blocks 1a, 1b-1n, respectively, in accordance with the interruption (off) of the charging switches (SW1-7) 4a, 4b-4n. That is, at the time of discharging, the first sensing resistors 3a, 3b to 3n are bypassed to form a discharge path.

  In this case, the host CPU unit 9 detects a discharge current via the second sensing resistor 8, and information on the discharge current is obtained from the CPU units 2a, 1b, 1b of the battery blocks 1a, 1b to 1n. 2b to 2n are notified respectively. Then, in each of the CPU units 2a, 2b to 2n, the discharge amount is obtained by integrating the discharge current, and the remaining battery capacity (remaining charge capacity) is obtained by subtracting the discharge amount from the full charge capacity. Yes. When the remaining battery capacity decreases with discharge and reaches a preset remaining capacity, this is notified to the host CPU unit 9 as a discharge limit. Receiving this notification, the host CPU unit 9 shuts off (turns off) the discharge switches (SW10) 6a, 6b-6n, thereby stopping the discharge from the battery blocks 1a, 1b-1n all at once (collectively). Then, the discharge control ends.

  In the above description, the charging and discharging are controlled by alternative on / off control of the charging switches (SW1-7) 4a, 4b-4n and the discharging switches (SW10) 6a, 6b-6n. In the case where the CPU units 2a, 2b-2n respectively provided in the battery blocks 1a, 1b-1n have a function of individually controlling on / off charging and discharging, for example, The charging and discharging may be controlled as shown in FIGS.

  That is, FIG. 3 shows a schematic control procedure in the host CPU unit 9 and each CPU unit 4 (4a, 4b to 4n) during charging. In this case, in the host CPU unit 9, the above-described charging switches (SW1 to 7) 4a and 4b to 4n are turned on all at once, and a plurality of battery blocks 1a and 1b to 1n are connected in parallel to perform charging (not shown). Connect to the power source <Step S1>, and set the charge management mode for each CPU unit 4 <Step S2>. Then, the CPU unit 4 in each of the battery blocks 1a, 1b to 1n detects the charging current Ic from the first sensing resistor 3 (3a, 3b to 3n) in accordance with the setting of the charge management mode <step S3> Then, it is determined whether the secondary battery is fully charged from the change in the charging current Ic <step S4>. Then, when the secondary battery is fully charged, the charging is stopped <step S5>.

  On the other hand, the host CPU unit 9 collects information on the state of charge from the CPU units 4 of the battery blocks 1a, 1b to 1n <step S6>, and all the battery blocks 1a, 1b to 1n are fully charged. It is monitored whether or not the charging is stopped <Step S7>. When all the battery blocks 1a, 1b to 1n are fully charged, the above-described charging switches (SW1 to 7) 4a and 4b to 4n are respectively cut off (off) <step S8>, and the plurality of battery blocks 1a , 1b to 1n may be disconnected from a charging power source (not shown) to stop the charging control.

  On the other hand, at the time of discharging, as shown in FIG. 4, first, in the host CPU unit 9, the discharge switch 6 is turned on, and the plurality of battery blocks 1a, 1b to 1n are connected in series to a load (not shown). Connect <Step S11>, and set the discharge management mode for each CPU unit 4 <Step S12>. Then, the host CPU unit 9 detects the discharge current Idc from the second sensing resistor 8 inserted in series in the discharge path <step S13>, and the detected discharge current Idc is detected from the plurality of battery blocks 1a, 1b to Each CPU unit 4 of 1n is notified <step S14>. Thereafter, while collecting information on the discharge state from each CPU unit 4 <step S15>, it is determined whether there are any battery blocks 1a, 1b to 1n that have stopped discharging <step S16>. When all the battery blocks 1a, 1b to 1n are normally discharged, the procedure from the discharge current detection process shown in step S13 is repeatedly executed.

  However, if there are battery blocks 1a, 1b to 1n that have stopped discharging <Step S16>, the discharge switch 6 described above is shut off (turned off), and the plurality of battery blocks 1a, 1b to 1n are disconnected from the load all at once. The discharge is stopped <Step S17>, a discharge stop command is issued to each CPU unit 4, and the discharge control is terminated <Step S18>.

  On the other hand, each CPU unit 4 obtains the discharge current Idc notified from the host CPU unit 9 <step S20>, and integrates the discharge current Idc to discharge capacity (consumption capacity) from the secondary battery. <Step S21>. Then, the remaining capacity of the secondary battery in the battery block is obtained by subtracting the discharge capacity from the full charge capacity <step S22>. In addition, each CPU unit 4 determines whether or not the remaining battery capacity has decreased to a preset limit capacity (lower limit value) <step S23>. After confirming whether or not a discharge stop command is issued from the host CPU unit 9, <step S24>, the procedure from the discharge current Idc acquisition process shown in step S20 is repeated. On the other hand, when the remaining battery capacity is reduced to a preset limit capacity (lower limit value) <Step S23>, or when a discharge stop command is issued from the host CPU unit 9, <Step S24> At that time, the discharge from the secondary battery is stopped and the discharge control is stopped <step S25>.

  As described above, in the secondary battery device according to the present invention, at the time of charging, the plurality of battery blocks 1a, 1b to 1n are connected in parallel to charge the secondary batteries, and the battery blocks 1a, 1b to 1n are The charging of each battery block 1a, 1b-1n is controlled based on the charging current individually detected by one sensing resistor 3a, 3b-3n, and a plurality of battery blocks 1a, 1b-1n are connected in series at the time of discharging. And simultaneously discharging the battery and monitoring the remaining battery level for each of the battery blocks 1a, 1b to 1n based on the discharge current detected by the second sensing resistor 8, so that the discharge is controlled. Even when the battery blocks 1a, 1b to 1n are connected in series to obtain a high output voltage for a large power load, the charging and discharging can be controlled stably and reliably. The In particular, the discharge can be controlled without being affected by the first sensing resistors 3a, 3b to 3n provided for each of the plurality of battery blocks 1a, 1b to 1n, and the plurality of first sensing resistors 3a, 3b. Since there is no problem of voltage drop due to ˜3n, the practical advantage is great.

  By the way, as described above, when a secondary battery device is constructed by dividing a plurality of secondary batteries into a plurality of battery blocks 1a, 1b to 1n, each battery as shown in FIG. Each of the blocks 1a, 1b to 1n is housed in a box-shaped case 10 together with the CPU units 3a, 3b to 3n, etc. described above to form a battery pack (unit). It is desirable to arrange and use it detachably in a case (rack) 20. In this case, generally, waste heat cooling is performed in the housing 20 in a lump using the fan 21 incorporated in the housing (rack) 20, but the cooling efficiency between the plurality of battery packs BP is low. There is a concern that the temperature of the secondary battery may vary due to equilibrium.

  Accordingly, in order to prevent such a problem, the secondary battery unit BP, which is housed in the case 10 together with the CPU units 3a, 3b to 3n, etc. for each battery block 1a, 1b to 1n as described above, As shown in FIG. 5, it is desirable to incorporate a cooling fan 11 and manage the temperature of the secondary battery by individually cooling each secondary battery unit BP. Specifically, a cooling fan 11 is incorporated in the case 10 of each secondary battery unit (battery pack) BP, and a temperature sensor (for example, a thermistor) for detecting the temperature of the secondary battery is incorporated, and the above-described control of the CPU unit 4 is performed. The air volume of the cooling fan 11 may be controlled so that the battery temperature is constant below.

  If such a configuration is adopted, even if the thermal influence received from the surroundings differs depending on the storage position of the secondary battery unit (battery pack) BP in the housing 20, the individual secondary battery units ( Battery pack) Since it becomes possible to control the cooling fan 11 for each BP to keep the battery temperature at a preset constant temperature, it is possible to suppress variations in the battery temperature among a plurality of secondary battery units (battery packs) BP. can do. As a result, it is possible to sufficiently exhibit the battery performance in each secondary battery unit (battery pack) BP while suppressing changes in battery performance and variations in battery life due to differences in battery temperature. And discharge control can be performed with high reliability.

  Further, when the plurality of battery blocks 1a, 1b to 1n are respectively stored in the case 10 to form the battery pack BP in this way, the secondary battery BAT is suspended in the case 10 as shown in FIG. It is desirable to provide a gap 12 that forms an air layer around the secondary battery BAT. Specifically, the secondary battery BAT is supported in a suspended manner using a stay 13 fixed to the inside of the case 10, and a predetermined space (gap between the outer peripheral surface of the secondary battery BAT and the inner wall surface of the case 10 is provided. ) To form a support structure.

  With such a structure, even if a plurality of secondary battery units (battery packs) BP are arranged and stored in close contact with each other in the casing 20 described above, Since an air layer can be formed around the secondary battery BAT in the secondary battery unit (battery pack) BP, the air layer prevents intrusion of unintentional heat from the outside and allows air flow. Thus, heat generated from the secondary battery BAT can be effectively released to the outside. In particular, if the air around the secondary battery BAT is passed by the cooling fan 11 described above, the waste heat effect and cooling efficiency can be enhanced, and the stable operating environment of the secondary battery unit (battery pack) BP. Can be easily secured.

  FIG. 7 is a diagram showing a specific configuration of a secondary battery unit (battery pack) BP realized under the above-described considerations, where (a) is a plan view showing the internal structure, and (b) is an internal structure. (C) is a front view, (d) is a left side view, and (d) is a right side view. Here, FIG. 7C is described as the front surface of the secondary battery unit (battery pack) BP, but the direction of use in the housing (rack) 20 or the like is specified by this. It is not a thing.

  The secondary battery unit (battery pack) BP shown in FIG. 7 will be briefly described. The secondary battery unit (battery pack) BP includes a rectangular box-shaped lower case 10a and a cover that covers the lower case 10a. (Upper case) 10b is configured to house the secondary battery BAT having the battery block described above and the circuit board 15 on which the CPU unit 4 and the like are mounted. A substantially right half of the case 10 is used as a storage area A for the secondary battery BAT, and a substantially left half of the case 10 is used as a storage area B for the circuit board 15 described above. The storage area A has a size capable of storing, for example, secondary batteries BAT in which 36 cylindrical battery cells are arranged side by side in two rows and two rows and are alternately arranged in series. In particular, the storage area A is provided with a stay 13 for forming a predetermined gap between the periphery of the secondary battery BAT and the case 10 a, and supports the secondary battery BAT via the stay 13. Thus, the secondary battery BAT is housed in the case 10 in a suspended state.

  Further, a cooling fan 11 is provided at a position facing the secondary battery BAT on the right side surface portion of the lower case 10a, and the inside of the case 10 is provided through a plurality of slit holes 16 formed on the right side surface portion of the lower case 10a. Air is exhaled with heat. In particular, the air in the case 10 is discharged to the outside of the case 10 through the slit hole 16 while absorbing heat generated from the secondary battery ABT through a gap formed around the secondary battery BAT. . The secondary battery BAT is electrically connected to the circuit board 15 via a connector 16. The circuit board 15 is connected to the host CPU unit 9 via the connector 17.

  Thus, according to the secondary battery unit (battery pack) BP configured by housing the battery block and the circuit board 15 in the case 10, a plurality of secondary battery units (battery packs) BP are arranged in close contact with each other. Even in such a case, thermal interference between the secondary batteries BAT in each secondary battery unit (battery pack) BP can be suppressed. Therefore, the secondary battery BAT is kept at a constant temperature, and charging and discharging can be controlled easily and stably.

  The present invention is not limited to the embodiment described above. For example, the number of battery blocks 1a, 1b to 1n (the number of battery packs BP) set by dividing a plurality of secondary batteries may be determined according to the specifications of the device. It goes without saying that the number of secondary batteries constituting the blocks 1a, 1b to 1n may be determined according to the specifications. The charge switches 4a, 4b to 4n and the discharge switch 6 may be incorporated in the battery blocks 1a, 1b to 1n, respectively, but may be provided as external parts for the battery blocks 1a, 1b to 1n. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

The schematic block diagram of the secondary battery apparatus which concerns on one Embodiment of this invention. The figure which shows the equivalent circuit at the time of charge and discharge of the secondary battery apparatus which concerns on this invention. The figure which shows the example of the charge control procedure in the secondary battery apparatus which concerns on this invention. The figure which shows the example of the discharge control procedure in the secondary battery apparatus which concerns on this invention. The figure which shows the structural example when the some battery block in the secondary battery apparatus which concerns on this invention is unitized and accommodated in one housing | casing. The figure which shows the example of the suspended structure of the secondary battery in a battery block. The figure which shows the structural example of the battery block unitized.

Explanation of symbols

1a, 1b to 1n Battery block 2a, 2b to 2n CPU unit 3a, 3b to 3n First sensing resistor 4a, 4b to 4n Charge switch 5p, 5n Charge terminal 6a, 6b to 6n Discharge switch 7a, 7b Discharge terminal 8 2 Sensing resistance 9 Host CPU unit 10 Case of secondary battery unit (battery pack) 11 Cooling fan 20 Housing (frame)

Claims (4)

A secondary battery device comprising a plurality of secondary batteries,
Dividing the plurality of secondary batteries into a plurality of battery blocks, and incorporating a first sensing resistor for detecting a charging current for each battery block,
At the time of charging the plurality of secondary batteries, the plurality of battery blocks are connected in parallel, and the charging to the secondary battery is controlled based on the charging current detected for each battery block via the first sensing resistor,
On the other hand, when discharging a plurality of secondary batteries, the plurality of battery blocks are connected in series by bypassing the first sensing resistors in the plurality of battery blocks, and a discharge current is detected in a discharge path formed by these battery blocks. A secondary battery, wherein a second sensing resistor is inserted in series, and discharge from the plurality of secondary batteries is controlled based on a discharge current detected through the second sensing resistor. apparatus. Each of the battery blocks individually includes a CPU unit for charge / discharge management,
The charge / discharge control for the plurality of secondary batteries is performed by connecting the plurality of battery blocks in parallel under the control of a host CPU unit that communicates information with the CPU unit of each battery block. The secondary battery according to claim 1, wherein the CPU unit is set in a charge management mode, or the plurality of battery blocks are connected in series and the CPU unit of each battery block is set in a discharge management mode. Battery device.   The charging control for the plurality of secondary batteries is performed by controlling the charging of each battery block individually by detecting a full charge from a change in charging current detected via the first sensing resistor for each battery block. The secondary battery device according to claim 1, wherein when the secondary batteries of all the battery blocks reach full charge, the power supply to each of the battery blocks is stopped.   In the discharge control for the plurality of secondary batteries, each battery block is notified of a discharge current detected via the second sensing resistor, the remaining battery capacity is managed for each battery block, and the battery 2. The secondary battery device according to claim 1, wherein when a battery block whose remaining capacity reaches a lower limit is generated, discharge from all the battery blocks is collectively stopped.

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