JP2010154623A - Control circuit of dc-dc converter, dc-dc converter and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control circuit of a DC-DC converter which improve response characteristics, and also to provide the DC-DC converter and an electronic apparatus. <P>SOLUTION: An oscillator 20 frequency-divides a fundamental clock signal Ck of a first frequency via a frequency-dividing circuit 21, and outputs it to a digital circuit 22 as a frequency-divided clock signal Ckd of a second frequency. The oscillator 20 outputs a triangle waveform signal St of a first frequency synchronized with the fundamental clock signal Ck to an analog circuit 23. The digital circuit 22 makes PID-control in synchronization with the frequency-divided signal Ckd on the basis of an output voltage Vo. The analog circuit 23 controls the switching operation of a switching circuit 14 by making PWM-control on the basis of a control signal Sc and the triangle waveform signal St. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a DC-DC converter control circuit, a DC-DC converter, and an electronic device.

  Conventionally, DC-DC converters are mounted on various electronic devices. The DC-DC converter performs step-up conversion or step-down conversion on an input voltage to generate an output voltage of a desired voltage level, and supplies the output voltage to an electronic component (load) such as each semiconductor device in the electronic device as a power source. .

  As this type of DC-DC converter, there is known a digitally controlled DC-DC converter constituted by a digital circuit in which a control circuit of the DC-DC converter operates in synchronization with a clock signal.

  A digital control DC-DC converter controls a switching element on / off to increase / decrease an input voltage to generate a desired output voltage. In order to generate a desired output voltage, a PID (Proportional Integral Derivative) compensator, a DPWM (Digital Pulse Frequency Modulation) ). The digital control DC-DC converter determines whether the output voltage is held at a desired voltage level by the PID compensator and DPWM, and turns on the switching element so that the output voltage becomes a preset target voltage. The switching element is on / off controlled by setting the time / off time.

  In addition, the digital control DC-DC converter can set various settings such as a voltage level of a target voltage by external control such as a CPU. On the other hand, in the analog control DC-DC converter, adjustment is performed by an external component in order to set various settings such as the voltage level of the target voltage. Therefore, the digital control DC-DC converter can reduce the number of external components and save space compared to the analog control DC-DC converter.

However, the digital control DC-DC converter has a problem that the circuit scale is large and the current consumption is large as compared with the analog control DC-DC converter.
As a countermeasure for the above problem, conventionally, a digitally controlled DC-DC converter includes a PWM comparator circuit configured by an analog circuit instead of DPWM. The PWM comparator circuit operates based on a triangular wave signal having the same frequency synchronized with the clock signal. Thereby, the digital control DC-DC converter has reduced the circuit scale and reduced the current consumption by changing the DPWM to the PWM comparator circuit (for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-14234

  By the way, in the above digital control DC-DC converter, in order to set the output voltage to the target voltage, the PID compensator generates a control signal based on the difference voltage between the output voltage and the target voltage in synchronization with the clock signal. To do. Then, in the PWM comparator circuit, the ON time / OFF time of the switching element is set for each period of the triangular wave signal synchronized with the clock signal in accordance with the voltage level of the control signal.

  In other words, the digital control DC-DC converter synchronizes with the clock signal and the triangular wave signal, and controls the operation amount of the output voltage according to the difference voltage between the output voltage and the target voltage to bring the output voltage close to the target voltage. .

  By the way, the smaller the ratio (gain) of the manipulated variable of the output voltage to the difference voltage between the output voltage and the target voltage, the more stable the control system (feedback loop) in which the feedback control of the digitally controlled DC-DC converter is performed. The output voltage is stable and difficult to oscillate. However, when the output voltage changes sharply, the digitally controlled DC-DC converter does not operate normally, that is, the frequency band becomes narrow and the response characteristics deteriorate.

  On the contrary, as the ratio (gain) of the manipulated variable of the output voltage to the differential voltage between the output voltage and the target voltage is larger, the control system (feedback loop) in which the feedback control of the digital control DC-DC converter is performed becomes unstable. That is, the output voltage becomes unstable and is likely to oscillate. However, when the output voltage changes sharply, the digitally controlled DC-DC converter operates normally, that is, the frequency band is widened and the response characteristics are improved.

  Therefore, the digital control DC-DC converter is set to the ratio (gain) of the manipulated variable of the output voltage with respect to the differential voltage between the output voltage and the target voltage so that the response characteristic is improved while maintaining the stability of the output voltage. It was.

  The DC-DC converter control circuit, the DC-DC converter, and the electronic device are intended to improve response characteristics.

  The control circuit for the DC-DC converter is a control circuit for a DC-DC converter that generates an output voltage obtained by voltage-converting the input voltage by switching the switching circuit to intermittently supply the input voltage to the smoothing circuit. In synchronism with the clock signal of the first frequency, the output voltage value obtained by digital conversion of the output voltage is compared with the target output voltage value to calculate a difference value, and a control voltage value based on the difference value is calculated. A digital circuit to be calculated, the control voltage value is input in synchronization with a clock signal, the control voltage value is converted into a control voltage, and the control voltage and a triangular wave signal having a second frequency higher than the first frequency are obtained. An analog circuit for controlling the switching circuit with a drive signal having a duty ratio based on the comparison result is provided.

  According to the control circuit of the DC-DC converter, the digital circuit calculates the control voltage value in synchronization with the clock signal having the first frequency, and outputs the control voltage value to the analog circuit. The analog circuit converts the control voltage value input in synchronization with the clock signal of the first frequency into a control voltage, and converts the drive signal based on the control voltage and the triangular wave signal of the second frequency higher than the first frequency. Generate. The analog circuit controls the switching circuit with this drive signal.

  For this reason, while the digital circuit calculates the control voltage value once in synchronization with the clock signal, the analog circuit compares the calculated control voltage value with the triangular wave signal multiple times to generate a plurality of drive signals. Each time, the switching circuit is controlled. As a result, while the digital circuit calculates the control voltage value once, the analog circuit also generates the drive signal once to control the switching circuit, so that the control circuit of the DC-DC converter sets the output voltage to the target value. The response characteristics can be improved.

  The disclosed DC-DC converter control circuit, DC-DC converter, and electronic device can improve response characteristics.

Hereinafter, an embodiment will be described with reference to FIG.
A DC-DC converter 10 shown in FIG. 1 is a digitally controlled DC-DC converter, and generates an output voltage Vo supplied to a load Ro by stepping down an input voltage Vcc input from an input power supply B.

The DC-DC converter 10 includes a control circuit 11, a switching circuit 14, and a smoothing circuit 15.
The control circuit 11 performs duty control according to the load state of the load Ro to turn on / off the output transistor T1 of the switching circuit 14 and generate the switching voltage Vsw in the switching circuit 14. The switching voltage Vsw generated by the switching circuit 14 is smoothed by the smoothing circuit 15 including the choke coil L1 and the smoothing capacitor C1, and is output from the output terminal To to the load Ro as the output voltage Vo.

The control circuit 11 includes an oscillator 20, a frequency divider circuit 21, a digital unit 22, and an analog unit 23.
The oscillator 20 is configured by a known circuit, and generates a basic clock signal Ck and a triangular wave signal St having a frequency f1 as a second frequency. The basic clock signal Ck and the triangular wave signal St having the same period are output from the oscillator 20 in synchronization. Then, the oscillator 20 outputs the generated basic clock signal Ck to the frequency divider circuit 21 configured by a known binary counter.

  The frequency dividing circuit 21 divides the basic clock signal Ck having the frequency f1 by N, and outputs the divided clock signal Ckd having the frequency f2 (= f1 / N) as the first frequency to the digital unit 22. . In this frequency dividing circuit 21, the frequency dividing ratio N is changed from time to time by a digital frequency dividing signal DSv obtained by converting the frequency dividing ratio N from the digital unit 22 described later into a digital signal.

  On the other hand, the oscillator 20 outputs the generated triangular wave signal St having the frequency f <b> 1 to the analog unit 23. Therefore, while the frequency-divided circuit 21 outputs the frequency-divided clock signal Ckd having the frequency f2 (= f1 / N) and then outputs the frequency-divided clock signal Ckd, the triangular wave signal St for N cycles is analog from the oscillator 20. Is output to the unit 23.

The digital unit 22 includes an A / D converter 25, a comparator 26, and a PID compensator 27.
The A / D converter 25 receives the output voltage Vo and the frequency-divided clock signal Ckd having the frequency f2 from the frequency-dividing circuit 21. Each time the A / D converter 25 rises to the H level of the divided clock signal Ckd (in synchronization with the divided clock signal Ckd), the A / D converter 25 converts the output voltage Vo into a digital signal and outputs a digital output voltage as an output voltage value. The signal DVo is output to the comparator 26.

  The comparator 26 is a digital output voltage signal DVo input from the A / D converter 25 in synchronization with the divided clock signal Ckd, and a target output obtained by converting the target voltage Vk in which the output voltage Vo is preset into a digital signal. A digital target voltage signal DVk as a voltage value is input. The comparator 26 synchronizes the difference voltage as a difference value between the input digital output voltage signal DVo and the digital target voltage signal DVk to the PID compensator 27 as a digital error signal DSg in synchronization with the divided clock signal Ckd. Output.

  When the digital output voltage signal DVo matches the digital target voltage signal DVk, the comparator 26 outputs a digital error signal DSg obtained by converting the difference voltage of 0V into a digital signal. As the output voltage Vo becomes lower than the target voltage Vk, a digital error signal DSg obtained by converting a large negative difference voltage relative to the output voltage into a digital signal is output to the PID compensator 27. On the contrary, as the output voltage Vo becomes larger than the target voltage Vk, a digital error signal DSg obtained by converting a large positive difference voltage relative to the output voltage into a digital signal is output to the PID compensator 27.

  The PID compensator 27 receives the digital error signal DSg input from the comparator 26 in synchronization with the frequency-divided clock signal Ckd and the frequency-divided clock signal Ckd having the frequency f2 from the frequency-dividing circuit 21. The PID compensator 27 performs PID control on the input digital error signal DSg to generate a digital control signal DSc as a control voltage value, which is a digital signal, and outputs the digital control signal DSc to the analog unit 23. The PID compensator 27 changes the voltage level of the digital control signal DSc generated by the PID control each time the input divided clock signal Ckd rises to the H level (in synchronization with the divided clock signal Ckd). And output to the analog unit 23.

  In the PID control, first, a proportional operation for executing proportional control for suppressing the digital error signal DSg, second, an integration operation for executing integral control, and third, for executing differential control. The digital control signal DSc is generated from the three elements of the differential operation.

The proportional operation refers to an operation in which an operation amount Op of the output voltage Vo proportional to the digital error signal DSg is used.
The integration operation is the sum of the digital error signal DSg and the digital error signal DSg at the rise of the previous divided clock signal Ckd to H level, that is, the digital error signal DSg in the period of the divided clock signal Ckd. Is an operation in which the manipulated variable Oi of the output voltage Vo proportional to the integrated value is applied.

  The differential operation is obtained by subtracting the digital error signal DSg and the digital error signal DSg at the rise of the previous divided clock signal Ckd to H level, that is, the digital error signal DSg in the period of the divided clock signal Ckd. An operation in which the manipulated variable Od of the output voltage Vo proportional to the differentiated value is used.

The digital control signal DSc generated by the PID control is expressed by the following equation.
DSc = Op (t) + Oi (t) + Od (t)
Op (t) = Gp × Sg (t)
Oi (t) = Gi {Sg (t) + Sg (t-1)}
Od (t) = Gd {Sg (t) -Sg (t-1)}
Note that “Op (t)”, “Oi (t)”, and “Od (t)” indicate the operation amounts Op, Oi, and Od of proportional operation, integration operation, and differentiation operation, respectively. Further, “Si (t−1)” and “Sd (t−1)” respectively indicate the operation amount of the integral operation and the operation amount of the differential operation in the previous PID control. Further, “Gp”, “Gi”, and “Gd” indicate proportional coefficients Gp, Gi, and Gd of proportional operation, integral operation, and differential operation, respectively.

At this time, the frequency division ratio N of the frequency dividing circuit 21 is set based on the proportional coefficients Gp, Gi, Gd of the proportional operation, integral operation, and differential operation, and is expressed by the following equation.
N = 1 / (Gp + Gi + Gd)
“N” indicates the frequency division ratio N of the frequency divider circuit 21.

  That is, the PID compensator 27 calculates the frequency dividing ratio N of the frequency dividing circuit 21 from the above formula based on the proportional coefficients Gp, Gi, Gd of the set proportional operation, integral operation, and differential operation. Then, the PID compensator 27 outputs a digital frequency division signal DSv, which is a digital signal having the calculated frequency division ratio N, to the frequency division circuit 21. The frequency dividing circuit 21 receives the digital frequency dividing signal DSv and changes the frequency dividing ratio according to the inputted digital frequency dividing signal DSv.

  In this embodiment, the proportional coefficients Gp, Gi, and Gd of the proportional operation, the integral operation, and the differential operation are set to be 1 or less even when they are added. Further, in the PID control, the ratio between the target voltage Vk and the difference voltage (digital error signal DSg) between the output voltage Vo and the manipulated variable of the output voltage Vo for stabilizing the output voltage Vo and preventing the output voltage Vo from oscillating ( Gain). The manipulated variable of the output voltage Vo varies according to the digital control signal DSc.

  From the above, since the digital control signal DSc varies according to the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation, the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation are output. The voltage Vo is set to be a digital control signal DSc for preventing oscillation.

  That is, since the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation are not added to 1 or more so that the output voltage Vo does not oscillate, the division ratio N becomes 1 or more, and the PID compensator 27 The frequency-divided clock signal Ckd having a frequency f2 (= f1 / N) lower than the basic clock signal Ck having the frequency f1 is input.

  Further, the smaller the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation, that is, the more stable the feedback loop, the larger the frequency division ratio N. On the contrary, the proportional operation, the integral operation, the differential operation If the operation proportional coefficients Gp, Gi, Gd are increased, that is, the response characteristics are improved, the frequency division ratio N is decreased.

The PID compensator 27 outputs the generated digital control signal DSc to the analog unit 23.
In other words, the PID compensator 27 performs PID control on the digital error signal DSg input from the comparator 26 in synchronization with the divided clock signal Ckd, so that the output voltage Vo quickly matches the target voltage Vk. A signal DSc is generated and output to the analog unit 23.

The analog unit 23 includes a D / A converter 31, a PWM comparator circuit 32, and a drive circuit 33.
The D / A converter 31 receives the digital control signal DSc input from the PID compensator 27, performs D / A conversion on the digital control signal DSc, and outputs the control signal Sc as an analog signal as a PWM. Output to the comparator circuit 32.

  In the PWM comparator circuit 32, the triangular wave signal St of the frequency f1 is input from the oscillator 20 to the negative input terminal, and the control signal Sc is input from the D / A converter 31 to the positive input terminal. When the control signal Sc becomes equal to or greater than the triangular wave signal St in one cycle of the triangular wave signal St, the PWM comparator circuit 32 reverses the L level determination signal Sj, and conversely, the control signal Sc is smaller than the triangular wave signal St. When this happens, an H level determination signal Sj is output.

  That is, the higher the control signal Sc, the longer the time during which the control signal Sc is higher than the triangular wave signal St and the shorter the time during which the control signal Sc is lower than the triangular wave signal St in one cycle of the triangular wave signal St. Conversely, the lower the control signal Sc, the shorter the time during which the control signal Sc is higher than the triangular wave signal St and the longer the time during which the control signal Sc is lower than the triangular wave signal St in one cycle of the triangular wave signal St.

  That is, in the PWM comparator circuit 32, the higher the control signal Sc, the lower the duty ratio of the determination signal Sj in one cycle of the triangular wave signal St. Conversely, the lower the control signal Sc, the one cycle of the triangular wave signal St. Inside, the duty ratio of the determination signal Sj becomes high.

  In other words, the PWM comparator circuit 32 decreases the duty ratio of the determination signal Sj in one cycle of the triangular wave signal St as the output voltage Vo increases, and conversely, as the output voltage Vo decreases, the PWM comparator circuit 32 increases the 1 of the triangular wave signal St. During the period, the duty ratio of the determination signal Sj increases.

  More specifically, when the output voltage Vo is a value close to the target voltage Vk, in the present embodiment, the output voltage Vo is approximately an intermediate voltage of the amplitude voltage of the triangular wave signal St. As a result, the duty ratio of the determination signal Sj output from the PWM comparator circuit 32 is approximately 50%.

  Further, as the output voltage Vo becomes smaller than the target voltage Vk, the control signal Sc becomes lower than the middle of the amplitude voltage of the triangular wave signal St. As a result, the duty ratio of the determination signal Sj output from the PWM comparator circuit 32 is 50% or more.

  Furthermore, the control signal Sc becomes higher than the middle of the amplitude voltage of the triangular wave signal St as the output voltage Vo becomes higher than the target voltage Vk. As a result, the duty ratio of the determination signal Sj output from the PWM comparator circuit 32 is less than 50%.

The determination signal Sj of the PWM comparator circuit 32 whose duty ratio is changed based on the output voltage Vo is output to the drive circuit 33.
Meanwhile, the PWM comparator circuit 32 sets the duty ratio of the determination signal Sj based on the triangular wave signal St having a frequency f1 higher than the frequency f2 (= f1 / N) of the divided clock signal Ckd input to the PID compensator 27. is doing. That is, during one PID control in the PID compensator 27, the PWM comparator circuit 32 inputs a triangular wave signal St having a plurality of cycles (N cycles) and outputs a determination signal Sj each time.

  Therefore, since the switching circuit 14 switches a plurality of times (N times) during one PID control, the output voltage Vo is closer to the target voltage Vk than when the switching circuit 14 is switched once during one PID control. be able to.

  When the determination signal Sj is at L level, the drive circuit 33 outputs an L level drive signal Sd to the gate of the output transistor T1. On the other hand, when the determination signal Sj is at the H level, the drive signal Sd outputs the H level drive signal Sd to the gate of the output transistor T1. Therefore, the drive circuit 33 outputs the drive signal Sd having the same duty ratio as the determination signal Sj to the output transistor T1.

The switching circuit 14 includes an output transistor T1 and a diode D1.
The output transistor T1 is a P-channel MOS transistor, the drive signal Sd is input to the gate, and the input voltage Vcc is supplied to the source. The drain of the output transistor T1 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the ground. The connection point (node N1) between the output transistor T1 and the anode of the diode D1 is connected to the output terminal To (load Ro) via the choke coil L1 of the smoothing circuit 15.

  The connection point (node N1) between the output transistor T1 and the diode D1 is connected to the output terminal To via the choke coil L1. The output terminal To is connected to the ground via the smoothing capacitor C1. The smoothing capacitor C1 and the choke coil L1 constitute a smoothing circuit 15 that smoothes the switching voltage Vsw that is the potential of the node N1 and generates the output voltage Vo.

  When the switching circuit 14 receives an L level driving signal Sd from the driving circuit 33, the output transistor T1 is turned on. Conversely, when the H level driving signal Sd is input from the driving circuit 33, the output transistor T1 is turned off. To do. At this time, the diode D1 prevents the backflow of the output current Io from the output terminal To to the ground.

  Based on the on / off operation (duty control) of the output transistor T1, the switching circuit 14 generates the switching voltage Vsw from the input voltage Vcc and outputs the switching voltage Vsw to the smoothing circuit 15. That is, the switching circuit 14 outputs the switching voltage Vsw having the same duty ratio as that of the drive signal Sd to the smoothing circuit 15. The smoothing circuit 15 smoothes the input switching voltage Vsw to generate an output voltage Vo, and supplies the output voltage Vo to the load Ro via the output terminal To.

  That is, when the output voltage Vo actually supplied to the load Ro is equal to or lower than the target voltage Vk supplied to the preset load Ro, the drive circuit 33 outputs the drive signal Sd having a long L level time, The output transistor T1 is turned on, the output voltage Vo is increased so as to be the target voltage Vk, and supplied to the load Ro.

  On the contrary, when the output voltage Vo actually supplied to the load Ro is higher than the target voltage Vk supplied to the preset load Ro, the drive circuit 33 outputs the drive signal Sd having a long H level time. The output transistor T1 is turned off, the output voltage Vo is lowered so as to be the target voltage Vk, and supplied to the load Ro.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The PWM comparator circuit 32 inputs a triangular wave signal St having a frequency f1 higher than the frequency f2 (= f1 / N) of the divided clock signal Ckd input to the PID compensator 27, and based on the triangular wave signal St. A determination signal Sj is generated. That is, the PWM comparator circuit 32 generates the determination signal Sj generated in the triangular wave signal St having a plurality of cycles (N cycles) during one PID control in the PID compensator 27.

  For this reason, the DC-DC converter 10 can bring the output voltage Vo closer to the target voltage Vk than the conventional case where the PWM comparator circuit 32 inputs the triangular wave signal St having the same frequency f2 as the frequency-divided clock signal Ckd. The characteristics can be improved.

  (2) The PID compensator 27 calculates the frequency division ratio N of the frequency dividing circuit 21 from the above formula based on the proportional coefficients Gp, Gi, Gd of the set proportional operation, integral operation, and differential operation. Therefore, as the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation are set to smaller coefficients, that is, as the output voltage Vo becomes more stable, the frequency division ratio N increases and the triangular wave signal St The ratio of the frequency f1 of the divided clock signal Ckd to the frequency f2 is increased, and the response characteristics of the DC-DC converter 10 can be improved. Therefore, even if the proportional coefficients Gp, Gi, Gd of the proportional operation, the integral operation, and the differential operation are set to small coefficients, the deterioration of the response characteristics of the DC-DC converter 10 is complemented by the operation in the PWM comparator circuit 32. It has become.

In addition, you may implement the said embodiment in the following aspects.
In the embodiment described above, the basic clock signal Ck having the frequency f1 output from the oscillator 20 is divided by the frequency dividing circuit 21 to generate the divided clock signal Ckd having the frequency f2 (= f1 / N). Output to the unit 22.

  Not limited to this, as shown in FIG. 2, the basic clock signal Ck output from the oscillator 20 is set to the frequency f2, and the basic clock signal Ck is output to the PID compensator 27. Then, the triangular wave signal St having the frequency f2 (= f1 / N) may be converted to the multiplied triangular wave signal Stt having the frequency f1 via the multiplication circuit 40 and output to the PWM comparator circuit 32.

It is an electric block circuit diagram of the DC-DC converter of this embodiment. It is an electric block circuit diagram of the DC-DC converter of another example.

Explanation of symbols

10 DC-DC converter 11 Control circuit 14 Switching circuit 21 Dividing circuit 22 Digital circuit 23 Analog circuit 40 Multiplying circuit Ckd Divided clock signal Gp, Gi, Gd Proportional coefficient N Dividing ratio, Multiplying ratio St Triangular wave signal Vk Target voltage Vo Output voltage

Claims (5)

A control circuit for a DC-DC converter that performs a switching operation of a switching circuit to intermittently supply an input voltage to a smoothing circuit and generates an output voltage obtained by converting the input voltage into a voltage;
Digital that calculates a difference value by comparing an output voltage value obtained by digitally converting the output voltage with a target output voltage value in synchronization with a clock signal of the first frequency, and calculates a control voltage value based on the difference value Circuit,
The control voltage value is input in synchronization with a clock signal, the control voltage value is converted into a control voltage, and the control voltage is compared with a triangular wave signal having a second frequency higher than the first frequency. A control circuit for a DC-DC converter, comprising: an analog circuit that controls the switching circuit with a drive signal having a duty ratio based on the above. In the control circuit of the DC-DC converter according to claim 1,
An oscillator for synchronizing and outputting a basic clock signal having the same second frequency as the triangular wave signal having the second frequency;
A frequency dividing circuit that divides the basic clock signal of the second frequency to generate the clock signal of the first frequency;
The digital circuit calculates the control voltage value by performing a PID control operation in synchronization with the clock signal of the first frequency,
A control circuit for a DC-DC converter, wherein a reciprocal of a value obtained by adding a proportional coefficient, an integral coefficient, and a differential coefficient in the PID control is used as a frequency dividing ratio of the frequency dividing circuit. In the control circuit of the DC-DC converter according to claim 1,
An oscillator for outputting a triangular wave signal having the same first frequency as the first frequency of the clock signal in synchronization with the clock signal having the first frequency;
A multiplication circuit for multiplying the triangular wave signal of the first frequency to generate the triangular wave signal of the second frequency;
The digital circuit calculates the control voltage value by performing a PID control operation in synchronization with the clock signal of the first frequency,
A control circuit for a DC-DC converter, wherein a reciprocal of a value obtained by adding a proportional coefficient, an integral coefficient, and a differential coefficient in the PID control is used as a multiplication ratio of the multiplication circuit.   The DC-DC converter provided with the control circuit of the DC-DC converter as described in any one of Claims 1-3.   An electronic apparatus comprising the DC-DC converter according to claim 4.

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