JP2010154075A - Transcode display device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transcode display device and method for correctly displaying a progress situation of conversion. <P>SOLUTION: The transcode display device controls display of a progress situation of transcode processing in a transcoder which has a decoder, a memory, and an encoder, and is provided with: a display circuit for selecting decode frame data from each memory display frame selection range of the prescribed number of frames, reading the selected decode frame data, and using them for display; and a display circuit control unit for controlling a display circuit so as to select either decode frame data based on first encoding data obtained by bidirectional prediction coding or data code frame data based on the first coding obtained by in-picture prediction coding or unidirectional prediction coding for every display frame selection range. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transcode display apparatus and method for displaying the progress of transcoding.

  In recent years, digitization of image processing has become widespread. In order to reduce the amount of codes, digitized image data is encoded with MPEG2 or H.264. In many cases, transmission and recording are performed after encoding using a moving image encoding method (encoding method) such as H.264, AVC standard. Conversion between the encoding methods is performed by a transcoder.

  For example, H.M. H.264 has a higher compression rate than MPEG2. Therefore, an MPEG2 encoded image employed in broadcast media is converted to H.264. A transcoder that converts to an H.264 encoded image may be used.

  The conventional transcoder realizes the conversion process by decoding the encoded data of the first encoding method and encoding the decoded result by the second encoding method. In order to check the progress status of such conversion processing, there is one having a function of displaying a decoded moving image during conversion processing.

  However, the transcoder conversion process may be executed at a rate higher than the frame rate of the moving image. In this case, it is necessary to select and display images of some frames of the image to be converted. The order of frames to be decoded may be different from the order of frames to be displayed. Therefore, when displaying the image in the transcode, it is necessary to have a function of outputting the decoded moving image in the display order.

  In Patent Document 1, a technique for solving these problems is proposed. In Patent Document 1, only an I picture image is selected and displayed from among moving images in transcoding. Thereby, in the proposal of patent document 1, it is possible to display an image in an appropriate display order corresponding to a conversion process faster than a displayable frame rate.

  However, the insertion rate of I pictures is not fixed, and there are cases where many I pictures are included in the moving picture to be transcoded, or on the contrary. If the moving picture to be transcoded includes many I pictures, even if only the I pictures are selected in the proposal of Patent Document 1, the displayed image may exceed the displayable rate.

On the other hand, for a moving image including a small number of I-pictures, the proposal in Patent Document 1 does not update the display frame for a relatively long time, and the interval between the frame being transcoded and the frame to be displayed is increased. May not be displayed correctly. That is, the display frame rate varies depending on the data to be decoded, and the display frame rate is not guaranteed.
JP 2005-51287 A

  An object of the present invention is to provide a transcode display apparatus and method that can correctly display the progress of conversion.

  A transcode display device according to an aspect of the present invention decodes first encoded data of a first encoding method and outputs decoded frame data, and stores the decoded frame data in the decoding order of the decoder Transcoding processing in a transcoder having a memory and an encoder that reads out the decoded frame data stored in the memory and encodes the decoded frame data into second encoded data of a second encoding scheme different from the first encoding scheme A transcode display device for controlling display of the progress status of the selected frame, wherein the decode frame data is selected from the memory for each display frame selection range of a predetermined number of frames, and the selected decode frame data is read out for display. A display circuit to be used and the display frame selection range; Every time, the first encoded data obtained by intra-frame predictive encoding or unidirectional predictive encoding by the decoded frame data by bi-directional predictive decoding with respect to the first encoded data obtained by bi-directional predictive encoding And a display circuit control unit for controlling the display circuit so as to select the decoded frame data by intra-screen predictive decoding or unidirectional predictive decoding for data.

  A transcode display method according to an aspect of the present invention includes a decoder that decodes first encoded data of a first encoding method and outputs decoded frame data, and stores the decoded frame data in the decoding order of the decoder Transcoding processing in a transcoder having a memory and an encoder that reads out the decoded frame data stored in the memory and encodes the decoded frame data into second encoded data of a second encoding scheme different from the first encoding scheme A transcode display method for controlling the display of the progress status of the display, wherein the decoding frame data is selected from the memory for each display frame selection range of a predetermined number of frames, and both directions are included in the display frame selection range. The first encoded data obtained by predictive encoding. When the decoded frame data by bidirectional predictive decoding for is present, the decoded frame data obtained by the bidirectional predictive decoding in the display frame selection range is selected, and the display frame selection range is selected. When the decoded frame data by the bidirectional prediction decoding does not exist, the intra prediction decoding or the unidirectional prediction decoding for the first encoded data obtained by the intra prediction encoding or the unidirectional predictive encoding. A process of selecting the decoded frame data obtained by the second decoding from the last in the display frame selection range from the decoded frame data by the conversion, and reading the selected decoded frame data for display It is characterized by being output to.

  The transcode display method according to another aspect of the present invention includes a decoder that decodes first encoded data of a first encoding method and outputs decoded frame data, and the decoded frame data in the decoding order of the decoder. In a transcoder comprising: a memory for storing the decoded frame data; and an encoder for reading the decoded frame data stored in the memory and encoding the second encoded data in a second encoding scheme different from the first encoding scheme A transcode display method for controlling display of a progress status of transcode processing, wherein the decode frame data is selected from the memory for each display frame selection range of a predetermined number of frames, and the display frame selection range The decoded frame data at the selection determination position in If it is obtained by bi-directional predictive decoding on the first encoded data obtained by directional prediction encoding, the decoded frame data at the selection determination position is selected, and the selection determination position at the selection determination position When the decoded frame data is obtained by intra-frame predictive decoding or unidirectional predictive decoding with respect to the first encoded data obtained by intra-frame predictive encoding or unidirectional predictive encoding, A process of selecting the decoded frame data obtained by the intra prediction decoding or the unidirectional predictive decoding immediately before the decoding at the selection determination position is performed, and the selected decoded frame data is read and displayed. It is output for use.

  According to the present invention, the progress of conversion can be displayed correctly.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a transcoder incorporating a transcode display device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a specific configuration of the display circuit control unit 15 in FIG.

  First, the transcode display method employed in the present embodiment will be described with reference to FIGS.

  MPEG standard image data includes an I picture obtained by encoding using only the data in the screen, a P picture obtained by predictive encoding for the prediction error between the data in the screen and the data of the immediately preceding one screen, and the data in the screen. It consists of a B picture by predictive coding for the prediction error with the data of the next two screens. To create a P picture, it is necessary to refer to an I picture or another P picture, and to create a B picture, it is necessary to refer to an I or P picture. Note that the B picture is never referenced.

  Encoded digital image data (hereinafter referred to as a stream) is configured by appropriately arranging I, P, and B pictures. A normal I picture is arranged at the head of the stream. To decode a B picture, it is necessary to obtain decoded data of a P picture referred to by the target B picture before decoding the target B picture. For this reason, each picture is arranged in consideration of the decoding order in the stream. That is, in a stream including a B picture, the actual image order (display order) is different from the order of each picture in the stream.

  FIG. 3 is an explanatory diagram showing picture types for encoding an image, and FIG. 4 is an explanatory diagram for explaining the arrangement of pictures constituting a stream and display during transcoding.

  In FIG. 3, each frame indicates one frame image, I, P, and B in the frame indicate that the encoding picture type is I, P, and B picture, respectively, and the numbers indicate the display order. . The display order is the display order of each frame.

  Pictures I0, I1, I5, I6, and I8 are generated using the images of the 0th, 1st, 5th, 6th, and 8th frames, respectively. Pictures P4, P7, and P11 are generated using the first, sixth, and eighth frames, respectively, as reference images. Pictures B2 and B3 are generated using the first, fourth and fourth frames as reference images, and pictures B8 and B9 are generated using the eighth and tenth frames as reference images.

  Since it is necessary to decode the reference image first at the time of decoding, the picture that becomes the reference image is transmitted before the picture that uses the reference image. In the example of FIG. 3, the transmission order in the stream of each picture is as shown in the upper part of FIG. For example, when decoding the B2 and B3 pictures, the I1 and P4 pictures that have become reference images must be decoded first, and these pictures are first in the transmission order. At the time of decoding, decoding is performed in the order of transmission. That is, the decoding order matches the transmission order.

  In the present embodiment, in order to indicate the progress of transcoding, a predetermined frame is selected from the decoded frames and displayed. In such a transcode progress display, one frame is displayed for each predetermined number of frames (hereinafter referred to as a display frame selection range) in consideration of the fact that the transcode conversion speed is higher than the display rate. The frame is selected and displayed. By making the number of frames in the display frame selection range constant, display at a constant rate is possible.

  In addition, each frame in the transcode progress display needs to be displayed in an order corresponding to the actual image display order (hereinafter referred to as a normal order). In the present embodiment, frames to be selected from the display frame selection range are selected according to the following two criteria (1) and (2), and displayed in the order of selection, whereby each frame in the transcode progress display is displayed. The order of display is in the normal order.

(1) The latest B picture decoded last within the display frame selection range is selected.

  If only B pictures are viewed, the decoding order is the normal order. If B pictures are selected according to the decoding order, the display order of the frames in the transcode progress display is the normal order. Therefore, when there is a B picture within the display frame selection range, the last decoded B picture within the display frame selection range is always selected, and the selected B pictures are displayed in that order. As a result, for the B picture, the transcode progress display is in the normal order.

(2) When there is no B picture in the display frame selection range, the I and P pictures decoded second from the end in the display frame selection range are selected.

  When the frame images of I and P pictures become reference images of B pictures, these I and P pictures are transmitted ahead of the B pictures and decoded. That is, out of two I and P pictures decoded before a predetermined B picture, the picture preceding in the decoding order is the picture preceding the display order of the B picture, and the picture subsequent in the decoding order is the picture It is a picture that is later in the display order of the B picture.

  Therefore, when the B picture does not exist in the display frame selection range, if the second picture from the end in the decoding order within the display frame selection range is selected, the selected I and P pictures are always It is guaranteed that the picture is earlier in the display order than the B picture in the next display frame selection range.

  In the example of FIG. 4, the display frame selection range is indicated by a broken line. That is, the number of frames in the display frame selection range is three. The pictures I0, I1, and P4 in the first display frame selection range do not include a B picture. Therefore, the image (I1) of the first frame, which is the result of decoding of the picture I1, is selected by applying the above (2) within the display frame selection range. B pictures are included in pictures B2, B3, and I5 in the next display frame selection range. Therefore, the image (B3) of the third frame, which is the decoding result of the last picture B3, is selected by applying the above (1) within this display frame selection range. Similarly, from the next display frame selection range, the seventh frame image (P7) as a result of decoding of the picture P7 is selected, and from the last display frame selection range, the result of decoding of the picture B10 is selected. The tenth frame image (B10) is selected.

  That is, by applying the above criteria (1) and (2), the images of the first, third, seventh and tenth frames are displayed as the progress display of transcoding, and at a constant rate. It is possible to perform display with the display order as normal.

  In FIG. 1, the storage unit 2 stores encoded data of moving images encoded by the first encoding method. The transcoder 1 reads the encoded data from the storage unit 2, converts it into encoded data of the second encoding method, and outputs it to the storage unit 3. The storage unit 3 stores encoded data from the transcoder 1.

  The transcoder 1 according to the present embodiment includes a decoder 11 that decodes input encoded data, a frame memory 12 that stores a frame image of a decoding result by the decoder 11, and an encoder 13 that performs encoding using a new encoding method. And have.

  The control unit 14 controls the decoder 11 and the encoder 13 and controls writing and reading of the frame memory 12. The decoder 11 is controlled by the control unit 14 to decode the input encoded data, and provides frame image data (hereinafter referred to as decoded frame data) as a decoding result to the frame memory 12 for sequential storage. The encoder 13 is controlled by the control unit 14 and reads the decoded frame data stored in the frame memory 12 and encodes it by the second encoding method. In this case, the encoder 13 can read the decoded frame data obtained by the decoding process in the order of decoding and can encode it by the second encoding method.

  The control unit 14 has a display circuit control unit 15. The display circuit control unit 15 selects the decoded frame data decoded and stored in the frame memory 12 for each display frame selection range, and reads the selected decoded frame data from the frame memory 12 in the decoding order. I do. In this case, the display circuit control unit 15 selects a frame in accordance with the criteria (1) and (2).

  The control unit 14 controls the decoder 11 and obtains information on the picture type of the picture decoded in the decoder 11 and information on the end of decoding of each picture (decoding end notification). The control unit 14 also obtains address information (decoded frame address) of the frame memory 12 in which the decoded frame data from the decoder 11 is stored.

  In FIG. 2, the decoded picture type, the decoded frame address, and the decoding end notification are input to the display circuit control unit 15 from other parts of the control unit 14.

  A decoding end notification is input to the frame counter 21 of the display circuit control unit 15. The frame counter 21 counts up the decoding completion notification to count up each picture and outputs the count value to the frame counter determination unit 22. In the frame counter determination unit 22, information on the number of frames N in the display frame selection range is set. The frame counter determination unit 22 determines the count value of the frame counter 21 and resets the count value for each number of frames in the display frame selection range. As a result, the frame counter determination unit 22 obtains a position determination result within the display frame selection range indicating which position within the display frame selection range the decoded frame is, and outputs the result to the frame selection unit 23. .

  In the present embodiment, the frame counter determination unit 22 determines that it is the position determination result indicating that it is the last N frames of the display frame selection range and the last (N−1) frame immediately before. It is only necessary to output the position determination result shown.

  The decoded picture type is input to the frame selection unit 23. The frame selection unit 23 has a memory (not shown) that stores whether or not the B picture is included in the display frame selection range, and transcodes based on the decoded picture type and the position determination result in the display frame selection range. A write control signal for selecting a frame to be used for the progress display is output. The frame selection unit 23 outputs a write control signal to the next display frame address register 24. The next display frame address register 24 is given a decode frame address, and stores the decode frame address and outputs it to the display frame address register 25 in accordance with the write control signal.

  That is, the frame selection unit 23 performs write control to the next display frame address register 24 when it is indicated that the picture type of the frame decoded by the decoded picture type is B picture according to the criterion (1). A signal is given to always store the decode frame address. That is, for the B picture, the next display frame address register 24 always stores the decoded frame address of the last decoded frame.

  Further, according to the criterion (2), the frame selection unit 23, when the B frame is not included in the second to last frames within the predetermined display frame selection range, The decoded frame address of the P picture is stored in the next display frame address register 24. In this case, when the last frame within the predetermined display frame selection range is not a B picture, the frame selection unit 23 decodes the I and P picture decoded frames stored in the next display frame address register 24. The address is directly output to the display frame address register 25 and stored.

  The frame selector 23 controls the writing of the decoded frame address of the last frame in the display frame selection range, and then outputs the decoded frame address stored in the next display frame address register 24 to the display frame address register 25 for storage. Let The display frame address register 25 is controlled by the frame selector 23 and outputs the stored decoded frame address to the display circuit 4 as a display frame address. Thus, the display frame address conforms to the above criteria (1) and (2).

  The display circuit 4 reads out the decoded frame data stored in the frame memory 12 in accordance with the display frame address and displays it on a display (not shown).

  Next, the operation of the embodiment configured as described above will be described with reference to the flowchart of FIG.

  The encoded data of the first encoding method read from the storage unit 2 is supplied to the decoder 11. The decoder 11 is controlled by the control unit 14 to sequentially decode the encoded data and store the decoded frame data in the frame memory 12. The encoder 13 sequentially reads the decoded frame data stored in the frame memory 12, generates encoded data of the second encoding method, and outputs the encoded data to the storage unit 3.

  In order to display the progress of transcoding by the decoder 11 and the encoder 13, the picture type of the frame decoded by the decoder 11, the address of the decoded frame (decoded frame address) stored in the frame memory 12, and the decoding end notification of each picture Is supplied to the display circuit control unit 15 in the control unit 14.

  The frame selection unit 23 of the display circuit control unit 15 determines whether or not the picture type of the decoded frame is a B picture in step S1 of FIG. If it is a B picture, the frame selector 23 updates the decoded frame address stored in the next display frame address register 24 in step S2. As a result, the decoded frame address of the B picture decoded last is always written in the next display frame address register 24.

  When the frame selection unit 23 indicates in step S3 that the count value of the frame counter determination unit 22 has reached (N−1), that is, the second frame from the end in the display frame selection range. Determines whether or not the B picture has been included in the display frame selection range up to that point. If the B picture is not included, the frame selection unit 23 updates the decoded frame address stored in the next display frame address register 24 in step S4. As a result, the decoded frame address of the second I and P picture from the last in the display frame selection range is written in the next display frame address register 24.

  From the head of the display frame selection range to the (N-2) th frame, the next display frame address register 24 is updated in step S2, and the processing returns to step S1 by the determinations in steps S5 and S7. In the second (N−1) frame from the end of the display frame selection range, the next display frame address register 24 is updated in step S4, and the process returns to step S1 by the determination in step S7. When the last frame in the display frame selection range is decoded, the decoded frame address stored in the next display frame address register 24 is updated only when the last frame is a B picture (step S2).

  That is, in the next display frame address register 24, when there is no B picture within the display frame selection range, the decoded frame addresses of the I and P pictures decoded second from the last are stored, and the B picture exists. In this case, the decoded frame address of the last decoded B picture is stored.

  In the next step S5, when the frame selection unit 23 indicates that the counter number is N, that is, the last frame in the display frame selection range, the decoding stored in the next display frame address register 24 is performed in step S6. The frame address is given to and stored in the display frame address register 25, and the counter 21 is reset.

  The decoded frame address stored in the display frame address register 25 of the display circuit control unit 15 is supplied to the display circuit 4. The display circuit 4 reads the decoded frame data by designating the decoded frame address input to the frame memory 12 in accordance with the progress of transcoding. In this way, the decoding frame data is selected based on the above criteria (1) and (2). The display circuit 4 gives the read decoded frame data to a display (not shown) to display the progress of transcoding.

  As described above, in this embodiment, it is possible to display the progress of transcoding at a constant rate by selecting one frame of decoded image data for each display frame selection range of a predetermined number of frames. To. If the B picture exists in the display frame selection range, the latest decoded frame data of the B picture is selected. If the B picture does not exist, the second I and P pictures from the end of the display frame selection range are selected. select. As a result, the selected decode frame data is selected and displayed in the same normal order as the display order, and it is possible to correctly display the transcoding progress status for streams having a different decode order and display order. is there.

(Second Embodiment)
FIG. 6 is a block diagram showing a second embodiment of the present invention. In FIG. 6, the same components as those in FIG.

  This embodiment is different from the first embodiment in that an input I / F unit 31 is provided. The input I / F unit 31 can set the number of frames N in the display frame selection range in the display circuit control unit 15 ′ in accordance with a user input operation. The display circuit control unit 15 ′ is different from the display circuit control unit 15 only in that a display frame selection range is set by a user operation.

  In the embodiment configured as described above, the user can set the number of frames N in the display frame selection range. As a result, a moving image showing the progress of transcoding can be displayed at a frame rate that matches the user's preference.

(Third embodiment)
FIG. 7 is a block diagram showing a display control circuit employed in the third embodiment of the present invention.

  In the first embodiment, display at a constant rate is enabled by selecting one decode frame data for each display frame selection range. However, as is apparent from the comparison between the reproduced moving image sequence and the display frame shown in FIGS. 3 and 4, the interval between the selected frames is not constant, and the constant rate display is not performed in a short period. Therefore, in the present embodiment, display at a constant rate is made possible by selecting frames at regular time intervals. Also in the present embodiment, a display frame selection range of a predetermined number of frames is set, and a frame to be selected is determined for each display frame selection range. In the present embodiment, the frame to be displayed is determined for each display frame selection range, but the selected frame is not limited to be within the display frame selection range.

  FIG. 8 is an explanatory diagram for explaining a method of selecting a display frame in the present embodiment. In the first row of FIG. 8, each frame indicates one frame image, I, P, and B in the frame indicate that the picture type of encoding is I, P, and B picture, respectively. The image order is shown, and an example in which the same encoding as that in FIG. 3 is adopted is shown. The second row in FIG. 8 shows the arrangement of each picture constituting the stream generated by adopting the first-stage coding, and shows the same stream order (decoding order) as in FIG. The third row in FIG. 8 shows a playback moving image sequence obtained by decoding the second row stream and rearranging in the display order, and the fourth row in FIG. 8 shows a display frame selected in the present embodiment. Note that the third circle in FIG. 3 indicates the display frame to be selected.

  As shown in the first and second tiers of FIG. 8, on the stream, an I and P picture that is a forward reference picture and an I and P picture that is a backward reference picture are arranged before a B picture. Therefore, when the decoded frame is normally displayed, it is necessary to display the previously decoded backward reference image after displaying the later decoded B picture image.

  The third row in FIG. 8 shows an algorithm for converting such decoding order into normal display order. That is, the decoded frame data of the I and P pictures is held in the memory, and is output for display after the decoding of the next I and P pictures. The decoded frame data of the B picture is output as it is for display. Therefore, for the I and P pictures decoded after the B picture, the decoded frame data of the I and P pictures decoded before the B picture are output for display before the decoding output. Thus, the decoding order is converted to the display order.

  In the present embodiment, a display frame at a constant rate is obtained by using such a display order conversion algorithm at regular time intervals. That is, as shown in the fourth row of FIG. 8, a display frame selection range of a predetermined number of frames is set (in FIG. 8, the display frame selection range is 3 frames), and at a constant cycle defined by the display frame selection range. Select a display frame. For example, a predetermined frame position within the display frame selection range is set as a selection determination position (the last frame in FIG. 8), and when the selection determination position is a B picture, the B picture is selected, and when the selection determination position is an I or P picture Selects an I or P picture decoded immediately before the I or P picture at the selection determination position. As a result, a display frame in which the display order is the normal order is obtained at a constant period defined by the display frame selection range.

  In FIG. 7, the decoding end notification is input to the frame counter 36 of the display circuit control unit 35. The frame counter 36 counts up the decoding end notification, counts up for each picture decoding, and outputs the count value to the frame selection unit 37. In the frame selection unit 37, information on the number of frames N in the display frame selection range is set. The frame selection unit 37 determines the count value of the frame counter 36 and resets the count value of the frame counter 36 for each number of frames in the display frame selection range. Accordingly, the frame selection unit 37 obtains a position determination result indicating which position of the decoded frame is within the display frame selection range.

  The decoded frame address supplied to the display circuit control unit 35 is supplied to the next display frame address register 38 and the display frame address register 39. The next display frame address register 38 and the display frame address register 39 are controlled to be written and read by a write control signal from the frame selector 37 and store the decoded frame address.

  The decoded picture type is input to the frame selection unit 37. The frame selection unit 37 controls writing and reading of the next display frame address register 38 and the display frame address register 39 according to a predetermined position (selection determination position) within the display frame selection range, for example, the picture type of the last frame. .

  That is, when the frame at the selection determination position is a B picture, the frame selection unit 37 stores the decoded frame address in the display frame address register 39, and when the frame is an I or P picture, the frame selection unit 37 sets the decoded frame address to the next. The data is stored in the display frame address register 38. Then, when the frame at the selection determination position is an I or P picture, the frame selection unit 37 outputs the decoded frame address stored in the next display frame address register 38 to the display frame address register 39 for storage. .

  The frame selection unit 37 causes the display circuit 4 to output the decoded frame address held in the display frame address register 39 as a display frame address. That is, the frame selection unit 37 outputs the decoded frame address as it is for the B picture at the selection determination position, and outputs the decoding frame address of the immediately preceding I and P pictures for the I and P pictures at the selection determination position.

  Next, the operation of the embodiment configured as described above will be described with reference to the flowchart of FIG.

  In the present embodiment, the frame selection method by the display circuit control unit 35 is different from that of the first embodiment. The frame counter 36 of the display circuit control unit 35 outputs a count value indicating a position within the display frame selection range to the frame selection unit 37. In step S11 in FIG. 9, the frame selection unit 37 determines whether the picture type of the decoded frame is a B picture. If it is an I or P picture, the frame selector 37 updates the decoded frame address stored in the next display frame address register 38 in step S12. If it is a B picture, the frame selection unit 37 updates the decoded frame address stored in the display frame address register 39 in step S13.

  If the count value of the frame counter 36 reaches N in step S14, that is, if it is indicated that it is the last frame in the display frame selection range, the frame selection unit 37 determines that the picture type of the frame is It is determined whether or not the picture is a B picture (step S15). If the last frame is an I or P picture, the frame selector 37 displays the decoded frame address of the I or P picture decoded immediately before stored in the next display frame address register 38 in step S16. It is transferred to the frame address register 39 and stored. In step S17, the frame selection unit 37 outputs the decoded frame address stored in the display frame address register 39 as a display frame address.

  If the last frame is a B picture, the frame selector 37 outputs the decoded frame address of the B picture stored in the display frame address register 39 as a display frame address in step S13. In this way, the display frame shown in FIG. 8 is obtained.

  As described above, in the present embodiment, for each display frame selection range of a predetermined number of frames, a display frame is determined by using a display order conversion algorithm, so that a display frame is selected at a constant rate. It is possible to display the progress of transcoding in order.

(Fourth embodiment)
FIG. 10 is a block diagram showing a fourth embodiment of the present invention. In FIG. 10, the same components as those in FIG.

  This embodiment is different from the third embodiment in that an input I / F unit 31 is provided. The input I / F unit 31 can set the number of frames N in the display frame selection range in the display circuit control unit 35 ′ in accordance with a user input operation. The display circuit control unit 35 ′ is different from the display circuit control unit 35 only in that a display frame selection range is set by a user operation.

  In the embodiment configured as described above, the user can set the number of frames N in the display frame selection range. As a result, a moving image showing the progress of transcoding can be displayed at a frame rate that matches the user's preference.

(Fifth embodiment)
FIG. 11 is a block diagram showing a fifth embodiment of the present invention. In the second and fourth embodiments, the user sets the number of frames N in the display frame selection range. In the present embodiment, the number N of frames in the display frame selection range is automatically set.

  In FIG. 11, the display frame selection range determination unit 41 includes a decode counter 42, a timer 43, an integrator 44 and a register 45. The integrator 44 can be omitted as will be described later. The register 45 stores the number N of frames in the display frame selection range. Information on the number N of frames in the register 45 is set in the frame counter determination unit 22 in FIG. 2 and the frame selection unit 37 in FIG. 7 as the number of frames in the display frame selection range.

  First, in order to simplify the description, it is assumed that the integrator 44 is omitted and the output of the decode counter 42 is directly supplied to the register 45. It is assumed that the maximum frame rate that can be displayed by the display circuit 4 is β (fps (frame / second)). In this case, since the minimum time required for displaying one frame is 1 / β, in order to display the transcoded display frame reliably, the time t corresponding to the number N of frames in the display frame selection range is used. Needs to be 1 / β or more. This time t information is set in the register 43R in the timer 43. The timer 43 outputs a reset signal to the decode counter 42 at every time t set in the register 43R and also outputs a write control signal for writing to the register 45.

  The decode counter 42 counts the decode end notification, holds the count value c in the register 42R, and outputs it. The decode counter 42 is reset by a reset signal from the timer 43, and counts up for each decoding of each picture. Therefore, the count value c of the decode counter 42 indicates the number of frames decoded at time t.

  Since the time t is set to be longer than the minimum time necessary for displaying one frame by the display circuit 4, the number of frames given by the count value c is reliably determined by the display circuit 4 for one decoded frame. It is guaranteed that it can be displayed. By storing the count value c of the decode counter 42 in the register 45 by the write control signal for each time t from the timer 43, the register 45 displays the display frame selection range necessary for reliably displaying the decoded frame. The count value c is held as the number of frames N. The register 45 outputs the stored information N (= c).

The above description is for the case where the integrator 44 is omitted, that is, when the coefficient m of the integrator 44 is 1. In this case, the relationship between the time t and the maximum frame rate β that can be displayed by the display circuit 4 is:
t ≧ (1 / β) (seconds)
It becomes. For example, when β = 30 (fps), t ≧ 1/30 (second), and at least 1/30 (second) is required to determine the number N of frames. An integrator 44 is provided to shorten this time.

  That is, the integrator 44 multiplies the count value c from the decode counter 42 by m and outputs the result to the register 45. Accordingly, the time t ′ required for the count value c to be held in the register 45 is t ′ = t / m. From t ≧ 1 / β, mt′β ≧ 1. That is, a time t ′ that is 1 / m of a time t corresponding to the number N of frames in the display frame selection range may be set in the register 43R of the timer 43. Therefore, if m> 1, the time t ′ required to determine the number N of frames can be shortened as compared with the case where the accumulator 44 is omitted.

  Note that if the unit of t ′ is milliseconds, mt′β ≧ 1000, and if the unit of t ′ is a clock cycle, mt′β ≧ clock frequency.

  In the embodiment configured as described above, the number of frames N in the display frame selection range can be automatically set according to the frame rate that can be displayed by the display circuit. As a result, regardless of the data to be decoded, it is possible to guarantee the display frame rate and to reliably display a moving image indicating the progress of transcoding.

  Also, by setting a value close to 1 / β (or 1 / mβ) as time t (or t ′), the difference between the transcode progress display and the actual transcode progress can be reduced. .

  In each of the above embodiments, the same operation as that of the display circuit control units 15 and 35 can be realized by software processing by causing a computer to execute software for realizing the flow of FIG. 5 or FIG.

1 is a block diagram showing a transcoder incorporating a transcode display device according to an embodiment of the present invention. The block diagram which shows the specific structure of the display circuit control part 15 in FIG. Explanatory drawing which shows the picture type of the encoding with respect to an image. Explanatory drawing for demonstrating arrangement | positioning of each picture which comprises a stream, and the display in the middle of transcoding. The flowchart for demonstrating operation | movement of 1st Embodiment. The block diagram which shows the 2nd Embodiment of this invention. The block diagram which shows the display control circuit employ | adopted in the 3rd Embodiment of this invention. Explanatory drawing for demonstrating the selection method of the display frame in 3rd Embodiment. The flowchart for demonstrating operation | movement of 3rd Embodiment. The block diagram which shows the 4th Embodiment of this invention. The block diagram which shows the 5th Embodiment of this invention.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Transcoder, 4 ... Display circuit, 11 ... Decoder, 12 ... Frame memory, 13 ... Encoder, 14 ... Control part, 15 ... Display circuit control part.

Claims (5)

A decoder for decoding first encoded data of the first encoding method and outputting decoded frame data; a memory for storing the decoded frame data in the decoding order of the decoder; and the decoded frame data stored in the memory A transcode display device for controlling the display of the progress status of transcoding processing in a transcoder having an encoder that reads out and encodes into second encoded data of a second encoding scheme different from the first encoding scheme There,
A display circuit that selects the decode frame data from the memory for each display frame selection range of a predetermined number of frames, reads the selected decode frame data, and uses it for display;
For each display frame selection range, the decoded frame data obtained by bidirectional predictive decoding with respect to the first encoded data obtained by bidirectional predictive encoding, or obtained by intra prediction encoding or unidirectional predictive encoding. A transcode display, comprising: a display circuit control unit that controls the display circuit so as to select the decoded frame data by intra prediction decoding or unidirectional predictive decoding with respect to the first encoded data. apparatus. The display circuit control unit, when the decoded frame data by the bidirectional predictive decoding is present in the display frame selection range, is obtained by the last bidirectional predictive decoding in the display frame selection range. When decoding frame data is selected and the decoded frame data by the bidirectional predictive decoding does not exist within the display frame selection range, the decoded frame data by the intra prediction decoding or the unidirectional predictive decoding 2. The transcode display according to claim 1, wherein the display circuit is controlled so as to select the decoded frame data obtained by the second decoding from the last in the display frame selection range. apparatus. The display circuit control unit selects the decoded frame data at the selection determination position when the decoded frame data at the selection determination position within the display frame selection range is obtained by the bidirectional predictive decoding. When the decoded frame data at the selection determination position is obtained by the intra prediction decoding or the unidirectional prediction decoding, the decoding unit immediately before the decoding at the selection determination position The transcode display device according to claim 1, wherein the display circuit is controlled so as to select the decoded frame data obtained by intra prediction decoding or the unidirectional predictive decoding. A decoder for decoding first encoded data of the first encoding method and outputting decoded frame data; a memory for storing the decoded frame data in the decoding order of the decoder; and the decoded frame data stored in the memory A transcode display method for controlling the display of the progress status of transcode processing in a transcoder having an encoder that reads out and encodes into second encoded data of a second encoding scheme different from the first encoding scheme There,
A process of selecting the decoded frame data from the memory for each display frame selection range of a predetermined number of frames, the bidirectional direction for the first encoded data obtained by bidirectional predictive encoding within the display frame selection range When the decoded frame data by predictive decoding is present, the decoded frame data obtained by the bi-directional predictive decoding at the end of the display frame selection range is selected, and the bidirectional direction is within the display frame selection range. When the decoded frame data by predictive decoding does not exist, by intra prediction decoding or unidirectional predictive decoding for the first encoded data obtained by intra prediction encoding or unidirectional predictive encoding Among the decoded frame data, the second from the end in the display frame selection range It performs a process of selecting the decoding frame data obtained by the decoding of
A transcode display method, wherein the selected decoded frame data is read and output for display. A decoder for decoding first encoded data of the first encoding method and outputting decoded frame data; a memory for storing the decoded frame data in the decoding order of the decoder; and the decoded frame data stored in the memory A transcode display method for controlling the display of the progress status of transcode processing in a transcoder having an encoder that reads out and encodes into second encoded data of a second encoding scheme different from the first encoding scheme There,
A process of selecting the decoded frame data from the memory for each display frame selection range of a predetermined number of frames, wherein the decoded frame data at a selection determination position within the display frame selection range is obtained by bidirectional predictive encoding When it is obtained by bidirectional predictive decoding for the first encoded data, the decoded frame data at the selection determination position is selected, and the decoded frame data at the selection determination position is selected as an intra-frame prediction code. If the first encoded data obtained by encoding or unidirectional predictive encoding is obtained by intra-screen predictive decoding or unidirectional predictive decoding, the decoding at the selection determination position is performed. The decoded frame data obtained by the previous intra-screen predictive decoding or the one-way predictive decoding. It performs a process of selecting the data,
A transcode display method, wherein the selected decoded frame data is read and output for display.

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