JP2010151866A - Display device, method of manufacturing display device, thin film transistor substrate and method of manufacturing thin film transistor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device superior in display characteristics in which uneven brightness between light emitting devices is prevented while capacity of a capacitive element is secured, and to provide a method of manufacturing it. <P>SOLUTION: The display device has a thin film transistor substrate 1a in which pixel circuits comprising a thin-film transistor Tr2 and a capacitive element Cs are arranged in the linewidth direction of a gate electrode 14b of the thin-film transistor Tr. The thin-film transistor Tr2 is composed by disposing a semiconductor thin-film 32A on the gate electrode 14b through a gate dielectric film. The gate electrode 14b, in particular, is patterned to a predetermined linewidth. The capacitive element Cs is composed by disposing an upper electrode 22c over a lower electrode 21c that extends from the gate electrode 14b via the gate dielectric film. The lower electrodes 21c, in particular, are disposed spaced from the gate electrode 14b when they are adjacent to each other in the linewidth direction of the gate electrode 14b. The upper electrode 22c is provided as a continuous pattern using the same layer as the source electrode 22s or the drain electrode 22d. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device and a manufacturing method of the display device, and a thin film transistor substrate and a manufacturing method of the thin film transistor substrate, and more particularly, an active matrix driving display device including an organic electroluminescent element, a manufacturing method thereof, and a display device suitable for this display device. The present invention relates to a thin film transistor substrate used and a method for manufacturing the thin film transistor substrate.

  In an active matrix driving display device in which an organic electroluminescent element and a pixel circuit connected thereto are arranged on a substrate, an organic electric field is generated depending on a current amount of a thin film transistor (TFT) constituting the pixel circuit. The luminance of the light emitting element is determined. The pixel circuit that determines the amount of current to be supplied to the organic electroluminescent element includes at least a TFT that samples the video signal, a capacitor that holds the video signal, and a driving TFT that drives the organic electroluminescent element based on the held video signal. Three elements are required, and the layout density of the pixel circuit is higher than that of the liquid crystal element.

  Therefore, by adopting a so-called mirror inversion structure in which the layout of the pixel circuits arranged adjacent to each other in the scanning line direction on the substrate is inverted, one power supply line is shared by the two pixel circuits and the layout density is lowered. A configuration has been proposed (see Patent Documents 1 to 5 below).

  FIG. 15 shows a layout diagram of a thin film transistor substrate for a display device having such a mirror inversion structure. As shown in this figure, scanning lines 11 and power supply lines 12 are wired in parallel within the display area on the substrate 10, and signal lines 13 are wired perpendicularly thereto. Then, corresponding to each intersection of the scanning line 11 and the power supply line 12 and the signal line 13, each sub-pixel a (R) corresponding to three colors of red (R), green (G), and blue (B). ), A (G), and a (B) are arranged in this order. These sub-pixels a (R), a (G), and a (B) constitute a substantially square display pixel A having a set of three colors.

  In each color sub-pixel a, a pixel circuit including thin film transistors Tr1 and Tr2 'and a capacitive element Cs is arranged. Each thin film transistor Tr1 and Tr2 'includes gate electrodes 14a and 14b' extending in parallel with the signal line 13. Of these, the gate electrode 14b 'of one thin film transistor Tr2' is formed integrally with the lower electrode 21c of the capacitive element Cs. The thin film transistor Tr2 'has a configuration in which one power supply line 12 portion is shared on the drain side between adjacent sub-pixels a. Each of the sub-pixels a has a configuration in which an organic electroluminescence element (not shown) is connected to the thin film transistor Tr2 '.

  Further, as described above, in a display device in which the luminance of the organic electroluminescent element is determined by the amount of current of the thin film transistor that constitutes the pixel circuit, in order to perform good display with reduced luminance unevenness, the variation in characteristics of the thin film transistor is suppressed. This is very important.

  However, when the channel region of the thin film transistor is formed of polycrystalline silicon, transistor characteristics are likely to vary because the size of crystal grains present in the channel region is not uniform. Therefore, as a method of microcrystallizing the semiconductor thin film constituting the channel region to such an extent that the crystal grain size is not nonuniform, crystallization annealing is performed in which the amorphous thin film is microcrystallized using a solid-state laser. Yes.

  Here, when the thin film transistor substrate having the mirror inversion structure described with reference to FIG. 15 is manufactured, such a crystallization annealing step is performed, for example, as follows. First, as shown in FIG. 16, after forming gate electrodes 14a and 14b ′ composed of a first electrode pattern (21), a lower electrode 21c and other electrodes on a substrate 10, these first electrode patterns are formed. A gate insulating film and an amorphous semiconductor thin film are formed while covering (21). Next, after a buffer layer and a photothermal conversion layer are formed on the semiconductor thin film as necessary, the semiconductor thin film is irradiated with laser light generated from the solid laser through these layers. As a result, the semiconductor thin film portion 32A corresponding to the laser light irradiated portion is microcrystallized. At this time, the scanning direction (v) of the laser beam is the direction along the scanning line 11, that is, the channel length direction of the thin film transistors Tr1 and Tr2 'and the line width direction of the gate electrodes 14a and 14b'.

Patent No. 4036235 JP 2005-266830 A JP 2006-11429 A JP 2006-343768 A JP 2008-33091 A

  However, the crystallization annealing of the semiconductor thin film using the solid-state laser described above has a longer thermal diffusion length when the amount of heat necessary for crystallization of the semiconductor thin film is supplied than the crystallization annealing using the excimer laser. . For this reason, the influence of heat conduction by the gate electrode provided in the lower layer of the semiconductor thin film is remarkable, and the arrangement state of the gate electrode affects the crystallinity of the semiconductor thin film portion constituting the thin film transistor.

  That is, as described above, when the direction along the scanning line 11 shown in FIG. 15, that is, the line width direction (channel length direction) of the gate electrodes 14a and 14b ′ is the scanning direction (v) of the laser light, The gate electrodes 14a and 14b ′ are less likely to be thermally saturated on the upstream side, and the gate electrodes 14a and 14b ′ are likely to be thermally saturated on the downstream side in the scanning direction (v) of the laser beam.

  Therefore, on the upstream side in the laser beam scanning direction (v) across the gate electrodes 14a and 14b ′, the semiconductor thin film is crystallized before the gate electrodes 14a and 14b ′ are sufficiently heated by the laser beam irradiation. Therefore, the crystallinity becomes sparse. In contrast, the semiconductor thin film is crystallized on the downstream side in the scanning direction (v) of the laser beam with the gate electrodes 14a and 14b 'interposed therebetween, while the gate electrode is sufficiently heated by the laser beam irradiation. , The crystallinity becomes dense. That is, in the driving transistors Tr2 ′ of a (R) and a (B) in the left pixel A and the a (G) in the right pixel A in FIG. It is. On the other hand, in the a (G) in the left pixel A and the driving transistors Tr2 ′ in the a (R) and a (B) in the right pixel A in FIG. become. Such a crystalline density in the channel length direction in the channel region greatly affects the on-current of the thin film transistor.

  Therefore, if the layout of the adjacent subpixels a is mirror-inverted, the thin film transistor Tr1 of the subpixel a [for example, the subpixel a (G)] of the same color between the display pixels A adjacent in the scanning line 11 direction. , Tr2 ′ layout is inverted. For this reason, in the thin film transistors Tr1 and Tr2 'between the sub-pixels a of the same color, there is a difference in transistor characteristics, for example, on-current due to the above-described crystalline density at the ends in the channel length direction. Thereby, in the sub-pixel a of the same color between the adjacent display pixels A, a luminance difference is generated in the light emitting elements connected to the thin film transistors Tr1 and Tr2 ′. As a result, the luminance difference between the display pixels A adjacent in the scanning line 11 direction. However, it is visually recognized as luminance unevenness in the scanning line 11 direction.

  Therefore, the present invention can make the on-state current of the thin film transistor uniform without depending on the layout of the pixel circuit, and thereby a display device with good display characteristics in which uneven luminance of the light emitting element connected to the thin film transistor is prevented. It is another object of the present invention to provide a method for manufacturing such a display device.

  In order to achieve such an object, the display device of the present invention is a pixel circuit provided with a thin film transistor and a capacitor element arranged in the line width direction of the gate electrode of the thin film transistor, and is configured as follows. Yes. The thin film transistor is configured by providing a semiconductor thin film on a gate electrode through a gate insulating film. In particular, the gate electrode is patterned to a predetermined line width. The capacitive element is configured by providing an upper electrode on the lower electrode extending from the gate electrode via the gate insulating film. In particular, the lower electrode is disposed apart from the gate electrode in a state of being adjacent to the gate electrode in the line width direction. The upper electrode is provided as a continuous pattern using the same layer as the source or drain electrode.

  The present invention is also a thin film transistor substrate in which a circuit including the thin film transistor and the capacitor having the above-described configuration is arranged.

  In the display device and the thin film transistor substrate having such a structure, the gate electrode of the thin film transistor is provided apart from the lower electrode of the capacitor element in the line width direction and is patterned with a predetermined line width. For this reason, it is possible to prevent variation in crystallinity between the source side and the drain side in the semiconductor thin film, which is caused by the non-uniformity of the gate electrode in the lower layer of the semiconductor thin film between the source side and the drain side. . In addition, since the lower electrode is extended adjacent to the line width direction of the gate electrode, a large area can be maintained, and a capacitance in a capacitive element configured using the lower electrode can be ensured. Therefore, the light-emitting element connected to the thin film transistor having a uniform on-state current and the capacitor element having a large capacity can be driven without depending on the layout direction of the thin film transistor and the capacitor element.

  The manufacturing method of the display device of the present invention performs the following steps. First, an electrode pattern including a gate electrode having a predetermined line width and a lower electrode extending from the gate electrode and spaced apart from the gate electrode in the line width direction of the gate electrode An array is formed in the line width direction. Next, a gate insulating film and an amorphous semiconductor thin film are formed in this order so as to cover the arrayed electrode pattern. Next, the semiconductor thin film is crystallized by irradiating while scanning energy lines in the line width direction of the gate electrode. Thereafter, a thin film transistor is formed by connecting a source electrode and a drain electrode to a semiconductor thin film crystallized on the gate electrode. Further, the capacitor element is formed by providing the upper electrode on the lower electrode as a continuous pattern made of the same layer as the source electrode or the drain electrode.

  In addition, this invention is also a manufacturing method of the thin-film transistor substrate which performs the above processes.

  By the manufacturing method as described above, the display device and the thin film transistor substrate having the above-described configuration can be obtained. Particularly in this manufacturing method, the semiconductor thin film constituting the thin film transistor is crystallized by scanning the energy line along the line width direction of the gate electrode. For this reason, in the thin film transistors constituting the pixel circuit provided along the arrangement direction, the thin film transistors that are irradiated with the energy rays with the source side as the upstream and the thin film transistors that are irradiated with the energy rays with the drain side as the upstream are alternately arranged. Will be placed. However, in the display device having the above-described configuration according to the present invention obtained by this method, the gate electrode of the thin film transistor is provided to be separated from the lower electrode of the capacitor element in the line width direction, and is patterned with a predetermined line width. For this reason, at the time of crystallization, the gate electrode under the semiconductor thin film affects the source side and the drain side equally. Therefore, variation in crystallinity between the source side and the drain side in the semiconductor thin film caused by the shape of the lower gate electrode can be prevented.

  As described above, according to the present invention, even when a thin film transistor is configured using a semiconductor thin film crystallized by scanning an energy beam, the on-current of the thin film transistor can be made uniform without depending on the layout direction. can do. Further, the light emitting element connected to the thin film transistor and the capacitor having a large capacity can be driven. Accordingly, it is possible to obtain a display device with favorable display characteristics in which unevenness in luminance of the light emitting element is prevented. Furthermore, since the on-state current of the thin film transistor can be made uniform without depending on the layout direction, the energy beam can be scanned back and forth in the layout direction. As a result, it is possible to shorten the crystallization annealing process of the semiconductor thin film.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments in which the present invention is applied to an active matrix display device in which an organic electroluminescent element is connected to a thin film transistor and a thin film transistor substrate used in the display device will be described in detail below with reference to the drawings. In addition, the same code | symbol is attached | subjected and demonstrated to the component same as the conventional structure demonstrated using FIG.

<Overall configuration of display device>
FIG. 1 is a plan view showing the overall configuration of the display device 1 of the first embodiment.

  As shown in this figure, the display device 1 includes a display panel 2 and flexible printed boards 3, 4 and 5 connected to the peripheral edge. The flexible printed boards 3, 4, and 5 are, for example, a video signal supply board 3, a power supply board 4, and a scanning signal and power control signal supply board 5.

  The display panel 2 has a planar rectangular shape, and a display area 2a that is substantially similar to the display panel 2 is set at the center thereof. In the display area 2a, scanning lines 11 and power supply lines 12 are wired along the long side direction x of the display area 2a, and signal lines 13 are wired perpendicularly thereto. Sub-pixels a are arranged corresponding to the intersections of the scanning lines 11 and the power supply lines 12 and the signal lines 13. Signals are input to the scanning lines 11 and the power supply lines 12 from the substrate 5 for supplying scanning signals and power supply control signals. A signal is input to the signal line 13 from the video signal supply substrate 3. In addition, a signal is input from the power supply substrate 4 to an electrode common to all the pixels at the cathode (or anode) of the organic electroluminescence element described later.

  Each of the sub-pixels a has a rectangular shape and is arranged with its long side parallel to the signal line 13. Further, these sub-pixels a constitute a substantially square display pixel A in which three sub-pixels a arranged in the direction of the scanning line 11 are set as one set.

  Here, three sub-pixels constituting each display pixel A are three sub-pixels a (R), a (G), and a (B) of red (R), green (G), and blue (B). Suppose that there is. The sub-pixel a constituting the display pixel A is not limited to this, and four pixels in which sub-pixels for displaying white (W) are added in the direction of the scanning line 11 may be used.

  The three sub-pixels constituting each display pixel A are arranged in a mirror inversion structure in which the direction of the signal line 13 is the target line and the layout is alternately inverted in the direction of the scanning line 11. Thereby, one power supply line can be shared by two pixel circuits, and the layout density can be lowered.

  In the display area 2a, a display pixel A in which the three sub-pixels a (R), a (G), and a (B) (represented as a representative) are arranged in the direction of the scanning line 11 as described above, They are arranged in a matrix along the scanning line 11 and power supply line 12 direction, and further along the signal line 13 direction.

<Circuit configuration of display device>
FIG. 2 shows a circuit configuration diagram of a display area in the display device 1.

  As shown in this figure, a switching thin film transistor Tr1, a driving thin film transistor Tr2, and a capacitive element Cs are arranged in each sub-pixel a, and a pixel circuit is constituted by these. The thin film transistors Tr1 and Tr2 are n-channel MOS transistors here.

  Each pixel circuit is connected to the light emitting elements EL (R), EL (G), and EL (B) of the respective emission colors in the source S of the driving thin film transistor Tr2. In such a pixel circuit, the video signal written from the signal line 13 through the switching thin film transistor Tr1 selected by the scanning line 11 is held in the holding capacitor Cs. Then, a current corresponding to the signal amount held in the holding capacitor Cs is supplied from the source S of the driving thin film transistor Tr2 to each light emitting element EL (R), EL (G), EL (B). Accordingly, each light emitting element EL (R), EL (G), EL (B) emits light with a luminance corresponding to the supplied current value.

<Configuration of Thin Film Transistor Substrate Used for Display Device>
FIG. 3 is a layout diagram of a thin film transistor substrate having a pixel circuit provided in each subpixel a in the display device as described above. Here, a layout diagram corresponding to two display pixel A portions adjacent in the direction of the scanning line 11 is shown. 4 shows an enlarged view of the main part in FIG. 3, and FIG. 5 shows a cross-sectional view of the main part of the display device corresponding to the AA ′ cross section in FIGS.

  As shown in these drawings, a pixel circuit including thin film transistors Tr1 and Tr2 and a capacitor element Cs is disposed in each subpixel a on the glass substrate 10 constituting the thin film transistor substrate 1a.

  Among these, the thin film transistors Tr1 and Tr2 have a bottom gate structure, and include gate electrodes 14a and 14b made of a first electrode pattern (21) provided immediately above the glass substrate 10. Each of the gate electrodes 14a and 14b is patterned to have a predetermined line width W substantially equal to the channel length of the thin film transistors Tr1 and Tr2. On these gate electrodes 14a and 14b, a semiconductor thin film 32A constituting a channel region is provided via a gate insulating film 31. The semiconductor thin film 32A is patterned in a shape covering the gate electrodes 14a and 14b for each of the thin film transistors Tr1 and Tr2. On such a semiconductor thin film 32A, an etching stopper layer 33 and a source S (34) and a drain D (34) made of a semiconductor layer 34 containing impurities are disposed. Then, in a state of being connected to the source S / drain D, the source electrode 22s and the drain electrode 22d made of the second electrode pattern (22) are patterned. In the drawing, the gate electrode 14b is patterned to have a predetermined line width in a part of the driving thin film transistor Tr2. However, the gate electrode 14b has a predetermined line width throughout the gate line width direction. It is preferable that it is patterned.

  The capacitive element Cs is formed integrally with the source S side of the driving thin film transistor Tr2 connected to the light emitting element, and includes a lower electrode 21c composed of the first electrode pattern (21) and a second electrode pattern (22). The gate insulating film 31 is sandwiched between the upper electrode 22c and the upper electrode 22c.

  In particular, the lower electrode 21c extends from the gate electrode 14b of the driving thin film transistor Tr2 and is formed in the same layer as the gate electrode 14b. The lower electrode 21c extends to a position adjacent to the gate electrode 14b in the line width direction, and is disposed apart from the gate electrode 14b at the adjacent position. The upper electrode 22c is provided as a continuous pattern using the same layer as the source electrode 22s of the driving thin film transistor Tr2. The upper electrode 22c may be continuously formed integrally with the source electrode 22s of the driving thin film transistor Tr2 even on the portion where the lower electrode 21c and the gate electrode 14b of the driving thin film transistor Tr2 are separated from each other. .

  The pixel circuits provided in each subpixel a using the thin film transistors Tr1 and Tr2 and the capacitive element Cs as described above are arranged in the line width direction of the gate electrodes 14a and 14b. The thin film transistors Tr1 and Tr2 are arranged with their channel length directions parallel to the scanning lines 11. As a result, the thin film transistors Tr1 and Tr2 are in a state in which the source S and the drain D are sequentially arranged in the direction of the scanning line 11.

  The sub-pixels a are also arranged in the direction of the signal line 13, and a pixel circuit having the same configuration is also provided in the sub-pixels a. In the direction of the signal line 13, the pixel circuits may be arranged in the same layout direction, or may be arranged by mirror-inversion with the direction of the power supply line 12 as the target line while sharing the power supply line 12. Thereby, one power supply line can be shared by two pixel circuits adjacent in the direction of the signal line 13, and the layout density can be lowered.

  In such a state, each subpixel a is arranged in a mirror inversion structure in which the layout is alternately inverted in the scanning line 11 direction with the signal line 13 direction as the target line as described above. Accordingly, in the pixel circuit constituting each sub-pixel a, the sources S and drains D of the thin film transistors Tr1 and Tr2 are sequentially laid out along the arrangement direction in a state where the arrangement directions are alternately inverted. Become.

  Further, in the driving thin film transistor Tr2 in the pixel circuit arranged adjacently, one power supply line 12 portion extended from the power supply line 12 is shared as a common drain electrode 22d. Thereby, the layout density of the pixel circuit can be suppressed. The adjacent sub-pixels a are laid out with respect to the power line 12 portion.

  Further, in the pixel circuit provided in each sub-pixel a, the channel width of the thin film transistors Tr1 and Tr2 and the layout area of the capacitive element Cs are adjusted for each emission color of the light emitting element connected to the pixel circuit. I will do it.

  In general, an organic electroluminescent element (light emitting element) has a different luminous efficiency for each emission color. For this reason, it is assumed that the channel width of the thin film transistors Tr1 and Tr2 and the layout area of the capacitor Cs in the pixel circuit are set larger for the sub-pixel a provided with a light emitting element having a relatively low emission efficiency. As an example, here, the channel width of the thin film transistors Tr1 and Tr2 and the layout area of the capacitive element Cs increase in the order of red subpixel a (R) <green subpixel a (G) <blue subpixel a (B). It is assumed that the pixel circuit is designed so that

  Here, the thin film transistors Tr1 and Tr2 have the bottom gate structure as described above, and the semiconductor thin film 32A formed on the gate electrodes 14a and 14b is microcrystalline having been crystallized by irradiation with energy rays. Suppose that it is a thin film transistor. At this time, the scanning direction v of the laser beam irradiated as the energy beam is an arrangement direction of the source S and the drain D in the thin film transistors Tr1 and Tr2, that is, a direction along the scanning line 11, and the line width of the gate electrodes 14a and 14b. Direction.

<Cross sectional configuration of the display device>
On the thin film transistor substrate 1a configured as described above, a light emitting element is provided in the following state.

  A thin film transistor substrate 1a having a pixel circuit including thin film transistors Tr1 and Tr2 is covered with a passivation film 51, and a planarization insulating film 52 is further provided thereon. A light emitting element EL is provided on the planarization insulating film 52 at a position corresponding to each subpixel a.

  Each light emitting element EL includes a lower electrode 53 patterned for each sub-pixel a, a light emitting functional layer 54 made of an organic material provided on the upper electrode 55, and an upper electrode 55 provided on the light emitting functional layer 54. ing.

  Of these, the lower electrode 53 is used as an anode (or a cathode). The light-emitting functional layer 54 includes at least an organic light-emitting layer. For example, a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and the like are stacked as necessary from the anode side. Yes. The light emitting functional layer 54 has a different configuration for each light emitting color of each light emitting element EL. The upper electrode 55 is used as a cathode (or an anode) of the organic electroluminescence element EL, and is provided as an electrode common to all pixels.

  The light emitting element EL having the above configuration is separated by an insulating pattern 56 covering the periphery of the lower electrode 53. Each light emitting element EL is configured to be connected to the source S of the driving thin film transistor Tr2 in the lower electrode 53 through a connection hole (not shown). An auxiliary electrode 53a composed of the same layer as the lower electrode 53 is provided on the planarization insulating film 52. By connecting the auxiliary electrode 53a to the upper electrode 55, a voltage drop in the upper electrode 55 is prevented. It is preferable that it is the structure to perform.

  Although illustration is omitted here, it is preferable that the light-emitting element EL having the above-described configuration is sealed by a counter substrate bonded with an adhesive sealant. In this case, the counter substrate may be bonded to the formation surface side of the light emitting element EL in the thin film transistor substrate 1a with an adhesive.

  In the display device 1 and the thin film transistor substrate 1a used in the display device 1 having such a configuration, the gate electrode 14b of the driving thin film transistor Tr2 is provided apart from the lower electrode 21c of the capacitive element Cs in the line width direction. Patterned with a predetermined line width. For this reason, the variation in crystallinity between the source side and the drain side in the semiconductor thin film 32A, which is caused by the non-uniformity of the gate electrode 14b under the semiconductor thin film 32a between the source side and the drain side, is prevented. be able to.

  Therefore, even when the semiconductor thin film 32A crystallized by laser annealing, which will be described in detail in the next manufacturing method, is used, it is caused by the arrangement direction of the source S / drain D, which is a problem particularly in the mirror inversion structure. The uneven brightness of the same color is prevented. Note that the current characteristics of the driving transistor Tr2 connected to the light emitting element EL, particularly in a state of being integrally formed with the capacitor element Cs, are important in preventing luminance unevenness of the light emitting element EL of the same color. In the conventional configuration, uneven brightness of vertical stripes extending in the direction of the signal line 13 occurs due to the variation in current characteristics of the driving transistor Tr2.

  In addition, the lower electrode 21c of the capacitive element Cs extends to a position adjacent to the line width direction of the gate electrode 14b of the driving thin film transistor Tr2, and the upper electrode 22c is continuous with the source electrode 22s of the thin film transistor Tr2. It is formed in a certain amount. For this reason, the area of the capacitive element Cs can be maintained sufficiently large, and the capacity of the capacitive element Cs can be ensured. Therefore, the light emitting element EL connected to the thin film transistor Tr2 having a uniform on-current and the capacitor element Cs having a large capacity can be driven without depending on the layout direction of the thin film transistor Tr2 and the capacitor element Cs. It becomes possible.

  Therefore, even with the mirror inversion structure, it is possible to perform display with good display characteristics with high luminance and prevention of luminance unevenness of the light emitting element without depending on the layout direction. Note that the gate electrode 14a of the switching thin film transistor Tr1 is also patterned to have a predetermined line width approximately equal to the channel length. For this reason, also in this thin film transistor Tr1, the crystal of the source side and the drain side in the semiconductor thin film 32A generated due to the non-uniformity of the gate electrode 14a below the semiconductor thin film 32a on the source side and the drain side. Variation in sex can be prevented. Thereby, variation in characteristics of the thin film transistor Tr1 is also suppressed.

<Method for Manufacturing Thin Film Transistor Substrate and Display Device>
Next, a method for manufacturing the thin film transistor substrate having the above-described configuration and a method for manufacturing the display device will be described.

  First, as shown in FIG. 6, a flat rectangular glass substrate 10 is prepared. And the formation area of the two display panels 2 is set with respect to this glass substrate 10, for example. At this time, the short side of the display panel 2 is arranged in parallel to the long side of the glass substrate 10 so that the two display panels 2 can be efficiently arranged on the single glass substrate 10. In each display panel 2, a display area 2a having a substantially rectangular shape and a plane rectangular shape is set.

  Further, a sub-pixel a having a planar rectangular shape is set in the display area 2a. These subpixels a are arranged with the long sides of the subpixels a parallel to the short side direction y of the display region 2a. Furthermore, these sub-pixels a constitute a substantially square display pixel A in which three sub-pixels a of red (R), green (G), and blue (B) arranged in the short side direction are set as one set. This is as described above.

  Next, as shown in the plan view of FIG. 7 and the sectional view of FIG. 8A (corresponding to the AA ′ sectional view of the plan view of FIG. 7), Gate electrodes 14a and 14b and a lower electrode 21c made of the first electrode pattern (21) are formed. In the same process, another wiring portion made of the first electrode pattern (21), for example, a part of the signal line 13 is formed.

  At this time, the gate electrode 14a of the thin film transistor (Tr1) and the gate electrode 14b of the thin film transistor (Tr2) have a predetermined line width approximately equal to the channel length and extend in parallel to the short side direction y of the display region 2a. Patterned. The lower electrode 21c extends from the gate electrode 14b of the driving thin film transistor (Tr2) and extends to a position adjacent to the line width direction of the gate electrode 14b. In the adjacent position, the gate electrode 14b is extended. Patterning so as to be spaced apart from each other. Further, a part of the signal line 13 is patterned so as to be parallel to the short side direction y of the display region 2a. The first electrode patterns (21) constituting the gate electrodes 14a and 14b and the lower electrode 21c are arranged in the line width direction of the gate electrodes 14a and 14b (long side direction x of the display region 2a). A plurality of rows are also formed in the short side direction y of the display area 2a.

  The first electrode pattern (21) including the gate electrodes 14a and 14b and the lower electrode 21c is formed by pattern etching a molybdenum (Mo) film formed by sputtering, for example, using the resist pattern as a mask. To do. The first electrode pattern (21) is not necessarily made of molybdenum (Mo), but may be any metal having a high melting point that hardly changes in quality in the subsequent heat process.

  Next, in a state of covering these first electrode patterns (21), a gate insulating film 31 using, for example, silicon oxide or silicon nitride is formed, and then a semiconductor thin film 32 made of amorphous silicon is formed. To do.

  Thereafter, as shown in FIG. 8B, a buffer layer 41 using silicon oxide or silicon nitride is formed in a state of covering the semiconductor thin film 32, and then a photothermal conversion layer using molybdenum (Mo). 42 is deposited. The photothermal conversion layer 42 is for absorbing energy rays such as laser light, which will be described later, and converting the light energy into heat energy. Therefore, the photothermal conversion layer 42 has a high absorption rate of laser light (energy rays) used in the subsequent crystallization annealing, a low thermal diffusion rate to the buffer layer 41 and the semiconductor thin film 32, Any material may be used as long as it satisfies the conditions such as a material having a high melting point that is not easily altered by heat generated during subsequent crystallization. For example, carbon (C) is used. May be.

  After the above, as shown in the plan view of FIG. 7 and FIG. 8 (3), the semiconductor thin film 32 is indirectly irradiated with the laser light Lh via the photothermal conversion layer 42 and the buffer layer 41. Heat treatment is performed. At this time, the laser beam Lh using a solid laser as a transmission source is irradiated. As a result, the irradiated portion of the semiconductor thin film 32 with the laser light Lh is a semiconductor thin film (microcrystalline silicon thin film) 32A crystallized into nanometer order crystal grains.

  In this case, the laser beam Lh is irradiated while scanning the laser beam Lh in the line width direction of the gate electrodes 14a and 14b. At this time, a plurality of rows of gate electrodes 14a and 14b arranged in the line width direction are scanned with the laser light Lh along the line width direction. Thereby, the scanning direction v of the laser beam is parallel to the long side direction x of the display region 2a, that is, parallel to the short side of the glass substrate 10 as shown in FIG. Thereby, the energy variation of the laser beam Lh due to the long scanning distance of the laser beam is prevented, and a more uniform crystal can be obtained.

  Further, here, the laser beam Lh is applied so that the plurality of gate electrodes 14a and 14b arranged in the line width direction have a scanning direction (v) reciprocating between the columns and a reverse scanning direction (−v). To scan. Thereby, it is possible to shorten the crystallization annealing process of the semiconductor thin film 32 by this laser beam Lh irradiation. Note that such irradiation with the laser beam Lh may be performed by a multi-head method in which the laser beam Lh can be irradiated to a plurality of row portions at a time. Further, the method is not limited to the method in which the laser beam Lh is scanned in a reciprocating manner, and so-called raster scanning in which scanning is performed only in one direction may be used.

  Note that the irradiation width of the laser beam Lh in the direction perpendicular to the scanning direction (± v) only needs to cover the formation portions of the transistors (Tr1) and (Tr2). The irradiation with the laser beam Lh here is performed only on the portions corresponding to the formation positions of the thin film transistors (Tr1) and (Tr2) arranged and formed as described with reference to FIG. 3, that is, on the gate electrodes 14a and 14b. What is necessary is just to selectively irradiate the area including the upper part.

  After the laser beam Lh irradiation as described above, as shown in FIG. 8 (4), the photothermal conversion layer 42 and the buffer layer 41 on the semiconductor thin film 32A are removed by etching.

  Next, as shown in FIG. 9A, an insulating stopper layer 33 is formed on the semiconductor thin film 32A at a position overlapping the gate electrodes 14a and 14b on the semiconductor thin film 32A portion serving as a channel region. .

  Next, as shown in FIG. 9B, an n-type semiconductor layer 34 made of, for example, silicon containing an n-type impurity is formed in a state of covering the stopper layer 33.

  Thereafter, as shown in FIG. 9 (3), the n-type semiconductor layer 34 and the semiconductor thin film 32A are patterned in an island shape above the gate electrodes 14a and 14b.

  Thereafter, as shown in FIG. 9 (4), by forming a metal film covering the n-type semiconductor layer 34 and patterning it, the source electrode 22s and the drain electrode 22d made of the second electrode pattern (22) are formed. Further, the upper electrode 22c is formed. Further, in the same process, another wiring portion made of the second electrode pattern (22), for example, the scanning line 11, the power supply line 12, and a part of the signal line 13 shown in FIG.

  At this time, the source electrode 22 s / drain electrode 22 d are patterned in a state of being divided on the stopper layer 33. Further, the n-type semiconductor layer 34 is also patterned so as to be separated on the stopper layer 33, and the source S / drain D composed of the n-type semiconductor layer 34 is formed. Thereby, a channel region is formed by the microcrystalline semiconductor thin film 32A, and thin film transistors Tr1 and Tr2 in which the source electrode 22s / drain electrode 22d are connected to the source S / drain D in contact with the channel region are obtained.

  The upper electrode 22c is formed at a position overlapping the lower electrode 21c. As a result, a capacitive element Cs is obtained in which the gate insulating film 31 is sandwiched between the lower electrode 21c and the upper electrode 22c. As described above, the upper electrode 22c is a source electrode of the driving thin film transistor (Tr2) even on the part where the lower electrode 21c and the gate electrode 14b of the driving thin film transistor (Tr2) are separated from each other. It is formed as a continuous pattern continuously formed integrally with 22s.

  As described above, as shown in FIG. 3, the scanning line 11, the power supply line 12, and the signal line 13 are formed on the glass substrate 10, and the thin film transistors Tr1 and Tr2 and the capacitive element Cs are formed in each subpixel a. A thin film transistor substrate 1a having a circuit is obtained. In the formation of each pixel circuit, wirings are formed so that the sources S and drains D of the thin film transistors Tr1 and Tr2 are alternately inverted in the line width direction of the gate electrodes 14a and 14b.

  Next, a light emitting element is formed over the thin film transistor substrate manufactured as described above. This process will be described with reference to FIG.

  First, the passivation film 51 is formed so as to cover the thin film transistor substrate 1a including the above pixel circuit (only the thin film transistor Tr2 and the capacitor element Cs are shown), and the planarization insulating film 52 is formed thereon. Next, a connection hole (not shown) that reaches one of the source electrode 22s / drain electrode 22d (for example, the source electrode 22s) of the thin film transistor Tr2 is formed in the planarization insulating film 52 and the passivation film 51. Next, the lower electrode 53 connected to the source electrode 22 s and the source S through the connection hole is patterned on the planarization insulating film 52. In the same process, the auxiliary wiring 53a is formed.

  Next, an insulating pattern 56 having a shape in which the central portion of the lower electrode 53 is widely exposed to cover the periphery and a part of the auxiliary wiring 53a is exposed is formed. In the insulating pattern 56, an opening portion where the lower electrode 53 is exposed becomes a pixel opening.

  Thereafter, the light emitting functional layer 54 formed using an organic material is formed in a state of covering the lower electrode 53 exposed from the insulating pattern 56. The light emitting functional layer 54 is individually formed in a different process for each light emission color of the light emitting element formed here. However, the material layers that can be used in common may be continuously formed in the same process. Next, the upper electrode 55 common to all the pixels is formed in a state of covering the light emitting functional layer 54 and being connected to the auxiliary wiring 53a.

  As described above, the light emitting element EL of each color light emission is formed on the planarization insulating film 52 by sandwiching the light emitting functional layer 54 including the organic light emitting layer between the lower electrode 53 and the upper electrode 55. These light emitting elements EL have a configuration in which the lower electrode 53 is connected to the thin film transistor Tr2.

  After the above, although illustration is omitted here, the counter substrate is disposed on the light emitting element EL forming surface side of the glass substrate 10, and the glass substrate 10 and the counter substrate are bonded via an adhesive sealant. And if it is a case where the formation area of the some display panel 2 is set to one glass substrate 10 as shown in FIG. 6, the glass substrate 10 and a counter substrate will be divided | segmented for every display panel 2, A flexible printed circuit board is connected to each divided portion according to a predetermined procedure as necessary, thereby completing the display device 1.

  By the manufacturing method of the first embodiment described above, the display device 1 in which the pixel circuits are arranged in the mirror inversion structure as described with reference to FIGS. 1 to 5 can be obtained.

  In particular, in this manufacturing method, during the crystallization annealing of the semiconductor thin film 32 constituting the channel regions of the thin film transistors Tr1 and Tr2, as shown in FIGS. 3 and 6, the line width direction of the gate electrodes 14a and 14b (scanning) The laser beam is scanned along the direction of the line 11). For this reason, the thin film transistors Tr1 and Tr2 constituting the pixel circuits arranged in the mirror inversion structure along the arrangement direction have the source side upstream and the laser light Lh irradiated, and the drain side upstream and the laser light Lh. Are irradiated alternately.

  However, in the display device 1 obtained by the manufacturing method described above, the gate electrode 14b of the thin film transistor Tr2 that has a great influence on the luminance of the light emitting element EL is provided apart from the lower electrode 21c of the capacitor element Cs in the line width direction. , And patterned with a predetermined line width. For this reason, the influence of the thermal diffusion of the gate electrode 14b when the laser beam Lh is irradiated in the crystallization annealing equally affects the source side and the drain side of the semiconductor thin film 32. Therefore, variation in crystallinity between the source side and the drain side in the semiconductor thin film 32 can be prevented. A driving transistor Tr2 having uniform current characteristics can be obtained even if a pixel circuit whose layout is inverted is provided in a subpixel of the same color provided in the display pixel A adjacent in the scanning direction of the laser beam Lh. Can do. In particular, the current characteristics of the driving transistor Tr2 that is integrally formed with the capacitor Cs and connected to the light emitting element EL is important in preventing luminance unevenness of the light emitting element EL of the same color.

  As a result, it is possible to obtain the thin film transistor substrate 1a that can drive the light emitting element EL without luminance unevenness without depending on the layout direction even with the mirror inversion structure. It is possible to obtain the display device 1 that performs good display.

  In the embodiment described above, the thin film transistor substrate 1a in which the pixel circuit is arranged in the mirror inversion structure and the display device provided with the same are exemplified. However, the present invention includes a circuit in which the gate electrode of the thin film transistor and the lower electrode of the capacitor element are continuously formed, and the source electrode of the thin film transistor is integrally formed with the drain electrode and the upper electrode of the capacitor element. Widely applicable to configurations.

<Application example>
Display devices obtained by the manufacturing method according to the present invention described above include various electronic devices shown in FIGS. 10 to 14, such as digital cameras, notebook personal computers, mobile terminal devices such as mobile phones, video cameras, etc. The present invention can be applied to display devices of electronic devices in various fields that display video signals input to electronic devices or video signals generated in electronic devices as images or videos. An example of an electronic device to which the present invention is applied will be described below.

  FIG. 10 is a perspective view showing a television to which the present invention is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101.

  11A and 11B are diagrams showing a digital camera to which the present invention is applied. FIG. 11A is a perspective view seen from the front side, and FIG. 11B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 12 is a perspective view showing a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like. It is produced by using.

  FIG. 13 is a perspective view showing a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using such a display device.

  FIG. 14 is a diagram showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an open state, (B) is a side view thereof, and (C) is in a closed state. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. And the sub display 145 is manufactured by using the display device according to the present invention.

It is a top view which shows the whole structure of the display apparatus of embodiment. It is a circuit block diagram of the display apparatus of embodiment. It is a block diagram of the thin-film transistor substrate in the display apparatus of embodiment. It is a principal part enlarged view of FIG. FIG. 5 is a main part cross-sectional view of the display device corresponding to the A-A ′ cross-sectional view of FIG. 4. It is a board | substrate block diagram for demonstrating the manufacturing process of the display apparatus of this invention. It is a principal part plane process drawing for demonstrating a part of manufacturing process of embodiment. FIG. 6 is a cross-sectional process diagram (No. 1) for describing a manufacturing process of the display device of the embodiment. It is sectional process drawing (the 2) for demonstrating the manufacturing process of the display apparatus of embodiment. It is a perspective view which shows the television to which this invention is applied. It is a figure which shows the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view showing a notebook personal computer to which the present invention is applied. It is a perspective view which shows the video camera to which this invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the portable terminal device to which this invention is applied, for example, a mobile telephone, (A) is the front view in the open state, (B) is the side view, (C) is the front view in the closed state , (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. It is a layout diagram of a thin film transistor substrate for a display device having a conventional mirror inversion structure. It is a principal part plane process drawing for demonstrating the conventional manufacturing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 1a ... Thin-film transistor substrate, 12 ... Power supply line, 14a, 14b ... Gate electrode, 21c ... Lower electrode, 31 ... Gate insulating film, 32 ... Amorphous semiconductor thin film, 32A ... Crystallized semiconductor thin film , Cs ... capacitance element, EL ... light emitting element, EL (R) ... red light emitting element, EL (G) ... green light emitting element, EL (B) ... blue light emitting element, ... light emitting element, Lh ... laser light (energy beam) , Tr1, Tr2 ... Thin film transistor, ± v ... Scanning direction

Claims (9)

A thin film transistor in which a semiconductor thin film is disposed on a gate electrode patterned to a predetermined line width via a gate insulating film, and a source electrode and a drain electrode are connected to the semiconductor thin film;
An upper electrode is provided on the lower electrode extending from the gate electrode via the gate insulating film, and the lower electrode is separated from the gate electrode in a state where the lower electrode is adjacent to the line width direction of the gate electrode. And the capacitive element provided as a continuous pattern using the same layer as the source electrode or the drain electrode, the upper electrode,
A display device comprising: a pixel circuit configured using the thin film transistor and a capacitor element and arranged in a line width direction of the gate electrode. The display device according to claim 1, wherein the semiconductor thin film on the gate electrode is crystallized by irradiating while scanning energy lines along a line width direction of the gate electrode. The display device according to claim 1, wherein the pixel circuits arranged adjacent to each other in the arrangement direction are laid out with respect to the power supply line in a state of sharing one power supply line. The display device according to claim 1, wherein a light emitting element is connected to the thin film transistor and the capacitor element. An electrode pattern comprising a gate electrode having a predetermined line width and a lower electrode extending from the gate electrode and spaced apart from the gate electrode in the line width direction of the gate electrode is defined as a line width of the gate electrode. Forming an array in a direction;
Forming a gate insulating film and an amorphous semiconductor thin film in this order so as to cover the electrode pattern;
Crystallization of the semiconductor thin film by irradiating while scanning energy lines in the line width direction of the gate electrode;
A thin film transistor is formed by connecting a source electrode and a drain electrode to a semiconductor thin film crystallized on the gate electrode, and an upper electrode is formed on the lower electrode as a continuous pattern made of the same layer as the source or drain electrode. And a step of forming a capacitor element by providing a display device. The method for manufacturing a display device according to claim 5, wherein the irradiation with the energy beam is performed by reciprocating between the columns in which the electrode patterns are arranged. The method for manufacturing a display device according to claim 5, wherein a step of forming a light emitting element connected to the thin film transistor and the capacitor is performed. A thin film transistor in which a semiconductor thin film is disposed on a gate electrode patterned to a predetermined line width via a gate insulating film, and a source electrode and a drain electrode are connected to the semiconductor thin film;
An upper electrode is provided on the lower electrode extending from the gate electrode via the gate insulating film, and the lower electrode is separated from the gate electrode in a state where the lower electrode is adjacent to the line width direction of the gate electrode. And the capacitive element provided as a continuous pattern using the same layer as the source electrode or the drain electrode, the upper electrode,
A thin film transistor substrate comprising: a circuit configured using the thin film transistor and a capacitor and arranged in a line width direction of the gate electrode. An electrode pattern comprising a gate electrode having a predetermined line width and a lower electrode extending from the gate electrode and spaced apart from the gate electrode in the line width direction of the gate electrode is defined as a line width of the gate electrode. Forming an array in a direction;
Forming a gate insulating film and an amorphous semiconductor thin film in this order so as to cover the electrode pattern;
Crystallization of the semiconductor thin film by irradiating while scanning energy lines in the line width direction of the gate electrode;
A thin film transistor is formed by connecting a source electrode and a drain electrode to a semiconductor thin film crystallized on the gate electrode, and an upper electrode is formed on the lower electrode as a continuous pattern made of the same layer as the source or drain electrode. And a step of forming a capacitor element by providing a thin film transistor substrate manufacturing method.

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