JP2010151724A - Test method and test circuit of differential buffer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test method and a test circuit of a differential buffer for simplifying a constitution, and evaluating an offset voltage and a differential voltage of a differential signal. <P>SOLUTION: The test circuit includes: first and second resistive elements connected between differential signals output from a differential buffer and first and second test channels of a tester; a first node between the first resistive element and the first test channel; a second node between the second resistive element and the second test channel; and a capacitive element between the first and second nodes. The offset voltage and the differential voltage of the differential buffer are evaluated by the tester based on a test pattern by using the test circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test method and a test circuit for a common mode voltage (offset voltage) and a differential voltage of a differential buffer.

  When testing the output voltage of the differential signal output from the differential buffer, the positive output signal having a relatively high voltage is set to a high level (H), and the negative output having a relatively low voltage is output. The signal is set to a low level (L), the voltage of each output signal is measured with a tester, and the offset voltage and the differential voltage are evaluated.

  The offset voltage is evaluated by calculating an average voltage of the positive output signal voltage and the negative output signal voltage and checking whether the voltage value is within a specified range. In addition, the differential voltage is evaluated by subtracting the voltage of the negative output signal from the voltage of the positive output signal to obtain the difference voltage between the two and determining whether the voltage value is within the specified range. Do by checking.

  Conventionally, as a differential buffer test method, as described above, the voltage value of the differential signal output from the differential buffer is measured by a tester, and the DC test of the differential signal is performed based on the voltage value. Yes. However, this test method has a problem that the test time becomes long. Therefore, as a test method of the differential buffer, for example, it is desired to perform a test by a function test that compares with an expected value using a test pattern.

  Here, there is Patent Document 1 as a prior art document considered to be relevant to the present invention. In this document, when the differential voltage and the offset voltage of the differential output buffer are evaluated, the voltages when the pair output positive / negative are both H / L and L / H are measured, and the difference between them is measured. Is a differential voltage, and an average voltage is an offset voltage, and it is disclosed to evaluate that they are within a specified value range.

  In Patent Document 1, evaluation is performed by generating a differential voltage and an offset voltage using a differential amplifier. In this method, since the evaluation circuit is relatively complicated, there is a problem that the evaluation circuit becomes large when evaluating a plurality of differential signals.

JP 2007-333536 A

  An object of the present invention is to provide a test method and a test circuit for a differential buffer capable of evaluating an offset voltage and a differential voltage of a differential signal with a simple configuration.

To achieve the above object, the present invention provides first and second resistors respectively connected between each of differential signals output from a differential buffer and first and second test channels of a tester. Elements,
Connected between a first node between the first resistance element and the first test channel and a second node between the second resistance element and the second test channel; A differential buffer test circuit including a capacitive element.

The present invention also provides a method for testing a differential buffer using the test circuit described above,
The first and second test channels are driven by the tester based on a test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
In the subsequent first time, the voltage of the first and second nodes is compared with the expected value of the test pattern, and the pass / fail judgment of the offset voltage of the differential buffer is performed. Provide test methods.

The present invention also provides a method for testing a differential buffer using the test circuit described above,
The first and second test channels are driven by the tester based on a test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
In a subsequent second time, after driving one of the first and second test channels and setting one of the first and second nodes as a reference voltage, the other of the first and second nodes And a test value of the test pattern is compared to determine whether the differential voltage of the differential buffer is good or bad.

The present invention also provides a method for testing a differential buffer using the test circuit described above,
The first and second test channels are driven by the tester based on the test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
At the first time that follows, the voltage of the first and second nodes is compared with the expected value of the test pattern, and the pass / fail judgment of the offset voltage of the differential buffer is performed.
In a subsequent second time, after driving one of the first and second test channels and setting one of the first and second nodes as a reference voltage, the other of the first and second nodes In the differential buffer test method for comparing pass voltage and expected value of the test pattern and determining whether the differential voltage of the differential buffer is good or bad, the expected value when the differential voltage is tested and the other The differential buffer test method is characterized in that the expected value at the time of the test of the offset voltage is matched.

  According to the present invention, it is possible to test the offset voltage and the differential voltage of the differential buffer by performing the function test with the tester using the test pattern. Compared with the conventional DC test method, this test method has an effect of shortening the test time because the differential signal output from the differential buffer is tested by the function test of the LSI tester.

  Further, by matching the expected value of the other voltage of the first and second nodes when testing the differential voltage of the differential buffer with the expected value of the offset voltage of the other voltage when testing, the LSI Since it is possible to determine whether or not the offset voltage and the differential voltage of the differential signal of the differential buffer are good by a single test without changing the setting of the tester, the test time can be further shortened.

  Hereinafter, a differential buffer test method and a test circuit according to the present invention will be described in detail with reference to preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a conceptual diagram of an embodiment showing a configuration of a test circuit for a differential buffer according to the present invention. The differential buffer test circuit 10 shown in FIG. 1 is based on the output voltages Vp and Vn of the differential signals S1 and S2 output from the differential buffer 14, and the offset voltage of the differential signals S1 and S2 by the tester 20. This is for testing (evaluating) (Vp + Vn) / 2 and the differential voltage Vp-Vn.

  Here, the differential buffer 14 is mounted on a DUT (device under test) 12, and the differential buffer 14 has a positive signal S 1 having a relatively high voltage and a relatively low value corresponding thereto. A negative signal S2 having a voltage is output. The output voltages of the signals S1 and S2 are Vp and Vn, respectively.

  Although the tester 20 includes a plurality of test channels, only two test channels 22 and 24 are shown in FIG. Each of the test channels 22 and 24 includes an input buffer (comparator) 26 and an output buffer (driver) 28. In each test channel 22, 24, the input terminal of the input buffer 26 and the output terminal of the output buffer 28 are connected, and the connection point is the input / output terminal of the test channels 22, 24.

  The test circuit 10 includes two resistance elements 30 and 32 and a capacitive element 34. Here, the resistance values of the resistance elements 30 and 32 are the same resistance values R1 and R1, and the capacitance value of the capacitance element 34 is C2.

  Further, in the figure, when the differential buffer 14 is used, a termination resistor 36 connected between the differential signals S1 and S2 is shown. The resistance value of the termination resistor 36 is R2. The termination resistor 36 is not a component of the test circuit 10 but a load resistor used when the differential buffer 14 is actually used. In this embodiment, according to the situation when the differential buffer 14 is actually used, a test is performed by connecting the termination resistor 36 when the differential buffer 14 is tested.

  Signals S1 and S2 are connected to input / output terminals of test channels 22 and 24 via resistance elements 30 and 32, respectively. In the figure, a capacitive element 34 is provided between a node S3 between the upper resistance element 30 and the input / output terminal of the test channel 22 and a node S4 between the lower resistance element 32 and the input / output terminal of the test channel 24. Is connected. The voltages of the nodes S3 and S4 are set as voltages Vpt and Vnt, respectively.

  Note that the capacitive elements 38 and 40 connected between the nodes S3 and S4 and the ground are the capacitances of the input / output terminals of the test channels 22 and 24 and the connection cables corresponding to the nodes S3 and S4, respectively. is there. The capacitance values of the capacitive elements 38 and 40 are the same C1 and C1.

Next, a test method for the differential buffer 14 will be described.
First, a test method for the offset voltage Vc will be described.

  The tester 20 drives the nodes S3 and S4 to the test start time t0 based on the test pattern, and measures (detects) the voltages of the nodes S3 and S4 at the time t1, respectively, and compares them with expected values. To test Vc.

  In a state where H and L are output to the differential signals S1 and S2 from the differential buffer 14, the output buffers 28 and 28 of the test channels 22 and 24 are driven, and the nodes S3 and S4 are set to the same voltage ( The initial voltages are V0 and V0 (about 1.2 V in this embodiment). At this time, since the same voltage V0 is applied to both ends of the capacitive element 34, the capacitive element 34 is discharged, and the nodes S3 and S4 are forced to have the same voltages V0 and V0.

  Thereafter, the outputs of the output buffers 28 and 28 of the test channels 22 and 24 are set to a high impedance state, and driving of the voltages V0 and V0 to the nodes S3 and S4 is stopped. At this time, due to the output of the differential signals S1 and S2 from the differential buffer 14, currents flow to the nodes S3 and S4 via the resistance elements 30 and 32, respectively, and the capacitive elements C1 and C1 and the capacitive element C2 are charged or discharged. Is done.

  When V0 = 1.2V, Vp = 1.53V, Vn = 1.03V, R1 = 30 kΩ, R2 = 100Ω, C1 = 80 pF, C2 = 3.3 nF, the waveforms of the nodes S3 and S4 in the above operation are illustrated. 2 and FIG.

  2 and 3 are graphs showing the waveforms of the voltages Vpt and Vnt of the nodes S3 and S4 at the time of offset voltage evaluation and at the time of differential voltage evaluation, respectively. FIG. 2 is an enlarged view showing the waveform from elapsed time t = 0 to 10000 ns in FIG. The vertical axis of these graphs represents voltage [V], and the horizontal axis represents elapsed time [ns]. These drawings also show a voltage (Vpt + Vnt) / 2 that is 1/2 of Vpt and Vnt corresponding to the offset voltage Vc.

  Assuming that the outputs of the output buffers 28 and 28 of the test channels 22 and 24 are in a high impedance state at time t0 (test start time, that is, timing when elapsed time = 0 ns in FIGS. 2 and 3), the node at time t The voltages Vpt and Vnt of S3 and S4, that is, the input voltages to the input buffers 26 and 26 of the test channels 22 and 24 are given by the following equations (1) and (2).

Here, Vc is an offset voltage and is represented by Vc = (Vp + Vn) / 2. Vd is a differential voltage and is expressed by Vd = Vp−Vn. e is the base of the natural logarithm. A CR circuit is formed by the resistance values R1 and R1 of the resistance elements 30 and 32, the capacitance value C2 of the capacitance element 34, and the capacitance values C1 and C1 of the capacitance elements 38 and 40, and the common mode time constant τ _C = R1C1, The speed of change of the voltages Vpt and Vnt at the nodes S3 and S4 is determined by the time constant τ _N = R1C1 + 2R1C2 in the normal mode.

  In the above formulas (1) and (2), the first item represents the initial voltage V0 at the nodes S3 and S4, the second item is the time change due to the offset voltage Vc, and the third item is the time change due to the differential voltage Vd. Represents minutes.

In the case of C2 >> C1, the value (voltage value) of the second item (time change due to the offset voltage Vc) of the expressions (1) and (2) rapidly approaches Vc−V0 exponentially. During this period (until Vpt and Vnt reach the standard value of Vc (about 1.28 V in this embodiment) from V0 (time t0)), the potentials of Vpt and Vnt are as shown in the graph of FIG. Furthermore, according to the time constant τ _C described above, the potential approaches Vc with almost no separation.

The time required for Vpt and Vnt to reach the standard value of Vc from V0 is determined by the size of C1 (ie, the size of time constant τ _C ). On the other hand, when C2 is small, Vpt and Vnt are shifted (moved away) from each other earlier, so that when offset voltage is evaluated, C2 is preferably larger. However, in the present embodiment, the timing for evaluating the differential voltage is delayed by that amount (the test time becomes longer), and therefore, for example, C2 is preferably about 100 times C1.

  Here, it is assumed that the standard value of the offset voltage Vc is in the range of V0 ± ΔV0. This is equivalent to the following equation (3).

  That is, it is only necessary to satisfy the following expressions (4) and (5) at time t1, which is the timing for evaluating the offset voltage Vc.

Here, (Vpt + Vnt) / 2 gradually approaches the offset voltage Vc = (Vp + Vn) / 2 according to the time constant τ _C, and the waveform at that time (voltage change rate) is determined in advance by the time constant τ _C. . As described above, since the standard value (range) of the offset voltage Vc is determined in advance, if the time t1 is determined, the voltage value (range) corresponding to the standard value (range) of the offset voltage Vc at the time t1. Range) can be calculated.

  Also, equation (6) is derived from equations (4) and (5).

  In the graph of FIG. 2, for example, since the relationship of the following formula (7) is established at the time t1 = 4000 ns, (Vpt + Vnt) / 2 at the time t1 = 4000 ns is in the range of about V0 ± 0.8111ΔV0. It would be good if it was inside. Here, R1 = 30 kΩ and C1 = 80 pF.

  Here, when the value (voltage value) of the third item (time change due to the differential voltage Vd) in the expressions (1) and (2) is sufficiently small and can be said to be within the allowable error range, (Vpt + Vnt) / 2≈Vpt≈Vnt. Therefore, by comparing Vpt and Vnt with the expected value of the test pattern by the comparator of the tester 20, and determining V0 ± 0.8111ΔV0 as the test pass region (passing range), it is possible to determine whether the offset voltage Vc is good or bad. .

  Next, a test method for the differential voltage Vd will be described.

  Subsequently, based on the test pattern, the tester 20 drives the node S4 at time t2, measures (detects) the voltage of the node S3, and compares this with the expected value to test Vd.

When C2 >> C1, Vpt and Vnt gradually deviate from the standard value of Vc according to the time constant τ _N as shown in the graph of FIG. 3 after Vpt and Vnt reach the standard value of Vc. It spreads in the direction.

  It is assumed that Vdmin ≦ Vd ≦ Vdmax (for example, 0.3 V ≦ Vd ≦ 0.5 V) is given as a standard value for Vd = Vp−Vn. Vdmin and Vdmax represent the minimum value and the maximum value of Vd, respectively. When Vd = Vp−Vn is calculated by subtracting Equation (2) from Equation (1), the relationship of Equation (8) below is established. Therefore, time t2 (t1 < At t2), the following equation (9) should be satisfied.

Here, Vpt-Vnt approaches the time constant tau _N gradually differential voltage Vd = Vp-Vn in accordance with, the time of the waveform (a rate of voltage change) is determined time constant tau _N Therefore advance. As described above, since the standard value of the differential voltage Vd is determined in advance, if the time t2 is determined, the voltage value (range) corresponding to the standard value of the differential voltage Vd at the time t2 is calculated. be able to.

  Subsequently, at time t2, as shown in the graph of FIG. 3, the node S4 is driven by the output buffer 28 of the tester channel 24 shown in FIG. 1, and Vnt is forcibly shifted to the potential of the reference voltage Vd0.

  At this time, although the electric charge of the capacitive element 34 is charged / discharged via the resistance elements 30 and 32, it does not change abruptly, so the potential of Vpt−Vnt is maintained. Therefore, immediately after Vnt is forcibly set to Vd0, the relationship of the following formula (10) is established. To be precise, although there is a charge transfer between the capacitive element 34 and the capacitive elements 38, 40, when C2 ≧ C1, the increase / decrease ratio of the charge of the capacitive element 34 is low, so the capacitive elements 38, 40 The charging voltage is almost unchanged.

  Accordingly, the Vpt value (voltage value) is compared with the expected value of the test pattern by the comparator of the tester 20, and the range of the Vpt value satisfying the condition of the following equation (11) is set as the test pass region. Whether the dynamic voltage Vd is good or bad can be determined.

  As described above, the function test is performed by the tester 20 using the test pattern, so that the offset voltage Vc and the differential voltage Vd of the differential buffer 14 can be tested. Compared with the conventional DC test method, this test method has an effect of shortening the test time because the differential signal output from the differential buffer is tested by the function test of the LSI tester.

  In the test method, the same tester channels 22 and 24 are used for the offset voltage Vc test and the differential voltage Vd test. The expected values of the comparators corresponding to the tester channels 22 and 24 cannot be changed during the test. Therefore, the test of the differential buffer 14 is performed twice in total for the offset voltage Vc test and the differential voltage Vd test.

  On the other hand, a comparison value (voltage value) for evaluating the offset voltage Vc and the differential voltage Vd is selected by selecting t1, t2, and Vd0 that satisfy the following expressions (12) and (13). Can be common.

  Here, the left side of Expression (12) is the minimum value of Vpt in Expression (11), and the right side is the minimum value of (Vpt + Vnt) / 2 in Expression (6). Similarly, the left side of equation (13) is the maximum value of Vpt in equation (11), and the right side is the maximum value of (Vpt + Vnt) / 2 in equation (6). That is, the voltage Vpt at the time of testing the offset voltage Vc and the voltage Vpt at the time of testing the differential voltage Vd are matched.

  As a result, the pass / fail judgment of the offset voltage and differential voltage of the differential signal of the differential buffer can be performed by a single test without changing the setting of the LSI tester, thereby further reducing the test time. Can do.

  The resistance values R1 and R1 of the resistance elements 30 and 32 and the capacitance value C2 of the capacitance element 34 are not limited at all, and may be determined as appropriate in consideration of test time, tester performance, and the like. In the test of the differential voltage Vd, the node S3 may be driven at time t2 and Vpt may be set to Vd0. In this case, the relationship between Vpt and Vnt is opposite to that in the above embodiment. It is also possible to test a plurality of differential buffers simultaneously in parallel.

  The initial voltage V0 may be any of a voltage lower than the specified value of the offset voltage Vc, the same voltage as the specified value of the offset voltage Vc, or a voltage higher than the specified value of the offset voltage Vc, as in the above embodiment. Good. Further, the reference voltage Vd0 is not limited at all, and may be determined as appropriate. The reference voltage Vd0 is a reference voltage when the comparison is performed using the test pattern by the comparator, and the value is reflected in advance in the comparison value of the test pattern.

  Further, the time t1 for testing the offset voltage Vc and the time t2 for testing the differential voltage Vd are not limited at all. However, although depending on the measurement accuracy of the tester, it is desirable that the time t1 is a period in which the voltage can be measured by the tester and the potential difference between the nodes S3 and S4 is small for the purpose of reducing the measurement error. Further, it is desirable that the time t2 is a period in which the voltage can be measured by the tester and the potential difference between the nodes S3 and S4 is large. That is, it is desirable that t1 <t2.

  Furthermore, it is desirable to determine appropriate times t1 and t2 based on the following equation (14) and to test the offset voltage Vc and the differential voltage Vd. The denominator on the left side of Equation (14) is the width of the determination range of the measured value (voltage value) of Vpt≈Vnt when testing the offset voltage Vc, and the numerator on the left side is the measured value of Vpt when testing the differential voltage Vd. It is an error width of (voltage value), and it is desirable that the ratio of both is 0.2 or less.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

It is a conceptual diagram of one Embodiment showing the structure of the test circuit of the differential buffer of this invention. It is a graph showing the waveforms of voltages Vpt and Vnt of nodes S3 and S4 at the time of offset voltage evaluation. 6 is a graph showing waveforms of voltages Vpt and Vnt of nodes S3 and S4 at the time of differential voltage evaluation.

Explanation of symbols

10 Test Circuit 12 DUT (Device Under Test)
14 Differential buffer 20 Tester 22, 24 Test channel 26 Input buffer 28 Output buffer 30, 32 Resistive element 36 Terminating resistor 34, 38, 40 Capacitance element S1, S2 Differential signal S3, S4 Node

Claims (4)

First and second resistance elements respectively connected between each of the differential signals output from the differential buffer and the first and second test channels of the tester;
Connected between a first node between the first resistance element and the first test channel and a second node between the second resistance element and the second test channel; A test circuit for a differential buffer, comprising: a capacitor element. A method for testing a differential buffer using the test circuit according to claim 1, comprising:
The first and second test channels are driven by the tester based on a test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
In the subsequent first time, the voltage of the first and second nodes is compared with the expected value of the test pattern, and the pass / fail judgment of the offset voltage of the differential buffer is performed. Test method. A method for testing a differential buffer using the test circuit according to claim 1, comprising:
The first and second test channels are driven by the tester based on a test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
In a subsequent second time, after driving one of the first and second test channels and setting one of the first and second nodes as a reference voltage, the other of the first and second nodes A differential buffer test method, comprising: comparing a voltage of the differential buffer with an expected value of the test pattern to determine whether the differential voltage of the differential buffer is good or bad. A method for testing a differential buffer using the test circuit according to claim 1, comprising:
The first and second test channels are driven by the tester based on the test pattern, and the first and second nodes are set to the same initial voltage, respectively. Set the output of the test channel to the high impedance state,
At the first time that follows, the voltage of the first and second nodes is compared with the expected value of the test pattern, and the pass / fail judgment of the offset voltage of the differential buffer is performed.
In a subsequent second time, after driving one of the first and second test channels and setting one of the first and second nodes as a reference voltage, the other of the first and second nodes In the differential buffer test method for comparing the voltage of the differential voltage with the expected value of the test pattern and determining whether the differential voltage of the differential buffer is good or bad, the expected value when the differential voltage is tested and the other A test method for a differential buffer, characterized in that an expected value of the offset voltage at the time of testing of the offset voltage is matched.

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