JP2010147072A - Non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower a breakdown voltage of an insulating film, relating to a non-volatile semiconductor memory device in which data is stored by dielectric breakdown of the insulating film, between a drain layer and a drain electrode. <P>SOLUTION: A drain electrode 18 has a triangular tip corner 18P, and the tip corner 18P is superimposed on the end part of a drain layer 11D via a gate insulating film 13. When the drain electrode 18 is applied with a breakdown voltage, a field concentration occurs at the tip corner 18P of the drain electrode 18, causing dielectric breakdown of the gate insulating film 13 at a low voltage, and this results in a short-circuit between the drain electrode 18 and the drain layer 11D. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which data is stored by dielectric breakdown of an insulating film between a drain layer and a drain electrode.

  2. Description of the Related Art Conventionally, there has been known a nonvolatile semiconductor memory device that stores data using dielectric breakdown of an insulating film. This nonvolatile semiconductor memory device includes a memory cell transistor in which a drain electrode is superimposed on a drain layer via an insulating film, and a bit line connected to the drain electrode, and applies a breakdown voltage from the bit line to the drain electrode. Thus, data is written to the memory cell transistor by causing the above-described insulating film to break down.

  When reading data, the bit line is precharged to an appropriate potential in advance, and then the memory cell transistor is turned on. Then, in a state where the insulating film is not broken down, since the drain layer and the drain electrode are insulated, the potential of the bit line remains the precharge potential. On the other hand, since the drain layer and the drain electrode are short-circuited in the state in which the insulating film breaks down, the bit line potential changes to the source potential when the memory cell transistor is turned on.

  That is, according to this nonvolatile semiconductor memory device, the state in which the insulating film is not broken down corresponds to, for example, the data value “0”, and the state in which the insulating film breaks down corresponds to the data value “1”. Data writing and reading can be performed.

  Since this nonvolatile semiconductor memory device uses dielectric breakdown, once data is written, it cannot be erased or rewritten thereafter, but it can be used as a trimming memory for analog circuits and the like. it can.

This type of nonvolatile semiconductor memory device is described in Patent Document 1.
JP 2006-245177 A

  In the above-described nonvolatile semiconductor memory device, it is necessary to apply a breakdown voltage of the insulating film to the drain electrode. However, this breakdown voltage is as high as 11.6 V to 12 V even when the thickness of the insulating film is about 7 nm, and it is necessary to further reduce the breakdown voltage for practical use.

  Therefore, a nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate via an insulating film, a source layer formed adjacent to one side of the gate electrode, A drain layer formed adjacent to the other side of the gate electrode, a drain electrode overlapped with the drain layer via the insulating film, and a voltage applying unit for applying a breakdown voltage to the drain electrode to break down the insulating film The drain electrode has a tip corner as viewed from a direction perpendicular to the surface of the semiconductor substrate, and the tip corner overlaps with the drain layer.

  According to the nonvolatile semiconductor memory device of the present invention, when a breakdown voltage is applied to the drain electrode, electric field concentration occurs at the corner of the tip, so that the breakdown voltage can be lowered.

  As a result, this type of nonvolatile semiconductor memory device can be incorporated into an LSI that operates at a low power supply voltage (eg, 3.3 V).

  A nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. The nonvolatile semiconductor memory device according to the present embodiment is a PROM in which data is written and stored only once by dielectric breakdown of the insulating film between the drain layer and the drain electrode. For example, as a trimming memory such as an analog circuit It is available.

  First, a circuit configuration example of this nonvolatile semiconductor memory device will be described with reference to the circuit diagram of FIG. The nonvolatile semiconductor memory device has a memory cell array MA in which a plurality of memory cell transistors are arranged in a matrix. In FIG. 1, for convenience of explanation, only four memory cell transistors MT1, MT2, MT3, MT4 are shown among the plurality of memory cell transistors, but other memory cell transistors (not shown) have the same configuration. is doing. In the following description, the memory cell transistors MT1, MT2, MT3, MT4,... Are all N-channel MOS transistors, but are not limited to this and may be P-channel transistors.

  A plurality of word lines WL1, WL2,... Made of polysilicon or the like are arranged in the row direction of the memory cell array MA. In the column direction of the memory cell array MA, a plurality of bit lines BL1, BL2,... Made of aluminum or the like are arranged crossing each word line WL1, WL2,.

  Memory cell transistors MT1, MT2, MT3, MT4,... Are arranged at intersections between the word lines WL1, WL2,. Each gate of each memory cell transistor MT1, MT2, MT3, MT4,... Is constituted by a corresponding word line WL1, WL2,. Further, each source layer 11S of each memory cell transistor MT1, MT2, MT3, MT4,... Is connected to a source line SL made of aluminum or the like. For example, a ground voltage Vss is supplied to the source line SL as a fixed voltage. On the other hand, a gate insulating film 13 is sandwiched between the drain layer 11D and the drain electrode 18 of each memory cell transistor MT1, MT2, MT3, MT4,. The drain electrode 18 is connected to the corresponding bit line BL1, BL2,.

  In the memory cell array MA described above, each word line WL1, WL2,... Is connected to a word line selection circuit (not shown). The word line selection circuit selects one of the plurality of word lines WL1, WL2,... According to the row address signal.

  Further, each bit line BL1, BL2,... Is connected to the read / write circuit BS via the bit line selection transistors BT1, BT2,. The bit line selection transistors BT1, BT2,... Select any one bit line from the plurality of bit lines BL1, BL2,. This is connected to the read / write circuit BS.

  The read / write circuit BS has a sense amplifier for detecting the voltage of the bit line selected by the bit line selection transistors BT1, BT2,... And a breakdown voltage for insulating the gate insulating film 13 on the bit line. A voltage generation circuit (not shown) to be applied is provided.

  Each bit line BL1, BL2,... Is provided with a precharge transistor PT that supplies a precharge voltage, for example, a power supply voltage Vdd, in accordance with the precharge signal PS. In the present embodiment, the precharge transistor PT is assumed to be a P-channel MOS transistor, but is not limited to this, and may be an N-channel type.

  Hereinafter, the configuration of the memory cell transistors MT1, MT2, MT3, MT4,... Will be described with reference to FIGS. FIG. 2 shows a planar configuration of one memory cell transistor MT1 as an example among the plurality of memory cell transistors MT1, MT2, MT3, MT4,. FIG. 3 is a cross-sectional view taken along line XX in FIG. 2, and FIG. 4 shows a cross section taken along line YY in FIG. Other memory cell transistors MT2, MT3, MT4,... Arranged in the memory cell array MA are the same as the configuration of the memory cell transistor MT1. In FIG. 2, only main components are shown, and other components such as the sidewall films SP1 and SP2 are not shown.

  For example, a P-type semiconductor layer 11 is formed on a semiconductor substrate 10 made of an N-type silicon substrate. A LOCOS (Local Oxidation of Silicon) insulating film 12 is formed on the surface of the P-type semiconductor layer 11 as an element isolation insulating film.

  The film thickness of the LOCOS insulating film 12 is, for example, 400 nm. A memory cell transistor MT1 is formed in the activation region surrounded by the LOCOS insulating film 12. A gate insulating film 13 made of a silicon oxide film or the like is formed on the surface of the P-type semiconductor layer 11 in the activated region. The film thickness of the gate insulating film 13 is about 7 nm, for example.

  On the gate insulating film 13, a word line WL1 functioning as a gate electrode is formed. A sidewall film SP1 made of an insulating film is formed on the sidewall of the word line WL1. A drain layer 11D composed of an N− type layer 14 and an N + type layer 15 is formed on the surface of the P type semiconductor layer 11 adjacent to one side of the word line WL1. The surface of the drain layer 11D is covered with a gate insulating film 13. A source layer 11S composed of an N− type layer 16 and an N + type layer 17 is formed on the surface of the P type semiconductor layer 11 on one side of the word line WL1. That is, the drain layer 11D and the source layer 11S have an LDD structure.

  Further, a drain electrode 18 made of polysilicon or the like extends from above the LOCOS insulating film 12 adjacent to the drain layer 11D so as to cover at least a part of the N− type layer 14 of the drain layer 11D. In other words, the end of the drain electrode 18 overlaps with the end of the drain layer 11 </ b> D, that is, at least a part of the N− type layer 14 with the gate insulating film 13 interposed therebetween. A sidewall film SP2 made of an insulating film is formed at the end of the drain electrode 18, but the sidewall film SP2 may be removed.

  An example of a method for forming the drain electrode 18 and the drain layer 11D in the above configuration will be described. First, the word line WL1 and the drain electrode 18 are formed, and then the sidewall films SP1 and SP2 are formed. Thereafter, the drain layer 11D is formed in a self-aligned manner by impurity implantation using the word line WL1, the drain electrode 18, and the sidewall films SP1 and SP2 as a mask. Alternatively, another forming method different from this may be used. For example, first, the word line WL1 is formed. Then, the drain layer 11D may be formed by impurity implantation, and then the drain electrode 18 may be formed.

  Note that the drain layer 11D may have a single drain structure composed of a single N + type layer instead of the LDD structure as described above. In this case, it suffices if the N + type layer overlaps with the drain electrode 18.

  In the example of the figure, in the gate insulating film 13, the region overlapping with the word line WL1 and the region overlapping with the drain electrode 18 are continuously formed with the same film thickness, but the present invention is not limited to this. , They may have different film thicknesses.

  In the example of the figure, the gate insulating film 13 is continuously formed so as to overlap with the word line WL1 and also overlap with the drain electrode 18. However, the present invention is not limited to this, and the gate insulating film 13 overlaps with the word line WL1. It may be formed separately in a region including a portion and another region including a portion where the drain electrode 18 overlaps.

  An interlayer insulating film 19 is formed so as to cover the memory cell transistor MT1. A contact hole CH1 reaching the drain electrode 18 is provided in the interlayer insulating film 19, and a bit line BL1 connected to the drain electrode 18 through the contact hole CH1 is formed on the interlayer insulating film 19. When a breakdown voltage is supplied to the bit line BL1 from the read / write circuit BS, the gate insulating film 13 sandwiched between the drain electrode 18 and the N− type layer 14 is broken down, so that the bit line BL1 and the drain layer are 11D is short-circuited.

  Further, a contact hole CH2 reaching the source layer 11S is provided in the interlayer insulating film 19 and the gate insulating film 13, and a source line SL connected to the source layer 11S through the contact hole CH2 is formed on the interlayer insulating film 19. Has been.

  Hereinafter, a more detailed structure of the memory cell transistor MT1 will be described. The drain electrode 18 of the memory cell transistor MT1 has a triangular tip corner 18P when viewed from the direction perpendicular to the surface of the semiconductor substrate 10, and the tip corner 18P is the end of the drain layer 11D. That is, it overlaps with the N− type layer 14. The angle of the tip corner 18P when viewed from the direction perpendicular to the surface of the semiconductor substrate 10 is, for example, about 90 degrees. The angle of the tip corner 18P may be other than this, but is preferably 90 degrees or less in order to cause stronger electric field concentration.

  When a breakdown voltage is applied to the drain electrode 18 via the bit line BL1, electric field concentration occurs at the tip corner 18P. Due to this electric field concentration, the gate insulating film 13 sandwiched between the drain electrode 18 and the N− type layer 14 of the drain layer 11 </ b> D is easily broken down. That is, the breakdown voltage can be lowered as compared with the case where the gate insulating film 13 is sandwiched between the drain electrode 18 having no tip corner 18P and the N− type layer 14.

  The tip corner 18P is formed by, for example, a process of patterning the drain electrode 18 using a mask formed by a photolithography technique. The finish of the tip of the tip corner 18P is finished according to the patterning accuracy at that time. The processing shape may be slightly rounded. However, the degree of roundness is such that it does not hinder the above-described decrease in breakdown voltage.

  Further, in addition to the above configuration, the drain layer 11D includes a wide first region 11D-A and a narrow second region 11D-B when viewed from a direction perpendicular to the surface of the semiconductor substrate 10. ing. The tip corner 18P of the drain electrode 18 overlaps the second region 11D-B. With this configuration, electric field concentration occurs in a narrow portion of the drain layer 11D, that is, the second region 11D-B, so that the breakdown voltage can be further reduced.

  Here, the effect of bird's beak of the LOCOS insulating film 12 in the cross-sectional configuration of the second region 11D-B will be described with reference to FIG. At the end of the LOCOS insulating film 12, a portion generally called a bird's beak is formed by lateral diffusion of oxygen during selective oxidation. When the bird's beak extends toward the center of the second region 11D-B in the drain layer 11D, the area of the thinner gate insulating film 13 becomes narrower, and electric field concentration occurs there. The gate insulating film 13 is easily broken down.

  As the element isolation insulating film, instead of the LOCOS insulating film 12, another insulating film, for example, a shallow trench insulating film (STI) in which an insulating film is embedded in a trench formed in the P-type semiconductor layer 11 is used. However, since the shallow trench insulating film does not use selective oxidation, no bird's beak is formed.

  Hereinafter, a write operation in the above-described nonvolatile semiconductor memory device will be described. First, the case where the data value “1” is written will be described by taking the memory cell transistor MT1 as an example. In this case, a high level (power supply voltage Vdd) row address signal is applied from the word line selection circuit to the word line WL1 connected to the memory cell transistor MT1. As a result, the word line WL1 is selected and the memory cell transistor MT1 is turned on. In addition, a low level (ground voltage Vss) column address signal is applied to the gate of the bit line selection transistor BT1 corresponding to the bit line BL1. Then, the bit line selection transistor BT1 is turned on, and the bit line BL1 is connected to the read / write circuit BS. A breakdown voltage is applied from the read / write circuit BS to the bit line BL1.

  Then, a breakdown voltage is applied to the drain electrode 18 of the memory cell transistor MT1 via the bit line BL1. As a result, electric field concentration occurs at the tip corner 18P of the drain electrode 18, and the gate insulating film 13 sandwiched between the tip corner 18P and the N− type layer 14 of the drain layer 11D breaks down. When the gate insulating film 13 is broken down, the drain layer 11D of the memory cell transistor MT1 and the bit line BL1 are electrically short-circuited. In this way, the data value “1” is written into the memory cell transistor MT1.

The state of the breakdown of the gate insulating film 13, FIG. 5, i.e., the drain current I _D in the drain layer 11D on the vertical axis, will be described with reference to the characteristic diagram in the case where the drain voltage V _D and the horizontal axis. As shown in the drawing, even when a voltage lower than the breakdown voltage V _X is applied to the drain electrode 18, the drain current _ID hardly changes, but when a voltage higher than the breakdown voltage V _X is applied to the drain electrode 18, The insulating film 13 is broken down, and the drain current _ID increases rapidly. The breakdown of this embodiment, the use of the drain electrode 18 having a tip angle portion 18P, the breakdown voltage V _X, the breakdown voltage V necessary when using drain electrode 18 without a tip angle portion 18P It can be lower than _X.

  On the other hand, writing is not performed on other memory cell transistors connected to the bit line BL1, for example, the memory cell transistor MT3. This is because a low level (ground voltage Vss) row address signal is applied to the word line WL2 corresponding to the memory cell transistor MT3, and the word line WL2 is not selected, so that the memory cell transistor MT3 is turned off. Because.

  That is, in the nonvolatile semiconductor memory device, the gate insulating films 13 of all the memory cell transistors MT1, MT2, MT3, MT4,... The electrode 18 is insulated. In this case, all the memory cell transistors MT1, MT2, MT3, MT4,... Store the data value “0”. As described above, the data value “1” is written by breaking down the gate insulating film 13 of the selected memory cell transistor.

  Hereinafter, a read operation in the nonvolatile semiconductor memory device described above will be described. First, when the precharge transistor PT is turned on by the precharge signal PS, the bit lines BL1, BL2,... Are precharged to the power supply voltage Vdd.

  The case of reading the data value stored in the memory cell transistor MT1 will be described. The word line WL1 is selected in the same manner as at the time of writing, and the memory cell transistor MT1 is turned on. The bit line BL1 connected to the memory cell transistor MT1 is selected by the bit line selection transistor BT1, and the bit line BL1 is connected to the read / write circuit BS.

  When the data value “1” is stored in the memory cell transistor MT1, since the drain layer 11D and the drain electrode 18 are short-circuited, the voltage of the bit line BL1 is the ground voltage that is the voltage of the source line SL from the power supply voltage Vdd. The voltage changes to Vss. On the other hand, when the data value “0” is stored in the memory cell transistor MT1, since the drain layer 11D and the drain electrode 18 are insulated, the voltage of the bit line BL1 does not change from the power supply voltage Vdd. Therefore, the data value stored in the memory cell transistor MT1 can be read by determining whether the voltage of the bit line BL1 is the ground voltage Vss or the power supply voltage Vdd by the read / write circuit BS.

  As described above, according to the nonvolatile semiconductor memory device of this embodiment, the breakdown voltage of the gate insulating film can be lowered. Thereby, it becomes easy to mount the nonvolatile semiconductor memory device on various LSIs including analog circuits and digital circuits. The breakdown voltage is created by a voltage generation circuit (not shown) of the read / write circuit BS, but the voltage generation circuit is formed by a booster circuit (not shown) that boosts the power supply voltage Vdd, so that the breakdown voltage is high. The circuit scale becomes large and the practicality becomes poor. On the other hand, according to the present embodiment, the breakdown voltage can be lowered, so that the boosting by the booster circuit can be reduced and the circuit scale can be suppressed.

1 is a circuit diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. It is a figure explaining the mode of the dielectric breakdown of the gate insulating film by embodiment of this invention from the relationship between drain current and drain voltage.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 P type semiconductor layer 11D-A 1st area | region 11D-B 2nd area | region 12 LOCOS insulating film 13 Gate insulating films 14 and 16 N-type layer 15, 17 N + type layer 18 Drain electrode 19 Interlayer insulating film WL1, WL2 Word line BL1, BL2 Bit line SL Source line MA Memory cell array MT1, MT2, MT3, MT4 Memory cell transistor BT Bit line selection transistor PT Precharge transistor SP1, SP2 Side wall film

Claims (5)

A semiconductor substrate;
A gate electrode formed on the surface of the semiconductor substrate via an insulating film;
A source layer formed adjacent to one side of the gate electrode;
A drain layer formed adjacent to the other side of the gate electrode;
A drain electrode overlapping the drain layer via the insulating film;
A voltage application unit for applying a breakdown voltage to the drain electrode for dielectric breakdown of the insulating film,
The nonvolatile semiconductor memory device, wherein the drain electrode has a tip corner portion as viewed from a direction perpendicular to the surface of the semiconductor substrate, and the tip corner portion overlaps the drain layer. When viewed from the direction perpendicular to the surface of the semiconductor substrate, the drain layer extends in a direction closer to the gate electrode from the first region, and extends farther from the first region to the gate electrode and than the first region. Including a second region having a narrow width;
The nonvolatile semiconductor memory device according to claim 1, wherein a tip corner portion of the drain electrode overlaps with the second region. A LOCOS film having a film thickness thicker than the insulating film adjacent to the outside of the drain layer;
3. The nonvolatile semiconductor memory device according to claim 1, wherein an end portion of the LOCOS film has a bird's beak extending toward the drain electrode superimposed on the drain layer. The drain layer includes a first drain layer and a second drain layer having a lower concentration than the first drain layer, and the drain electrode overlaps with the second drain layer. The non-volatile semiconductor memory device according to claim 1. 5. The nonvolatile film according to claim 1, wherein the insulating film has a different thickness in a region overlapping with the gate electrode and a region overlapping with the drain electrode. Semiconductor memory device.

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