JP2010146521A - Arithmetic processing unit with floating point number computing function for controlling servo motor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that computational performance is reduced due to format conversion required when control operation including both integers and floating point numbers is executed. <P>SOLUTION: A command includes a conversion flag for instructing format conversion to input and output data instructed by an operand. A decoding stage of a pipeline includes a format conversion part for converting the format of the input data, referring to the conversion flag, and preparing input data for an execution stage. A write-back stage of the pipeline includes a format conversion part for converting the format of the computation result of a computing unit in the execution stage, referring to the conversion flag, and preparing input data to be supplied to the execution stage for data in the write-back stage and forwarding. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device that performs arithmetic processing for servo motor control by mixing an integer and a floating-point number, and a servo motor control device using such an arithmetic processing device.

Dedicated ASICs equipped with a program calculation function have come to be used in order to perform calculations specific to servo motor control efficiently at high speed. Variables necessary for servo motor control have been managed by registers having integer values. This is because the command value of the target position when performing positioning or the like is expressed by the number of pulses handled as an integer value. Parameters for servo control such as gain are also managed as integer values. However, in control filter processing, etc., there are many operations such as multiplication of variables.In integer operations, there is a problem such as overflow of digits, which requires time to check. It was. In the control of servo motors, there has been a demand to manage intermediate variables, especially multiplication, etc. with floating-point numbers while managing variables with integers. By doing so, speeding up can be realized without worrying about digit overflow. However, for that purpose, it is necessary to perform an operation in which an integer and a floating-point number are mixed. In the conventional arithmetic function, before performing a floating-point operation, a method is used in which an integer is converted into a floating-point number using a conversion instruction, and an operation result is converted again into an integer using the conversion instruction. In this case, as a matter of course, the entire processing is excessively performed for the time required for executing the conversion instruction.
FIG. 8 shows an example in which an integer is converted in format, added as a floating-point number, and converted into an integer again. All steps other than the step of actually executing an operation (FADD) are necessary for format conversion. Extra time is generated for the execution time of these steps.
In addition, there is an apparatus (for example, Patent Document 1) in which it is not necessary to perform format conversion by a format conversion instruction by having a format conversion unit in the arithmetic processing unit. FIG. 6 is an example of such a prior art.
In FIG. 6, the numerical processor 100 includes a conversion unit 102 and a limit unit 106 connected to the internal data bus 110, and includes an inverse conversion unit 103 whose input is the local data bus 111 and whose output is a limit unit, The register unit 101 includes a conversion control bit 104 for controlling the operation of the conversion unit and the inverse conversion unit, a conversion status bit 105 for holding the status output of the inverse conversion unit, and a limit unit control bit 107 for controlling the operation of the limit unit. And limit data 108 which is a boundary value to be given to the limit part, and AND 109 which takes the logical product of the conversion control bit and the limit part control bit. The purpose is to interface with a numeric format other than the floating-point number format, to operate the arithmetic unit with a floating-point number, and to obtain a correct calculation result. (For example, see Patent Document 1).
However, for example, when format conversion is performed on integers, addition is performed with floating-point numbers, and format conversion is performed again into integers, the description is as shown in FIG. An instruction for resetting is added, and extra time corresponding to the execution time necessary for this instruction is generated.
JP 2004-110665 (11 pages, Fig. 1)

In order to control the servo motor, when performing operations such as mixed integers and floating-point numbers, or when only operations are performed with floating-point numbers, but data are stored as integers, it is conventional The format conversion instruction is executed to unify the format for the operation, and the result is converted again.
Some arithmetic processing units have a format conversion unit that eliminates the need for format conversion instructions, but both require extra steps other than those required for computation, and execute those extra steps. There was a problem that the entire processing was delayed by the amount of time.
The present invention has been made in view of such problems, and format conversion is performed by executing format conversion from an integer to a floating-point number or a floating-point number to an integer in parallel in a pipeline process. Therefore, the servo motor is controlled at a high speed by eliminating the special step for the above and performing it only in the time required for the calculation.

In order to solve the above problem, the present invention is configured as follows.
The invention according to claim 1 is an arithmetic processing unit for servo motor control that performs floating-point arithmetic in conformity with IEEE754 in addition to integer arithmetic, and uses integers for input and output data indicated by operands. The instruction is provided with a conversion flag instructing floating-point number or format conversion from floating-point number to integer, and the pipeline decode stage refers to the conversion flag to input data, integer to floating-point number, or One or more first format converters for converting the format from floating-point number to integer and creating the input of the execution stage are provided. In the write-back stage of the pipeline, the arithmetic unit of the execution stage is referred to the conversion flag. The result of the operation is converted from integer to floating-point number or floating-point number to integer, and the output data of the write-back stage is converted. In which a second format conversion unit for generating input data for execution stage for data and forwarding.
The invention according to claim 2 is an arithmetic processing unit for servo motor control that performs floating-point arithmetic in accordance with IEEE754 in addition to integer arithmetic, and is an integer to floating-point number or a floating-point number to an integer. The conversion flag is provided with an operand encoded with a condition for format conversion to, and instructing format conversion from an integer to a floating-point number or from a floating-point number to an integer by decoding an operation code in a pipeline decoding stage Is generated.
The invention according to claim 3 uses the arithmetic processing device with a floating-point number arithmetic function as an arithmetic processing device of a servo motor control device.

According to the first aspect of the present invention, format conversion can be realized for all combinations of input data and calculation results. For this reason, it is possible to execute a control operation executed by mixing integers and floating-point numbers without reducing the operation performance. Furthermore, since the conversion flag can be created by checking the variable, for example, it is also possible to easily cope with a high-level language such as C language.
According to the second aspect of the present invention, format conversion can be realized for all combinations of input data and calculation results. For this reason, it is possible to execute a control operation executed by mixing integers and floating-point numbers without reducing the operation performance. Furthermore, since the conversion flag can be created by checking the variable, for example, it is also possible to easily cope with a high-level language such as C language.
According to the third aspect of the present invention, it is possible to improve the control performance of the servo device because no unnecessary time is generated for format conversion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an arithmetic processing unit for executing floating point number arithmetic operations according to the present invention. In FIG. 1, the arithmetic unit 16 of the arithmetic processing unit 2 performs a 2-input 1-output operation. For this reason, in this embodiment, the conversion flag 11 has a total of 3 bits, one bit for input and one bit for output. The fetch stage 6 fetches the instruction 5 stored in the instruction memory 3. The instruction is encoded with an opcode 10, a conversion flag and an operand 12. In order to perform pipeline processing, the fetched instruction is latched by FF and output to the decode stage 7. In the decoding stage, a conversion flag for input is input to the format conversion unit 131. The format conversion unit performs format conversion when the conversion flag is valid, but does not perform format conversion when it is invalid. The register 4 becomes an input to the format conversion unit provided in the fetch stage. The fetch stage data is latched by FF and output to the execution stage 8. In the execution stage, an operation is performed using two input data, and an operation result is generated. The execution stage data is latched by FF and output to the write back stage 9. In the write-back stage, an output conversion flag and an operation result are input to the format conversion unit 17. If the conversion flag is valid, format conversion is performed. If the conversion flag is invalid, format conversion is not performed. The output of the format conversion unit in the write-back stage is finally written into the register. Further, the output of the format conversion unit in the write-back stage is used for forwarding. Forwarding is a bypass circuit provided so that data to be written back can be used immediately by the next instruction.
FIG. 7 is a detailed block diagram of the format conversion unit. Since the format converters 13, 14, and 17 have basically the same configuration, the format converter 13 will be described. The format conversion unit 13 includes an input selector 30, a floating point number generation unit 31, an integer generation unit 37, and an output selector 42. The input selector 30 selects the operand 12 latched by FF and the output of the register 5 by the operation code 10 latched by FF. The opcode selects an operand for an immediate instruction and a register for any other instruction.
The floating-point number generation unit that converts an integer into a floating-point number includes an integer adjustment unit 32, a code generation unit 33, an exponent generation unit 34, a mantissa generation unit 35, and a floating-point number encoding unit 36. The integer adjustment unit calculates the highest 1 position for determining the location of the floating point (S1 in FIG. 2). The code generation unit uses the most significant bit of the selector output as a code (S2 in FIG. 2). The exponent generation unit determines the exponent from the highest 1 position excluding the sign (S3 in FIG. 2). This can be obtained by adding the most significant 1 position to the offset 127. The mantissa generation unit determines the mantissa by using the right side of the most significant 1 position excluding the sign. (S4 in FIG. 2). The floating point encoder encodes the output of the code generator at the top, the output of the exponent generator below it, and the output of the mantissa generator below it (S5 in FIG. 2). Generate floating point numbers.
The integer conversion unit that converts a floating-point number into an integer includes a code generation unit 38, an exponent check unit 39, a mantissa adjustment unit 40, and an integer encoding unit 41. The exponent inspection unit inspects whether the exponent is within a range represented by an integer (S7 in FIG. 3). The mantissa adjustment unit adds 1 to the most significant mantissa (S6 in FIG. 3). If the exponent is in the range represented by an integer with respect to the mantissa with 1 added, the mantissa is shifted by the exponent to make an unsigned integer (S8 in FIG. 3). At this time, the offset 127 is subtracted from the index. The code generator uses the most significant bit of the selector output to add the sign bit to the most significant (S9 in FIG. 3). When the exponent is within the range represented by an integer, the integer encoding unit encodes the output of the mantissa adjustment unit in the lower order and the output of the mantissa adjustment unit as an integer. If the exponent is out of the range represented by an integer, an unsigned integer for error is generated (S10 in FIG. 3) and output.
The output selector 42 receives the output of the floating-point generator, the output of the integer generator, and the output of the selector 30, and selects the output by the conversion flag 11 latched at FF. If the conversion flag converts an integer to a floating-point number, select the output of the floating-point number generator, and if the conversion flag converts a floating-point number to an integer, select the output of the integer generator. When the conversion flag is not converted, the output of the selector 30 is selected and used as the output of the selector 42.
Since the format conversion unit can be composed of a shifter and a selector, the number of logical stages can be reduced compared to the number of stages required for execution stage calculations. Therefore, even if a format conversion circuit is mounted in the decode stage or write back stage, it is not necessary to reduce the operating frequency of the pipeline clock.
In pipeline processing, since the execution stage performs complex processing, the number of stages of combinational circuits becomes deeper than other stages, and the time required for processing increases, and the clock that operates the pipeline executes the execution stage. Determined by time. Therefore, the decoding stage and the write back stage have a sufficient execution time, and format conversion can be executed in parallel with the original decoding and write back.
FIG. 10 shows an example in which an integer is converted in format, added as a floating-point number, and converted into an integer again.
In this description, “f” written after the period after the LD instruction is a conversion flag indicating that an integer is converted to a floating-point number. Also, “d” written after the period after the ST instruction is a conversion flag indicating that a floating-point number is converted to an integer.
Further, when the FADD instruction can use a memory as an operand, only an arithmetic instruction is used as shown in FIG.
In this description, “f1”, “f2”, and “d3” written after the period after the FADD instruction are conversion flags. “F1” indicates that an integer is converted to a floating-point number for operand 1 (INT_D1), “f2” indicates that an integer is converted to a floating-point number for operand 2 (INT_D2), and “d3 "" Indicates that floating-point numbers are converted to integers for operand 3 (INT_D3).

FIG. 2 is a flowchart of the arithmetic processing unit that executes the floating point number arithmetic operation according to the present invention, and describes the conversion from integer to floating point number executed by the format conversion unit. To convert an integer to a floating point number, perform the following five steps:

Step 1: Calculate the highest 1 position to determine the floating point location S1
Step 2: For signed integers, the most significant bit is the sign S2
Step 3: Determine the exponent from the highest 1 position excluding the sign S3
Step 4: Determine the mantissa using the right side of the highest 1 position excluding the sign S4
Step 5: Create floating-point number using sign, exponent and mantissa S5

FIG. 3 is a flowchart of the arithmetic processing unit that executes the floating point number arithmetic operation according to the present invention, and describes the conversion from the floating point number to the integer executed by the format conversion unit. To convert from a floating point number to an integer, perform the following three steps:

Step 1: Add 1 to the beginning of the mantissa S6
Step 2: Check whether the exponent is within the range represented by an integer S7
Step 2.1: Create an unsigned integer by shifting the mantissa by an exponent if it is within range S8
Step 2.2: Create an unsigned integer for error because it is out of range S10
Step 3: Add a sign bit to the beginning to make a signed integer S9

Floating point numbers can handle numbers larger than integers, so if they are outside the range of integers, it is an overflow and must be an error. At this time, for an unsigned integer for error, for example, if it is a 32-bit integer, it is good to use 0x80000000 in which all 31 bits except the sign are 1.

FIG. 4 is a block diagram of an arithmetic processing unit for executing the floating point number arithmetic operation of the present invention. The difference from the first embodiment is that the instruction 5 includes the operation code 10 encoded in the format conversion, and the decoder 18 that decodes the operation code 10 in the fetch stage 6, and the conversion flag 11 and the operation code 19 are set at the decoder output. It is a point to generate. In an operation with two input data and one output data, there is one operation type, but there are eight combinations of format conversion, so there are eight instructions. The decoder decodes this instruction and generates an operation code 19 and a conversion flag 11.
FIG. 12 shows an example in which an integer is converted in format, added as a floating-point number, and converted into an integer again.
In this description, the LDF instruction is an instruction indicating that an integer is converted to a floating-point number at the time of loading. The STD instruction is also an instruction indicating that a floating point number is converted to an integer at the time of storing.
Further, when the FADD instruction can use a memory as an operand, only an operation instruction is provided as shown in FIG.
In this description, the FADDf1f2d3 instruction is a conversion instruction. Indicates that integers are converted to floating-point numbers for operand 1 (INT_D1) and operand 2 (INT_D2), and floating-point numbers are converted to integers for operand 3 (INT_D3).

  FIG. 5 is a block diagram of an arithmetic processing unit that executes floating point number arithmetic and a servo device using the arithmetic processing unit. The servo device 1 includes an arithmetic processing unit 2 that executes control calculation, a power unit that generates a motor current to the servo motor 24, an ADC 21 that AD converts the output of the power unit and interfaces with the arithmetic processing unit, an encoder 24, It consists of an encoder IF 22 that interfaces. Since the feedback value input from the ADC or encoder IF is an integer, the arithmetic processing unit executes a control operation with a mixture of floating point numbers and integers. For this reason, format conversion between a floating point number and an integer is indispensable, and unnecessary time is not required for format conversion, so that the control performance of the servo device can be improved.

1 is a block diagram of an arithmetic processing unit that performs floating-point arithmetic operations according to a first embodiment of the present invention. The flowchart figure of the arithmetic processing unit which performs floating point number arithmetic which shows 1st execution example of this invention The flowchart figure of the arithmetic processing unit which performs floating point number arithmetic which shows 1st execution example of this invention The block diagram of the arithmetic processing unit which performs the floating point number calculation which shows 2nd Example Block diagram of an arithmetic processing unit for executing floating point number arithmetic and a servo device equipped with the same according to a third embodiment A block diagram of an arithmetic processing unit that executes conventional floating-point number arithmetic Detailed block diagram of format converter of first embodiment Description example of instructions for format conversion by format conversion instructions (prior art) Example of instruction description for arithmetic processing unit with format conversion function (prior art) Description example 1 of operation instruction in the case of the first embodiment Description example 2 of operation instruction in the case of the first embodiment Description example 1 of the operation instruction in the case of the second embodiment Description example 2 of operation instruction in the case of the second embodiment

Explanation of symbols

1 Servo device
2 Arithmetic processing unit
3 Instruction memory
4 instructions
5 registers
6 fetch stages
7 Decode stage, execution stage, write back stage, opcode, conversion flag, operand, format converter
14 Format converter
15 Selector
16 Calculator
17 Format converter
18 Decoder
19 Opcode
20 Power section
21 ADC
22 Encoder IF
23 Servo motor, Encoder, Selector, Floating point number generator, Integer adjuster, Sign generator, Exponent generator, Mantissa generator, Floating point encoder, Integer generator, Sign generator, Exponent checker, Mantissa Adjustment unit, integer coding unit, selector
100 math processor
101 Control register section
102 Conversion unit
103 Inverse converter
104 Conversion control bit
105 Conversion status bit
106 Limit section
107 Limit control bit
108 Limit data
109 AND1
110 Internal data bus
111 Local data bus

Claims (3)

  An arithmetic processing unit for servo motor control that performs floating-point arithmetic conforming to IEEE 754 in addition to integer arithmetic, from an integer to a floating-point number or a floating-point number for input and output data indicated by an operand A conversion flag for instructing format conversion to an integer is provided in the instruction, and the input data is converted from an integer to a floating-point number or from a floating-point number to an integer by referring to the conversion flag in the pipeline decoding stage. One or more first format conversion units for creating the execution stage input are provided, and the calculation result of the execution stage arithmetic unit is converted from an integer to a floating-point number by referring to the conversion flag in the pipeline write-back stage. Or format conversion from floating-point number to integer, output data and forwardin of write-back stage An arithmetic processing unit with a floating-point number arithmetic function for servo motor control, comprising: a second format conversion unit that creates input data of an execution stage for operation.   An arithmetic processing unit for servo motor control that performs floating-point arithmetic conforming to IEEE 754 in addition to integer arithmetic, and an operand in which a format conversion condition from integer to floating-point number or floating-point number to integer is encoded The conversion flag is generated by instructing format conversion from an integer to a floating-point number or from a floating-point number to an integer by decoding an opcode at a decoding stage of a pipeline. Arithmetic processing device with floating-point arithmetic function for servo motor control as described.   A servo motor control device using the arithmetic processing device with a floating-point arithmetic function for servo motor control.

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