JP2010141421A - Surface mount crystal oscillator - Google Patents

Surface mount crystal oscillator Download PDF

Info

Publication number
JP2010141421A
JP2010141421A JP2008313464A JP2008313464A JP2010141421A JP 2010141421 A JP2010141421 A JP 2010141421A JP 2008313464 A JP2008313464 A JP 2008313464A JP 2008313464 A JP2008313464 A JP 2008313464A JP 2010141421 A JP2010141421 A JP 2010141421A
Authority
JP
Japan
Prior art keywords
chip
terminal
recess
container body
crystal oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008313464A
Other languages
Japanese (ja)
Inventor
Yukihiro Okajima
幸弘 岡島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Dempa Kogyo Co Ltd
Original Assignee
Nihon Dempa Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Dempa Kogyo Co Ltd filed Critical Nihon Dempa Kogyo Co Ltd
Priority to JP2008313464A priority Critical patent/JP2010141421A/en
Publication of JP2010141421A publication Critical patent/JP2010141421A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16153—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/16155—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H01L2224/16157—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface mount oscillator of which height can be reduced and stray capacitance is small. <P>SOLUTION: In a surface mount crystal oscillator, a recessed vessel body 1 in which a recess is provided on an inner bottom surface stores an IC chip 2 in which an oscillation circuit is integrated, and the periphery of a crystal chip 3 to which an extraction electrode is extended is fixed to the inner-wall step part of the vessel body 1. In this case, an IC terminal 6 of the IC chip 2 stored in the recess is provided on a side, and is electrically joined while facing a terminal electrode 8 provided on the inner peripheral surface of the recess. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は表面実装用の水晶発振器（以下、表面実装発振器とする）を技術分野とし、特に側面にＩＣ端子を有するＩＣチップを容器本体に収容した表面実装発振器に関する。   The present invention relates to a surface mount crystal oscillator (hereinafter referred to as a surface mount oscillator), and more particularly to a surface mount oscillator in which an IC chip having an IC terminal on a side surface is accommodated in a container body.

（発明の背景）
表面実装発振器は小型・軽量であることから、特に携帯電話に代表される携帯型の電子機器に周波数及び時間の基準源として広く用いられている。そして、近年では電子機器の小型化に伴い、表面実装発振器に対する小型化の要求が一層強まっている。このようなものの一つに、容器本体に水晶片及びＩＣチップを収容して、金属カバーで密閉封入した表面実装発振器がある。 (Background of the Invention)
Since the surface-mounted oscillator is small and light, it is widely used as a frequency and time reference source, particularly in portable electronic devices typified by cellular phones. In recent years, with the miniaturization of electronic devices, the demand for miniaturization of surface mount oscillators has been further increased. One of such devices is a surface mount oscillator in which a crystal piece and an IC chip are accommodated in a container body and hermetically sealed with a metal cover.

（従来技術の一例）
第４図は一従来例を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）はＩＣチップの平面図、同図（ｃ）は水晶片の平面図である。 (Example of conventional technology)
FIG. 4 is a diagram for explaining a conventional example. FIG. 4A is a sectional view of a surface mount oscillator, FIG. 4B is a plan view of an IC chip, and FIG. 4C is a plan view of a crystal piece. is there.

特許文献１に従来技術として示される表面実装発振器は、容器本体１にＩＣチップ２と水晶片３とを収容し、容器本体１の開口端面となる枠壁上面に設けられた金属リング４に金属カバー５を接合してなる。容器本体１は底壁１ａ及び下枠壁１ｂ、上枠壁１ｃからなり、凹部及び段部を有して、多層構造としたセラミックの焼成によって形成される。   A surface-mount oscillator disclosed as a conventional technique in Patent Document 1 contains an IC chip 2 and a crystal piece 3 in a container body 1, and a metal ring 4 provided on the upper surface of a frame wall serving as an opening end surface of the container body 1. The cover 5 is joined. The container body 1 includes a bottom wall 1a, a lower frame wall 1b, and an upper frame wall 1c. The container body 1 is formed by firing a ceramic having a concave portion and a stepped portion and having a multilayer structure.

ＩＣチップ２は発振回路を構成する増幅器等の各素子を集積し、ＩＣ端子６を回路機能面としての一主面に有する。そして、容器本体１の凹部底面に、ＩＣチップ２の一主面側が例えばバンプ７を用いた超音波熱圧着によって固着される（所謂フリップチップボンディング）。これにより、底壁１ａに形成された端子電極８とＩＣ端子６とが電気的に接続する。そして、ＩＣチップ２の各ＩＣ端子６（水晶端子となるＩＣ端子６を除く）は、導電路９を経由して容器本体１の外底面の４隅に形成された実装端子１０に電気的に接続する。   The IC chip 2 integrates each element such as an amplifier constituting an oscillation circuit, and has an IC terminal 6 on one main surface as a circuit function surface. Then, one main surface side of the IC chip 2 is fixed to the bottom surface of the concave portion of the container body 1 by, for example, ultrasonic thermocompression using bumps 7 (so-called flip chip bonding). Thereby, the terminal electrode 8 formed in the bottom wall 1a and the IC terminal 6 are electrically connected. Each IC terminal 6 (except for the IC terminal 6 serving as a crystal terminal) of the IC chip 2 is electrically connected to mounting terminals 10 formed at the four corners of the outer bottom surface of the container body 1 via the conductive path 9. Connecting.

水晶片３は両主面の励振電極１１ａから例えば一端部両側に引出電極１１ｂを延出する。引出電極１１ｂを延出した一端部両側は導電性接着剤１２によって段部に固着し、下枠壁１ｂの上面（段部上面）に形成した一対の水晶保持端子１３に電気的・機械的に接続する。一対の水晶保持端子１３はＩＣチップ２の水晶端子となるＩＣ端子６に電気的に接続する。   The quartz crystal piece 3 extends, for example, extraction electrodes 11b on both sides of one end from the excitation electrodes 11a on both main surfaces. Both ends of one end of the extraction electrode 11b are fixed to the step by the conductive adhesive 12, and electrically and mechanically connected to a pair of crystal holding terminals 13 formed on the upper surface (upper surface of the step) of the lower frame wall 1b. Connecting. The pair of crystal holding terminals 13 are electrically connected to the IC terminal 6 that becomes the crystal terminal of the IC chip 2.

金属カバー５はシーム溶接やビーム溶接等によって、容器本体１の開口端面に設けられた金属リング４に接合される。なお、金属カバー５は実装端子１０中のアース端子に図示しないビアホール等を経て電気的に接続する。そして、これらによる表面実装発振器は、例えば携帯機器のセット基板に高熱炉を搬送しての半田等によって表面実装される。
特開２００７−２７４７２９号公報（「従来技術の一例」参照） 特開２００１−６８５１３号公報 The metal cover 5 is joined to the metal ring 4 provided on the opening end surface of the container body 1 by seam welding, beam welding or the like. The metal cover 5 is electrically connected to a ground terminal in the mounting terminal 10 through a via hole (not shown). The surface-mounted oscillators based on these are surface-mounted by, for example, soldering a high-temperature furnace transported to a set board of a portable device.
Japanese Unexamined Patent Publication No. 2007-274729 (see “Example of Prior Art”) JP 2001-68513 A

（従来技術の問題点）
しかしながら、上記構成の表面実装発振器では、ＩＣチップ２と底壁１ａの間にバンプ７があるため、低背化が妨げられるという問題があった。また、ＩＣチップ２の回路機能面には各ＩＣ端子６が近接して配置されることから浮遊容量を生じる。これにより、水晶発振器の発振特性特に発振周波数に影響を与えるという問題があった。 (Problems of conventional technology)
However, the surface mount oscillator having the above-described configuration has a problem in that a reduction in height is hindered because the bump 7 is provided between the IC chip 2 and the bottom wall 1a. Further, since each IC terminal 6 is arranged close to the circuit function surface of the IC chip 2, stray capacitance is generated. As a result, there is a problem in that it affects the oscillation characteristics of the crystal oscillator, particularly the oscillation frequency.

（発明の目的）
本発明は、低背化が可能であって浮遊容量の小さい表面実装発振器の提供を目的とする。 (Object of invention)
It is an object of the present invention to provide a surface mount oscillator that can be reduced in height and has a small stray capacitance.

本発明は、特許請求の範囲（請求項１）に示したように、凹状として内底面に凹所が設けられた容器本体に発振回路を集積化したＩＣチップを収容して、前記容器本体の内壁段部に引出電極の延出した水晶片の外周部を固着した表面実装用の水晶発振器において、前記凹所に収容された前記ＩＣチップのＩＣ端子は側面に設けられて、前記ＩＣ端子は前記凹所の内周面に設けられた端子電極と面対向して電気的に接合した構成とする。   According to the present invention, as shown in the claims (Claim 1), an IC chip in which an oscillation circuit is integrated is accommodated in a container body having a concave shape on the inner bottom surface thereof. In a surface-mount crystal oscillator in which an outer peripheral portion of a crystal piece with an extraction electrode extending is fixed to an inner wall step, an IC terminal of the IC chip housed in the recess is provided on a side surface, and the IC terminal is The terminal electrode provided on the inner peripheral surface of the recess is electrically bonded to face to face.

このような構成であれば、ＩＣチップは側面のＩＣ端子が凹所の内周面の端子電極と電気的に接続することから、低背化が可能である。また、ＩＣチップの各側面にＩＣ端子を分散して形成できるため、各ＩＣ端子間の距離を確保できる。したがって、浮遊容量の影響を小さくすることが可能である。   With such a configuration, the IC chip on the side surface can be reduced in height because the IC terminal on the side surface is electrically connected to the terminal electrode on the inner peripheral surface of the recess. In addition, since the IC terminals can be distributed and formed on each side surface of the IC chip, the distance between the IC terminals can be secured. Therefore, the influence of stray capacitance can be reduced.

（実施態様項）
本発明の請求項２では、請求項１において、前記ＩＣチップにおける回路機能面が形成された一主面に対する反対面が前記凹所の内底面に面接した構成とする。これにより、請求項１での構成をさらに明確にする。 (Embodiment section)
According to a second aspect of the present invention, in the first aspect, the surface opposite to the one main surface on which the circuit function surface of the IC chip is formed is in contact with the inner bottom surface of the recess. Thereby, the structure in Claim 1 is further clarified.

本発明の請求項３では、前記ＩＣチップが前記凹所の内底面に接着剤で接合された構成とする。これにより、ＩＣチップと容器本体との接合強度を確保できる。   According to a third aspect of the present invention, the IC chip is bonded to the inner bottom surface of the recess with an adhesive. Thereby, the joint strength between the IC chip and the container body can be secured.

（第１実施形態、請求項１、２に相当）
第１図は本発明の第１実施形態を説明する表面実装発振器の図で、同図（ａ）は断面図であり、同図（ｂ）はＩＣチップの斜視図、同図（ｃ）は容器本体の平面図である。なお、従来例と同一部分には同番号を付与してその説明は簡略又は省略する。 (First embodiment, equivalent to claims 1 and 2)
FIG. 1 is a diagram of a surface-mount oscillator for explaining a first embodiment of the present invention. FIG. 1 (a) is a sectional view, FIG. 1 (b) is a perspective view of an IC chip, and FIG. It is a top view of a container main body. In addition, the same number is attached | subjected to the same part as a prior art example, and the description is simplified or abbreviate | omitted.

第１実施形態の表面実装発振器は、容器本体１にＩＣチップ２と水晶片３とを収容し、容器本体１の開口端面に設けた金属リング４に金属カバー５を接合してなる。容器本体１は底壁１ａ、下枠壁１ｂ及び上枠壁１ｃからなり凹部及び段部を有する。これらは、多層構造としたセラミックの焼成によって形成される。   The surface-mount oscillator according to the first embodiment is formed by housing an IC chip 2 and a crystal piece 3 in a container body 1 and joining a metal cover 5 to a metal ring 4 provided on the opening end surface of the container body 1. The container body 1 includes a bottom wall 1a, a lower frame wall 1b, and an upper frame wall 1c, and has a recess and a step. These are formed by firing a ceramic having a multilayer structure.

ＩＣチップ２は、少なくとも発振回路を構成する増幅器等の各素子を集積しており、例えばＩＣウェハにスルーホール加工による貫通電極を設けて個々のＩＣチップに分割して形成される各種のＩＣ端子６が側面に設けられている（特許文献２参照）。そして、ＩＣチップ２は、回路機能面が形成された一主面に対する反対面が前記凹所の内底面に面接して収容される。また、容器本体１における下枠壁１ｂの内側面には、ＩＣ端子６に対応して端子電極８が形成される。そして、ＩＣ端子６とこれに対応する端子電極８とは導電性接着剤１４を用いて電気的・機械的に接合する。   The IC chip 2 integrates at least each element such as an amplifier that constitutes an oscillation circuit. For example, various IC terminals that are formed by dividing through each IC chip by providing a through-electrode by through-hole processing on an IC wafer. 6 is provided on the side surface (see Patent Document 2). The IC chip 2 is accommodated in such a manner that the surface opposite to the one main surface on which the circuit function surface is formed is in contact with the inner bottom surface of the recess. A terminal electrode 8 is formed on the inner side surface of the lower frame wall 1 b in the container body 1 corresponding to the IC terminal 6. The IC terminal 6 and the corresponding terminal electrode 8 are electrically and mechanically joined using the conductive adhesive 14.

水晶片３の引出電極１１ｂを延出した一端部両側を、導電性接着剤１２によって段部に固着し、下枠壁１ｂに形成した一対の水晶保持端子１３に電気的・機械的に接続する。そして、一対の水晶保持端子１３は、下枠壁１ｂの上面に形成された導電路９を経由して、ＩＣチップ２の水晶端子となるＩＣ端子６（ａｂ）に対応する端子電極８（ａｂ）に電気的に接続する。これにより、水晶片３とＩＣチップ２とが電気的に接続する。   Both ends of one end portion of the crystal piece 3 where the extraction electrode 11b is extended are fixed to the step portion by the conductive adhesive 12, and are electrically and mechanically connected to a pair of crystal holding terminals 13 formed on the lower frame wall 1b. . The pair of crystal holding terminals 13 are connected to terminal electrodes 8 (ab) corresponding to the IC terminals 6 (ab) serving as crystal terminals of the IC chip 2 through the conductive paths 9 formed on the upper surface of the lower frame wall 1b. ) Electrically connected. Thereby, the crystal piece 3 and the IC chip 2 are electrically connected.

また、ＩＣ端子６（ｃ〜ｆ）に対応する端子電極８（ｃ〜ｆ）は、底壁１ａ上面に形成された導電路９及び底壁１ａの外側面における４角部に形成された導電路９を経由して容器本体１の外底面の４隅に形成された実装端子１０に電気的に接続する。これにより、ＩＣチップ２と実装端子１０とが電気的に接続する。   Further, the terminal electrodes 8 (cf) corresponding to the IC terminals 6 (cf) are electrically conductive paths 9 formed on the upper surface of the bottom wall 1a and conductive materials formed on the four corners on the outer surface of the bottom wall 1a. Electrical connection is made to mounting terminals 10 formed at the four corners of the outer bottom surface of the container body 1 via the path 9. Thereby, the IC chip 2 and the mounting terminal 10 are electrically connected.

このようなものでは、先ず、従来例と同様に容器本体１を形成する。そして、セラミックからなる下枠壁１ｂに予め水晶保持端子１３及び導電路９、端子電極８の下地をタングステンの印刷によって形成する。また、セラミックからなる底壁１ａにも予め導電路９及び実装端子１０の下地をタングステンの印刷によって形成する。そして、底壁１ａ、下枠壁１ｂ及び上枠壁１ｃを積層・焼成して容器本体１を形成する。   In such a case, first, the container body 1 is formed as in the conventional example. Then, the base of the crystal holding terminal 13, the conductive path 9, and the terminal electrode 8 is formed in advance on the lower frame wall 1b made of ceramic by printing tungsten. In addition, the conductive path 9 and the base of the mounting terminal 10 are formed in advance on the bottom wall 1a made of ceramic by printing tungsten. And the bottom wall 1a, the lower frame wall 1b, and the upper frame wall 1c are laminated | stacked and baked, and the container main body 1 is formed.

その後、電解メッキ又は無電解メッキによって外表面に露出した前記の下地に例えばＮｉ及びＡｕ膜を順次に形成して、水晶保持端子１３及び端子電極８、実装端子１０、導電路９を設ける。次に、側面にＩＣ端子６を有するＩＣチップ２を容器本体１の内底面に設けられた凹所に収容する。このとき、ＩＣ端子６（ａ〜ｆ）と対応する端子電極８（ａ〜ｆ）とが対向するようにする。   Thereafter, for example, Ni and Au films are sequentially formed on the base exposed on the outer surface by electrolytic plating or electroless plating, and the crystal holding terminal 13, the terminal electrode 8, the mounting terminal 10, and the conductive path 9 are provided. Next, the IC chip 2 having the IC terminal 6 on the side surface is accommodated in a recess provided on the inner bottom surface of the container body 1. At this time, the IC terminal 6 (af) is made to face the corresponding terminal electrode 8 (af).

その後、導電性接着剤１４をＩＣ端子６（ａ〜ｆ）と対応する端子電極８（ａ〜ｆ）との間に滴下して、電気的・機械的に接続する。次に、導電性接着剤１２を用いて、水晶片３を水晶保持端子１３に電気的・機械的に接続する。最後に、容器本体１の開口端面となる枠壁１（ｂｃ）上面に設けられた金属リング４に金属カバー５をシーム溶接で接合して、水晶片３及びＩＣチップ２を密閉封入する。   Thereafter, the conductive adhesive 14 is dropped between the IC terminal 6 (af) and the corresponding terminal electrode 8 (af) to be electrically and mechanically connected. Next, the crystal piece 3 is electrically and mechanically connected to the crystal holding terminal 13 using the conductive adhesive 12. Finally, the metal cover 5 is joined to the metal ring 4 provided on the upper surface of the frame wall 1 (bc) serving as the opening end surface of the container body 1 by seam welding, and the crystal piece 3 and the IC chip 2 are hermetically sealed.

このような構成であれば、発明の効果の欄でも記載したように、ＩＣチップ２は側面のＩＣ端子６で端子電極８と電気的に接続しており、また、ＩＣチップ２は容器本体1の凹部における内底面に面接して配置される。したがって、容器本体１の凹部における内底面とＩＣチップ２とを、バンプを用いて接続する場合と比較して、表面実装発振器の低背化が可能である。また、ＩＣチップ２の各側面にＩＣ端子６を分散して形成できるため、各ＩＣ端子間の距離を確保できる。したがって、各ＩＣ端子６間の距離を確保できることから浮遊容量の影響を小さくすることが可能である。   In such a configuration, as described in the column of the effect of the invention, the IC chip 2 is electrically connected to the terminal electrode 8 by the IC terminal 6 on the side surface, and the IC chip 2 is connected to the container body 1. It is arranged in contact with the inner bottom surface of the recess. Therefore, the height of the surface-mounted oscillator can be reduced as compared with the case where the inner bottom surface of the concave portion of the container body 1 and the IC chip 2 are connected using bumps. Further, since the IC terminals 6 can be formed in a distributed manner on each side surface of the IC chip 2, a distance between the IC terminals can be secured. Therefore, since the distance between the IC terminals 6 can be ensured, the influence of stray capacitance can be reduced.

（第２実施形態、請求項１、２、３に相当）
第２図は本発明の第２実施形態を説明する表面実装発振器の断面図である。なお、前実施形態と同一部分には同番号を付与してその説明は簡略又は省略する。 (Embodiment 2 corresponds to claims 1, 2, and 3)
FIG. 2 is a cross-sectional view of a surface mount oscillator for explaining a second embodiment of the present invention. In addition, the same number is given to the same part as previous embodiment, and the description is simplified or abbreviate | omitted.

第２実施形態では、第１実施形態と同様にして凹状とした容器本体１に水晶片３とＩＣチップ２とを収容して密閉封入した表面実装発振器を形成する。そして、第２実施形態ではＩＣチップ２が容器本体１の内底面における凹所に導電性接着剤１５で接合される。これにより、ＩＣチップ２の固着強度を確保できる。   In the second embodiment, a surface-mount oscillator in which a crystal piece 3 and an IC chip 2 are accommodated and hermetically sealed is formed in a concave container body 1 in the same manner as in the first embodiment. In the second embodiment, the IC chip 2 is joined to the recess in the inner bottom surface of the container body 1 with the conductive adhesive 15. Thereby, the adhering strength of the IC chip 2 can be secured.

（他の事項）
前記各実施形態において、第３図（ａ）に示すように、半導体チップ１６を積層して形成したＩＣチップ２を用いても良い。半導体チップ１６は、半導体基板１７の一主面にＣＭＯＳトランジスタ等の回路素子１８が設けられて、前記一主面上にシリコン酸化膜１９を形成してなる。 (Other matters)
In each of the above embodiments, as shown in FIG. 3A, an IC chip 2 formed by stacking semiconductor chips 16 may be used. The semiconductor chip 16 includes a circuit element 18 such as a CMOS transistor provided on one main surface of a semiconductor substrate 17 and a silicon oxide film 19 formed on the one main surface.

シリコン酸化膜１９上には各種の配線２０や図示しないアルミニウム電極、抵抗等が設けられる。また、上下の半導体チップ１６と電気的に接続するための貫通電極２１が形成される。そして、側面にはＩＣ端子６となる電極が形成される。このような半導体チップ１６が接着層２２によって積層され、両主面に保護膜２３が設けられて、ＩＣチップ２が形成される。   Various wirings 20, aluminum electrodes (not shown), resistors, and the like are provided on the silicon oxide film 19. In addition, a through electrode 21 for electrical connection with the upper and lower semiconductor chips 16 is formed. And the electrode used as the IC terminal 6 is formed in the side surface. Such a semiconductor chip 16 is laminated by the adhesive layer 22, and the protective film 23 is provided on both main surfaces, so that the IC chip 2 is formed.

このようなＩＣチップ２は、回路素子１８やシリコン酸化膜１９が形成されて、分割線Ｘ−Ｘ、Ｙ−Ｙ上に貫通電極２４が設けられた第３図（ｂ）に示すシリコンウェハ２５を積層し、その後、分割して作成する。この結果、分割線上の貫通電極２４が、ＩＣチップ２の側面に形成されたＩＣ端子６となる。このようなＩＣチップ２であれば、従来例に示したＩＣチップ２のように、回路機能面にＩＣ端子６を設ける必要がないため、回路形成に利用できる面積を十分に確保できる。   Such an IC chip 2 has a silicon wafer 25 shown in FIG. 3 (b) in which circuit elements 18 and a silicon oxide film 19 are formed and through electrodes 24 are provided on the dividing lines XX and YY. Are laminated and then divided. As a result, the through electrode 24 on the dividing line becomes the IC terminal 6 formed on the side surface of the IC chip 2. With such an IC chip 2, there is no need to provide the IC terminal 6 on the circuit function surface as in the case of the IC chip 2 shown in the conventional example, so that a sufficient area can be secured for circuit formation.

前記各実施形態において、水晶片３の両端部を内壁段部に固着する構成としても良い。また、第２実施形態において、導電性接着剤１５に変えて絶縁性接着剤を用いてＩＣチップ２を底壁１ａに固着させた構成にしても良い。   In each of the embodiments, both ends of the crystal piece 3 may be fixed to the inner wall step. In the second embodiment, the IC chip 2 may be fixed to the bottom wall 1a using an insulating adhesive instead of the conductive adhesive 15.

本発明の第１実施形態を説明する表面実装発振器の図で、同図（ａ）は断面図であり、同図（ｂ）はＩＣチップの斜視図、同図（ｃ）は容器本体の平面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure of the surface mount oscillator explaining 1st Embodiment of this invention, The figure (a) is sectional drawing, The figure (b) is a perspective view of IC chip, The figure (c) is a plane of a container main body. FIG. 本発明の第２実施形態を説明する表面実装発振器の断面図である。It is sectional drawing of the surface mount oscillator explaining 2nd Embodiment of this invention. 本発明の他の事項を説明するＩＣチップの図で、同図（ａ）は断面図、同図（ｂ）はシリコンウェハの平面図である。It is a figure of the IC chip explaining the other matter of this invention, The figure (a) is sectional drawing, The figure (b) is a top view of a silicon wafer. 一従来例を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）はＩＣチップの平面図、同図（ｃ）は水晶片の平面図である。FIG. 1A is a cross-sectional view of a surface mount oscillator, FIG. 1B is a plan view of an IC chip, and FIG. 1C is a plan view of a crystal piece.

符号の説明Explanation of symbols

１ 容器本体、２ ＩＣチップ、３ 水晶片、４ 金属リング、５ 金属カバー、６ ＩＣ端子、７ バンプ、８ 端子電極、９ 導電路、１０ 実装端子、１１ａ 励振電極、１１ｂ 引出電極、１２ 導電性接着剤、１３ 水晶保持端子、１４ 導電性接着剤、１５ 導電性接着剤、１６ 半導体チップ、１７ 半導体基板、１８ 回路素子、１９ シリコン酸化膜、２０ 配線、２１ 貫通電極、２２ 接着層、２３ 保護膜、２４ 貫通電極、２５ シリコンウェハ。   DESCRIPTION OF SYMBOLS 1 Container body, 2 IC chip, 3 Crystal piece, 4 Metal ring, 5 Metal cover, 6 IC terminal, 7 Bump, 8 Terminal electrode, 9 Conductive path, 10 Mounting terminal, 11a Excitation electrode, 11b Extraction electrode, 12 Conductivity Adhesive, 13 Crystal holding terminal, 14 Conductive adhesive, 15 Conductive adhesive, 16 Semiconductor chip, 17 Semiconductor substrate, 18 Circuit element, 19 Silicon oxide film, 20 Wiring, 21 Through electrode, 22 Adhesive layer, 23 Protection Membrane, 24 through electrode, 25 silicon wafer.

Claims (3)

凹状として内底面に凹所が設けられた容器本体に発振回路を集積化したＩＣチップを収容して、前記容器本体の内壁段部に引出電極の延出した水晶片の外周部を固着した表面実装用の水晶発振器において、前記凹所に収容された前記ＩＣチップのＩＣ端子は側面に設けられて、前記ＩＣ端子は前記凹所の内周面に設けられた端子電極と面対向して電気的に接合したことを特徴とする表面実装用の水晶発振器。   A surface in which an IC chip in which an oscillation circuit is integrated is accommodated in a container body having a concave shape on the inner bottom surface, and the outer peripheral portion of the crystal piece with the lead electrode extended is fixed to the inner wall step portion of the container body. In the mounting crystal oscillator, an IC terminal of the IC chip housed in the recess is provided on a side surface, and the IC terminal is electrically opposed to a terminal electrode provided on an inner peripheral surface of the recess. Crystal oscillator for surface mounting, characterized by mechanical bonding. 請求項１において、前記ＩＣチップにおける回路機能面が形成された一主面に対する反対面が前記凹所の内底面に面接したことを特徴とする表面実装用の水晶発振器。   2. The surface-mount crystal oscillator according to claim 1, wherein a surface opposite to one main surface on which the circuit function surface of the IC chip is formed is in contact with an inner bottom surface of the recess. 請求項２において、前記ＩＣチップが前記凹所の内底面に接着剤で接合された表面実装用の水晶発振器。   3. The surface-mount crystal oscillator according to claim 2, wherein the IC chip is bonded to the inner bottom surface of the recess with an adhesive.
JP2008313464A 2008-12-09 2008-12-09 Surface mount crystal oscillator Pending JP2010141421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008313464A JP2010141421A (en) 2008-12-09 2008-12-09 Surface mount crystal oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008313464A JP2010141421A (en) 2008-12-09 2008-12-09 Surface mount crystal oscillator

Publications (1)

Publication Number Publication Date
JP2010141421A true JP2010141421A (en) 2010-06-24

Family

ID=42351183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008313464A Pending JP2010141421A (en) 2008-12-09 2008-12-09 Surface mount crystal oscillator

Country Status (1)

Country Link
JP (1) JP2010141421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014175998A (en) * 2013-03-12 2014-09-22 Kyocera Crystal Device Corp Crystal oscillator
JP2015220586A (en) * 2014-05-16 2015-12-07 京セラ株式会社 Board for mounting piezoelectric vibration element and piezoelectric device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014175998A (en) * 2013-03-12 2014-09-22 Kyocera Crystal Device Corp Crystal oscillator
JP2015220586A (en) * 2014-05-16 2015-12-07 京セラ株式会社 Board for mounting piezoelectric vibration element and piezoelectric device

Similar Documents

Publication Publication Date Title
JP5078512B2 (en) Crystal device
JP2006279872A (en) Piezoelectric vibrator, manufacturing method therefor, and manufacturing method of piezoelectric oscillator using the piezoelectric vibrator
JP2007158918A (en) Surface mount crystal oscillator
JP2007288268A (en) Crystal oscillator for surface mount
JP2009065334A (en) Surface-mount crystal oscillator
US7746184B2 (en) Bonding-type surface-mount crystal oscillator
JP4750177B2 (en) Crystal oscillator for surface mounting
JP2010141415A (en) Surface mount crystal oscillator and method of manufacturing the same
JP2008005088A (en) Package for piezoelectric vibrator and piezoelectric vibrator, and piezoelectric oscillator
JP2010200230A (en) Crystal oscillator for surface mounting
JP2010141421A (en) Surface mount crystal oscillator
JP2010171572A (en) Crystal oscillator for surface mounting
JP2007251601A (en) Small piezoelectric oscillator, and manufacturing method of small piezoelectric oscillator
JP2005268257A (en) Package for storing electronic component and electronic device
JP2009135562A (en) Crystal oscillator for surface mounting
JP6391235B2 (en) Crystal device
JP5489453B2 (en) Crystal oscillator for surface mounting
JP2010124165A (en) Surface mounted crystal oscillator
JP2010124022A (en) Temperature compensation crystal oscillator for surface mounting
JP2007142947A (en) Surface-mounting piezoelectric oscillator
JP4645393B2 (en) Surface mount type piezoelectric oscillator and electronic component unit
JP2005039791A (en) Temperature compensated crystal oscillator
JP2008017091A (en) Piezoelectric vibrator and piezoelectric oscillator
JP2005175520A (en) Piezoelectric vibrator
JP2007166130A (en) Oscillator ic chip and surface mount crystal oscillator using the same