JP2010141060A5 - - Google Patents

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Publication number
JP2010141060A5
JP2010141060A5 JP2008315108A JP2008315108A JP2010141060A5 JP 2010141060 A5 JP2010141060 A5 JP 2010141060A5 JP 2008315108 A JP2008315108 A JP 2008315108A JP 2008315108 A JP2008315108 A JP 2008315108A JP 2010141060 A5 JP2010141060 A5 JP 2010141060A5
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Prior art keywords
epitaxial wafer
temperature
epitaxial
susceptor
manufacturing
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JP2008315108A
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JP5378779B2 (en
JP2010141060A (en
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Priority to JP2008315108A priority Critical patent/JP5378779B2/en
Priority claimed from JP2008315108A external-priority patent/JP5378779B2/en
Priority to US12/632,032 priority patent/US9758871B2/en
Publication of JP2010141060A publication Critical patent/JP2010141060A/en
Publication of JP2010141060A5 publication Critical patent/JP2010141060A5/ja
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Claims (8)

実質的に水平状態に配されるサセプターに載置されたシリコンウェーハ基板の主表面にエピタキシャル層を成長させるエピタキシャルウェーハの製造方法において、
前記シリコンウェーハ基板の主表面に実際にエピタキシャル層を成長させる成層工程、を含み、
前記成層工程は、
前記エピタキシャル層の成長工程と、
前記エピタキシャル層を備えるエピタキシャルウェーハを冷却する冷却工程と、を含み、
前記冷却工程は、
該エピタキシャルウェーハの外周部の温度を求める工程と、
前記サセプターの温度を計測する工程と、
求められた前記外周部の温度と前記サセプターの温度との差が所定の範囲内となるように、少なくとも前記サセプター又は前記エピタキシャルウェーハを加熱できるヒータを制御する工程と、を含むことを特徴とするエピタキシャルウェーハの製造方法。 In an epitaxial wafer manufacturing method of growing an epitaxial layer on a main surface of a silicon wafer substrate placed on a susceptor arranged in a substantially horizontal state,
A stratification step of actually growing an epitaxial layer on the main surface of the silicon wafer substrate,
The stratification process includes
A growth step of the epitaxial layer;
Cooling the epitaxial wafer comprising the epitaxial layer, and
The cooling step includes
Determining the temperature of the outer periphery of the epitaxial wafer ;
Measuring the temperature of the susceptor;
And a step of controlling at least a heater capable of heating the susceptor or the epitaxial wafer so that a difference between the obtained temperature of the outer peripheral portion and the temperature of the susceptor falls within a predetermined range. Epitaxial wafer manufacturing method. 前記外周部の温度を求める工程は、前記エピタキシャルウェーハ基板の中央部の温度から外周部の温度を予測する予測方法によることを特徴とする請求項１に記載のエピタキシャルウェーハの製造方法。  The method for producing an epitaxial wafer according to claim 1, wherein the step of obtaining the temperature of the outer peripheral portion is based on a prediction method for predicting the temperature of the outer peripheral portion from the temperature of the central portion of the epitaxial wafer substrate. 前記予測方法は、予備工程において前記シリコンウェーハ基板の中央部の温度から外周部の温度を取得する方法であることを特徴とする請求項２に記載のエピタキシャルウェーハの製造方法。The epitaxial wafer manufacturing method according to claim 2, wherein the predicting method is a method of acquiring a temperature of an outer peripheral portion from a temperature of a central portion of the silicon wafer substrate in a preliminary process. 前記外周部の温度を求める工程は、前記エピタキシャルウェーハの外周部の温度を計測する工程を含むことを特徴とする請求項１に記載のエピタキシャルウェーハの製造方法。  The method for producing an epitaxial wafer according to claim 1, wherein the step of obtaining the temperature of the outer peripheral portion includes a step of measuring the temperature of the outer peripheral portion of the epitaxial wafer. 前記成長工程直後に前記冷却工程を所定の冷却速度以上で行うことを特徴とする請求項１から４のいずれかに記載のエピタキシャルウェーハの製造方法。 Method for manufacturing an epitaxial wafer according to any one of claims 1 to 4, characterized in that the cooling step after the growth step at a predetermined cooling rate higher. 前記冷却工程において、前記エピタキシャルウェーハは９００℃以上から冷却されることを特徴とする請求項１から５のいずれかに記載のエピタキシャルウェーハの製造方法。   The epitaxial wafer manufacturing method according to claim 1, wherein the epitaxial wafer is cooled from 900 ° C. or higher in the cooling step. 前記ヒータは、前記エピタキシャルウェーハの上方、及び／又は、前記サセプターの下方に配置されていることを特徴とする請求項１から６のいずれかに記載のエピタキシャルウェーハの製造方法。 The heater, the upper epitaxial wafer, and / or an epitaxial wafer manufacturing method according to any one of claims 1 6, characterized in that it is disposed below the susceptor. 前記冷却工程において、少なくとも前記エピタキシャルウェーハの上方又は前記サセプターの下方に配置されているヒータの出力を実質的に切ることを特徴とする請求項７に記載のエピタキシャルウェーハの製造方法。 8. The method of manufacturing an epitaxial wafer according to claim 7 , wherein, in the cooling step, the output of a heater disposed at least above the epitaxial wafer or below the susceptor is substantially cut off.
JP2008315108A 2008-12-10 2008-12-10 Epitaxial wafer manufacturing method Active JP5378779B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008315108A JP5378779B2 (en) 2008-12-10 2008-12-10 Epitaxial wafer manufacturing method
US12/632,032 US9758871B2 (en) 2008-12-10 2009-12-07 Method and apparatus for manufacturing epitaxial silicon wafer

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Application Number Priority Date Filing Date Title
JP2008315108A JP5378779B2 (en) 2008-12-10 2008-12-10 Epitaxial wafer manufacturing method

Publications (3)

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JP2010141060A JP2010141060A (en) 2010-06-24
JP2010141060A5 true JP2010141060A5 (en) 2012-02-02
JP5378779B2 JP5378779B2 (en) 2013-12-25

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Publication number Priority date Publication date Assignee Title
JP5646207B2 (en) * 2010-04-30 2014-12-24 株式会社ニューフレアテクノロジー Film forming apparatus and film forming method
JP6836965B2 (en) * 2017-06-23 2021-03-03 昭和電工株式会社 Film deposition equipment
JP2023097005A (en) * 2021-12-27 2023-07-07 株式会社Sumco Manufacturing method of epitaxial wafer and epitaxial wafer manufacturing device

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JPH06204143A (en) * 1992-12-28 1994-07-22 Hitachi Ltd Cvd equipment
JP3604425B2 (en) * 1994-08-09 2004-12-22 東芝機械株式会社 Vapor phase growth equipment
JP2000064029A (en) * 1998-08-20 2000-02-29 Toshiba Mach Co Ltd Temperature controlling mechanism in semiconductor producing device
JP2002289601A (en) * 2001-03-28 2002-10-04 Hitachi Kokusai Electric Inc Substrate processing apparatus and method
JP3922018B2 (en) * 2001-12-21 2007-05-30 株式会社Ｓｕｍｃｏ Vapor growth apparatus and temperature detection method for vapor growth apparatus
JP4059694B2 (en) * 2002-03-27 2008-03-12 株式会社日立国際電気 Substrate processing apparatus and semiconductor device manufacturing method
WO2005010970A1 (en) * 2003-07-28 2005-02-03 Hitachi Kokusai Electric Inc. Substrate processing apparatus and substrate processing method
JP4262763B2 (en) * 2006-08-02 2009-05-13 株式会社ニューフレアテクノロジー Semiconductor manufacturing apparatus and semiconductor manufacturing method

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