JP2010140268A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device for facilitating calculation of a writing time. <P>SOLUTION: A memory device has a memory 21 having a plurality of storage areas. A controller 22 has: a first mode, in which, when receiving writing data, the controller 22 can write the writing data in the storage areas while managing the correspondence among logical addresses of the writing data and the storage areas storing the writing data and can write the writing data having unspecified size in the storage areas without limiting an order of logical addresses, and stores the data which has not been an object to be written in a management unit storage area AU composed of a plurality of continuous storage areas; and a second mode in which the controller 22 writes a plurality of items of writing data having specified size in the storage areas in an order to increase each logical address and treats the data which has not been written in the management unit storage area as invalid data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory device, and more particularly to a memory device using a nonvolatile semiconductor memory.

  Currently, a memory device represented by a memory card using a nonvolatile semiconductor memory such as a flash memory is used as a recording medium for music data and video data. Memory devices often incorporate a controller for controlling the memory. The controller issues an instruction to write the write data assigned with the logical address requested from the file system of the host into which such a memory device is inserted into an unwritten storage area of the flash memory. The controller also manages the relationship between the logical address assigned to the data by the file system and the location of the storage area of the flash memory that stores this data.

  A typical example of a flash memory used for a memory device is a NAND flash memory. In the NAND flash memory, writing is performed in units called pages composed of a plurality of bits. Erasing can be performed only in units called blocks each composed of a plurality of pages.

  The user may be required to know the performance of the memory device through the host device. Such performance includes the recording speed of the memory device, the time required for recording, the recordable time, and the like. A technique for predicting these performances is described in JP-A-2006-178923 (Patent Document 1). This technique uses the following method.

  As described above, erasing can be performed only in a unit called a block composed of a plurality of pages. That is, the NAND flash memory cannot overwrite data. In order to update certain data in the memory, it is necessary to prepare a new block, copy data that is not updated therein, and write updated data. For this reason, in the flash memory, writing to consecutive pages where nothing has been written is fast, but writing to a block in which written pages and unwritten pages are mixed is slow. That is, the data writing speed varies depending on the distribution (fragmentation) of the write pages in the block. Using this, the recordable time of the memory device can be calculated from the number of blocks satisfying the write speed required by the application installed in the host device and storing the data in the memory device. I'm asking. However, in such a method using fragmentation, calculation of performance is complicated, and it takes a long time to execute. Therefore, there is a demand for a memory device that makes it possible to perform performance prediction more easily.

In addition, usage patterns of memory devices by users are diversified due to increase in memory capacity, performance improvement of memory devices, and diversification of contents that users want to record. For example, there has been a demand for recording two moving images such as two television programs in parallel, or shooting a still image while shooting a moving image. However, since data cannot be overwritten in the current flash memory, the above-mentioned data copy may be necessary. Since data copying takes a long time, writing with data copying is slow. For this reason, it is impossible to write a plurality of file data, particularly a plurality of file data in parallel to the memory device in real time in response to the above request.
JP 2006-178923 A

  The present invention is intended to provide a memory device that enables real-time recording of a plurality of streams by providing a memory device having a certain writing performance and facilitates calculation of writing time.

  A memory device according to an aspect of the present invention, when receiving a write data, a memory having a plurality of storage areas, and managing the correspondence between a logical address of the write data and the storage area for storing the write data It is possible to write data to the storage area and write write data of an unspecified size to the storage area without restriction of the logical address order, and within a management unit storage area composed of a plurality of continuous storage areas. It has a first mode for holding data that was not a write target, and a plurality of write data of a specific size are written to the storage area in the order of increasing logical addresses and written to the management unit storage area. And a controller having a second mode for handling missing data as invalid data. And wherein the door.

  A memory device according to an aspect of the present invention, when receiving a write data, a memory having a plurality of storage areas, and managing the correspondence between a logical address of the write data and the storage area for storing the write data A controller that writes data to the storage area, recognizes a logical address area composed of a plurality of consecutive logical addresses, and shifts to a real-time writable state upon receipt of a first command, the real-time writable When receiving the write request, the controller in the state transfers a plurality of write data to the work area temporarily prepared corresponding to the management unit storage area to which the logical address of the write data belongs. Write to the storage area in the work area in the order , Or write to the last of the storage area in the work area is completed, allocated to the logical address to the working area upon receipt of a second command, it is characterized.

  According to the present invention, it is possible to provide a memory device that facilitates the calculation of the write time.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary. However, it should be noted that the drawings are schematic.

  Hereinafter, a memory card, particularly an SD card will be described as an example of the memory device according to the embodiment of the present invention. However, any memory device having a memory as described below and a controller for controlling the memory is included in the scope of the present invention.

(First embodiment)
[1] Configuration The configuration of the memory card according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows main functional blocks of a memory card according to the first embodiment of the present invention. FIG. 1 also shows functional blocks of the host device connected to the memory card. Each functional block can be realized as hardware, computer software, or a combination of both. For this reason, in order to make it clear that each block is any of these, the following description will generally be made in terms of their functions. Whether such functionality is implemented as hardware or software depends upon the specific implementation or design constraints imposed on the overall system. Those skilled in the art can implement these functions in various ways for each specific embodiment, and any implementation technique is included in the scope of the present invention.

  A host device (hereinafter referred to as a host) 1 includes software 11 such as an application and an operating system. The software 11 is instructed by the user to write data to the memory card 2 and read data from the memory card 2. The software 11 instructs the file system 12 to write and read data. The file system 12 is a mechanism for managing file data recorded on a storage medium to be managed, records management information in a storage area of the storage medium, and manages file data using this management information. .

  The host 1 has an SD interface 13. The SD interface 13 includes hardware and software necessary for performing interface processing between the host 1 and the memory card 2. The host 1 communicates with the memory card 2 via the SD interface 13. The SD interface 13 defines various agreements necessary for communication between the host 1 and the memory card 2, and includes various command sets that can be mutually recognized with the SD interface 31 of the memory card 2 described later. . The SD interface 13 also includes a hardware configuration (pin arrangement, number, etc.) that can be connected to the SD interface 31 of the memory card 2.

  The memory card 2 includes a NAND flash memory 21 and a controller 22 for controlling the memory 21. When the memory card 2 is connected to the host 1 or inserted into the off-state host 1 and the host 1 is turned on, the memory card 2 receives the power supply and performs an initialization operation. Process according to access.

  The memory 21 stores data in a nonvolatile manner, and writes and reads data in units called pages composed of a plurality of memory cells. Each page is assigned a unique physical address. The memory 21 erases data in units called physical blocks (erase blocks) composed of a plurality of pages. A physical address may be assigned in units of physical blocks.

  The controller 22 manages the storage state of data in the memory 21. Storage state management refers to the relationship between which physical address page (or physical block) holds which logical address data, and which physical address page (or physical block) is erased (nothing written) Management of whether the data is not stored or has invalid data.

  The controller 22 includes an SD interface 31, a micro processing unit (MPU) 32, a read only memory (ROM) 33, a read only memory (RAM) 34, and a NAND interface 35.

  The SD interface 31 includes hardware and software necessary for performing interface processing between the host 1 and the controller 22, and, like the SD interface 13, defines an agreement that enables communication between the two and various types of software. It includes a set of commands and includes hardware configuration (pin placement, number, etc.). The memory card 2 (controller 22) communicates with the host 1 via the SD interface 31. The SD interface 31 includes a register 36.

  The MPU 32 controls the operation of the entire memory card 2. For example, when the memory card 2 receives power supply, the MPU 32 reads the firmware (control program) stored in the ROM 33 onto the RAM 34 and executes predetermined processing. The MPU 32 creates various tables (described later) on the RAM 34 in accordance with the control program, and executes predetermined processing on the memory 21 in accordance with commands received from the host 1.

  The ROM 33 stores a control program controlled by the MPU 32 and the like. The RAM 34 is used as a work area for the MPU 32 and temporarily stores control programs and various tables. As such a table, a conversion table (logical / physical table) of physical addresses of pages that actually store data having logical addresses assigned to data by the file system 12 is included. The NAND interface 35 performs an interface process between the controller 22 and the memory 21.

  The storage area in the memory 21 includes, for example, a system data area, a confidential data area, a protected data area, a user data area, and the like according to the type of data to be stored. The system data area is an area reserved in the memory 21 for the controller 22 to store data necessary for its operation. The confidential data area stores key information used for encryption and confidential data used for authentication, and cannot be accessed from the host 1. The protected data area stores important data and secure data. The user data area can be freely accessed and used by the host 1 and stores user data such as AV content files and image data. In the following description, when the description of the memory 21 is used to indicate the memory space of the memory 21, this description indicates the user data area. The controller 22 reserves a part of the user data area and stores control data (logical / physical table or the like) necessary for its own operation.

  As illustrated in FIG. 2, the register 36 includes various registers such as a card status register, CID, RCA, DSR, CSD, SCR, and OCR. These registers are limited in error information, individual number of memory card 2, relative card address, bus driving power of memory card 2, characteristic parameter value of memory card 2, data arrangement, and operating range voltage of memory card 2. This stores the operating voltage and the like.

  The register 36, for example, the CSD stores the class of the memory card 2, the time required for copying data, the AU size, and the like. A class is defined by a minimum writing speed guaranteed by a memory card belonging to a certain class. The highest writing speed is determined by class. Therefore, the host 1 can read the data indicating the AU size from the register 36 and use this information when managing the memory card 2. Also, the host 1 can read the data indicating the class from the register 36 and store the maximum data in the memory card 2. Can learn the write performance. In addition, performance performance information, for example, performance information described in JP-A-2006-178923 may be stored in the CSD.

  FIG. 3 shows the configuration of the memory space of the memory 21. As shown in FIG. 3, the memory 21 includes a normal memory area 41 and a page buffer 42. The memory area 41 includes a plurality of physical blocks BLK. Each physical block BLK is composed of a plurality of pages PG. Each page PG includes a plurality of memory cell transistors connected in series.

  Each memory cell includes a MOSFET (metal oxide semiconductor field effect transistor) having a so-called stacked gate structure. Each memory cell transistor changes the threshold voltage according to the number of electrons stored in the floating gate electrode, and stores information corresponding to the difference in the threshold voltage. The memory 21 may be configured so that the memory cell transistor can take two or more threshold voltage different states, that is, the memory cell can store multiple values (multi-bit).

  Control gate electrodes of memory cell transistors belonging to the same row are connected to the same word line. Select gate transistors are provided at both ends of memory cell transistors belonging to the same column and connected in series. One select gate transistor is connected to the bit line. Data writing and reading are performed for each set of memory cell transistors connected in series, and a storage area including the set of memory cell transistors corresponds to one page.

  In the example of FIG. 3, each page PG has, for example, 2112B, and each block 52 has, for example, 128 pages. Data is erased in units of blocks BLK. The page buffer 34 inputs / outputs data to / from the memory 21 and temporarily holds data. The data size that can be held by the page buffer 42 is, for example, 2112B (2048B + 64B), similar to the size of the page PG.

  As shown in FIG. 4 and as described above, the memory 21 writes and reads data in units of page PG, and erases data in units of blocks BLK. On the other hand, the file system 12 manages data in units of RU (recording units). That is, the file system 12 divides the data to be written requested by the software 11 into a plurality of portions having an appropriate size according to the size of the RU, and assigns a logical address to each portion. RU corresponds to a unit written by one multi-block write command. The file system 12 supplies the data assigned the unique logical address as write data to the memory card 2 following the write command. The controller 22 writes the write data assigned with the logical address to an appropriate page. The size of the RU is an integral multiple of the size of the page capacity. Therefore, the memory card 2 writes the write data having the size of RU to a plurality of pages having consecutive physical addresses. Since each RU corresponds to a unique logical address managed by the file system, assigning data to the RU is synonymous with assigning a logical address to the data. The file system 12 uses a table to manage the connection relation of each part of the divided data, and restores the original data by connecting the data parts using this connection relation. Further, the controller 22 manages the correspondence between the logical address and the address (physical address) of the page storing the data of the logical address by using a conversion table (logical / physical table).

  Further, the file system 12 performs management using the concept of AU (allocation unit) consisting of a set of a predetermined number of consecutive RUs belonging to a predetermined range. The controller 22 can recognize the AU separation by looking at the upper bits of the logical address of the data. The size of AU is an integral multiple of the capacity of a block (physical block). Thus, RU matches the size of a natural number of pages, and AU matches the size of a natural number of blocks. Therefore, in the following description, RU and AU are used as data reading / writing units in the memory card 2. That is, the term “RU” used in the description related to the memory card 2 means a plurality of continuous pages having the same size as the RU, and the term “AU” used in the description related to the memory card 2 is the same size as the AU. , Meaning a plurality of consecutive blocks. Specifically, the data assigned to the RU of the file system 12 by the file system 12 is written in a certain RU of the memory card 2, and the memory card 2 stores the RU (logical address) assigned to the data by the file system 12. The table manages the RUs in the memory 21 storing the write data.

[2] Operation [2-1] First Example Next, a part of the operation of the memory card 2 will be described with reference to FIGS. FIG. 5 is a transition diagram of modes that the memory card according to the first embodiment can take. As shown in FIG. 5, the memory card 2 has a random write mode and a sequential write mode, and the controller 22 operates according to the currently set mode among these two modes. The memory card 2 is in the random write mode when the power supply from the host 1 is started. When the memory card 2 is in the random write mode and receives a sequential write start command, the memory card 2 shifts to the sequential write mode. On the other hand, when the memory card 2 receives the sequential write end command while in the sequential write mode, the memory card 2 shifts to the random write mode. The SD interface 31 is configured to recognize a sequential write start command and a sequential write end command.

  Next, the random write mode will be described with reference to FIGS. 6 to 9 sequentially illustrate one state at the time of writing in the random writing mode. 6 to 9, the AU excluding the work AU represents the AU recognized by the file system 12, and also represents the AU storing the data in the AU in the memory card 2. ing.

  First, data 1 to data N are written in the first to NRU belonging to AU 1 in the memory card 2. In this state, the host 1 desires to write data 20 to data 22 in the fourth to sixth RUs of AU1. However, since the flash memory 21 cannot directly execute this update command by overwriting data, the following operation is performed. First, as shown in FIG. 7, the memory card 2 (controller 22) prepares an AU (work AU) for temporary work. Next, the memory card 2 copies data 1 to data 3 to the first to third RUs in the work AU that are the same as the RUs in which AU1 is not updated.

  As shown in FIG. 8, the memory card 2 writes data 20 to data 22 in the fourth to sixth RUs in the work AU that are the same as the update target RUs of AU1.

  As shown in FIG. 9, the memory card 2 copies the data 7 to data N of AU1 to the seventh to NRU of the work AU that is the same as the RU that is not updated of AU1, respectively. Next, the memory card 2 performs a closing process for the work AU1. The close process is to set the work AU to AU1, that is, to set the work AU as storing data in AU1 recognized by the file system 12 (rewrite the logical-physical table). is there. At the same time, the old AU1 is discarded. In other words, the old AU1 is handled as an AU having invalid data. Data in the old AU is erased at a predetermined timing and becomes a new unwritten AU.

  Next, the sequential write mode will be described with reference to FIGS. FIG. 10 shows a first example of commands and data exchanged between the host 1 and the memory card 2 before and after the sequential write mode. 11 to 14 sequentially show one state at the time of writing of the first example in the sequential writing mode. In FIG. 11 to FIG. 14, AUs excluding work AUs represent AUs recognized by the file system 12, and also represent AUs that store data in the AUs in the memory card 2. ing.

  First, the memory card 2 is in the random writing mode, and as shown in FIG. 11, data 1 to data 8 are written in the first to eighth RUs of AU1, and data 9 to data are stored in the first to eighth RUs of AU2. Data 16 is written. In this state, as shown in FIG. 10, the host 1 supplies a sequential write start command to the memory card 2. When this command is received, the memory card 2 shifts to the sequential write mode.

  As shown in FIG. 11, the host 1 desires to write data 20 to data 22 into the fourth to sixth RUs of AU1. That is, the host 1 desires to update the fourth to sixth RUs with the data 20 to the data 22. In order to perform this writing, as shown in FIG. 10, the host 1 supplies the memory card 2 with a write command and subsequently data 20 to data 22 associated with the fourth to sixth RUs of AU1. When this write request is received, the memory card 2 prepares a work AU1 for AU1 as shown in FIG. The work AU is composed only of RUs that do not store data, and is an AU that is temporarily used by the memory card 2 for internal processing. In the sequential write mode, the memory card 2 always prepares an unwritten work AU in response to a write request, and writes data to the work AU. At this stage, since the original AU1 for the work AU is still valid, even if a write error occurs for some reason, it is possible to restore the state before writing.

  In the sequential write mode, RU data that is not updated is not copied to the RU of the work AU. Therefore, as shown in FIG. 12, the memory card 2 writes data 20 to data 22 in the fourth to sixth RUs in the work AU, which are the same as the RUs in which data 20 to data 22 are written in AU1.

  Next, as shown in FIG. 12, the host 1 updates the data 7 and data 8 of the seventh and eighth RUs of AU1 with data 23 and data 24, and the data 9 to data of the first to third RUs of AU2. It is desired to update the data 11 with the data 25 to the data 27. In order to perform this update, as shown in FIG. 10, the host 1 sends a write command, data 23 associated with the seventh and eighth RUs of AU1, data 24, and first to third RUs of AU2 to the memory card 2. The data 25 to the data 27 associated with are supplied. When this write request is received, as shown in FIG. 13, the memory card 2 stores data 23 and data in the seventh and eighth RUs in the work AU, which are the same as the RUs in which data 23 and data 24 are written in AU1. Write 24 each. At this time, since the data is written in the last RU of the work AU1, as shown in FIG. 14, the memory card 2 performs a closing process on the work AU. Further, the memory card 2 prepares a new work AU for AU2.

  As shown in FIG. 15, the memory card 2 writes data 25 to data 27 in the first to third RUs in the work AU, which are the same as the RUs in which data 25 to data 27 are written in AU2.

  Since the write request is completed, the host 1 supplies a sequential write end command to the memory card 2 as shown in FIG. When this command is received, as shown in FIG. 15, the memory card 2 closes the work AU without copying the data 12 to data 16 written in the fourth to eighth RUs of the AU 2 to the work AU. Processing is performed, and then the random write mode is entered.

[2-2] Second Example Next, recording a plurality of file data in parallel by applying the first example will be described with reference to FIGS. FIG. 16 shows a second example of commands and data received by the memory card according to the first embodiment. FIGS. 17 to 21 sequentially show one state at the time of writing in the second example in the memory card 2 according to the first embodiment. In FIG. 17 to FIG. 21, AUs excluding the work AU represent AUs recognized by the file system 12, and also represent AUs that store data in the AUs in the memory card 2. ing. The second example relates only to the operation in the sequential write mode, and the other operations are the same as those in the first example.

  First, the memory card 2 is in the random write mode. In this state, as shown in FIG. 16, the memory card 2 shifts to the sequential write mode by the sequential write start command received from the host 1.

  As shown in FIG. 17, the host 1 desires to write data A1 to data A5 in the first to fifth RUs of AU1. In order to perform this writing, as shown in FIG. 16, the host 1 supplies the memory card 2 with a write command and subsequently data A1 to data A5 associated with the first to fifth RUs of AU1.

  As described above, in the sequential write mode, the memory card 2 always prepares an unwritten work AU in response to a write request, and writes data to the work AU. For this reason, as shown in FIG. 18, the memory card 2 writes data A1 to data A5 in the first to fifth RUs in the work AU1, which are the same as the RUs in which data A1 to data A5 are written in AU1, respectively. .

  As shown in FIG. 18, the host 1 desires to write data B1 to data B3 to the first to third RUs of AU2. In order to perform this writing, as shown in FIG. 16, the host 1 supplies the memory card 2 with a write command and subsequently data B1 to data B3 associated with the first to third RUs of AU2. The data B1 to B3 belong to an AU different from the data A1 to A3. Therefore, the data B1 to B3 is data that forms a file different from the file that the data A1 to A3 configures. As a specific example, for example, data B1 to data B3 are a part of moving image data, and data A1 to data A5 are a part of another moving image data. The memory card 2 (controller 22) observes AU, that is, the upper bits of the logical addresses assigned to these data, that the data A1 to data A5 and the data B1 to data B3 form different types of files. Judgment can be made.

  When the memory card 2 receives a write request for data B1 to data B3, the AU determines from the AU that these data constitute a file different from the data A1 to data A5 requested to be written first. To do. As a result of this determination, as shown in FIG. 19, the memory card 2 prepares a new work AU2 for AU2, and is the same as the RU in which data B1 to B3 are written in AU2 in work AU2. Data B1 to B3 are written to the first to third RUs, respectively.

  Furthermore, as shown in FIG. 19, the host 1 desires to write data A6 and data A7 in the sixth and seventh RUs of AU1. In order to perform this writing, as shown in FIG. 16, the host 1 supplies the memory card 2 with a write command and subsequently data A6 and data A7 associated with the sixth and seventh RUs of AU1. The data A6 and the data A7 belong to the same AU1 as the data A1 to data A5 that received the write request before. Therefore, as shown in FIG. 20, when the memory card 2 receives this write request, the data is stored in the sixth and seventh RUs in the work AU1 that are the same as the RUs in which the data A6 and the data A7 are written in the AU1. A6 and data A7 are written respectively.

  Furthermore, as shown in FIG. 20, the host 1 desires to write data B4 to data B6 in the fourth to sixth RUs of AU2. In order to perform this writing, as shown in FIG. 16, the host 1 supplies the memory card 2 with a write command and subsequently data B4 to data B6 associated with the fourth to sixth RUs of AU2. The data B4 to data B6 belong to the same AU2 as the data B1 to data B3. Therefore, as shown in FIG. 20, when the memory card 2 receives this write request, the data is stored in the fourth to sixth RUs in the work AU2 that are the same as the RUs in which the data B4 to data B6 are written in the AU2. B4 to B6 are written respectively.

  Since the write request has ended, the host 1 supplies a sequential write end command to the memory card 2 as shown in FIG. When this command is received, as shown in FIG. 21, the memory card 2 performs the closing process for all the work AUs, and then shifts to the random writing mode.

  In the description of the second example, two data streams, that is, two streams each including file data of data A1 to data A7 and data B1 to data B6 have been described. However, it is possible to apply this embodiment to more than two streams based on the principles described herein. How many streams of data can be simultaneously written in the memory card 2 depends on how many work AUs the memory card 2 can prepare simultaneously. The number of work AUs prepared simultaneously can be selected according to the writing speed, storage capacity, and specifications of the memory card 2.

[2-3] Third Example Next, a method for closing the work AU at an arbitrary timing will be described with reference to FIGS. 22 to 27. FIG. 22 shows a third example of commands and data received by the memory card according to the first embodiment. 23 to 27 sequentially show one state at the time of writing of the third example in the memory card 2 according to the first embodiment. In FIG. 23 to FIG. 27, AUs excluding work AUs represent AUs recognized by the file system 12, and also represent AUs that store data in the AUs in the memory card 2. ing. Note that the third example relates only to the operation in the sequential write mode, and the other operations are the same as those in the first example.

  First, the memory card 2 is in the random write mode. In this state, as shown in FIG. 22, the memory card 2 shifts to the sequential write mode by the sequential write start command received from the host 1.

  As shown in FIG. 23, the host 1 desires to write data A1 to data A5 in the first to fifth RUs of AU1. In order to perform this writing, as shown in FIG. 22, the host 1 supplies the memory card 2 with a write command and subsequently data A1 to data A5 associated with the first to fifth RUs of AU1.

  Upon receiving this write request, as shown in FIG. 24, the memory card 2 prepares a new work AU1 for AU1, and the RU in which data A1 to data A5 are written in AU1 in the work AU1. The data A1 to data A5 are respectively written in the same first to fifth RUs.

  As shown in FIG. 24, the host 1 desires to write data B1 to data B3 to the first to third RUs of AU2. In order to perform this writing, as shown in FIG. 16, the host 1 supplies the memory card 2 with a write command and subsequently data B1 to data B3 associated with the first to third RUs of AU2. Since the memory card 2 forms a file different from the data A1 to data A5, the memory card 2 prepares a new work AU2 for AU2 as shown in FIG. Subsequently, the memory card 2 writes data B1 to data B3 in the same first to third RU as the RU in which data B1 to data B3 are written in AU2 in the work AU2.

  Next, the host 1 stores a work AU close command in the memory in order to end the writing of the file composed of the data B1 to the data B3 while continuing the writing of the file composed of the data A1 to the data A5. 2 is supplied. Upon receiving this command, the memory card 2 performs a closing process on the work AU in which data has been written immediately before this command. As a result, a further work AU can be provided instead of the work AU2. For example, if the number of file data that can be written in parallel by the memory card 2 is 2, the file data can be written after the closing process for the work AU2.

  The close command has an argument for designating a work AU to be closed. In this argument, it is possible to specify the work AU to which data has been written immediately before as described above, to specify an arbitrary work AU when there are a plurality of work AUs, and to specify all the work AUs.

  As shown in FIG. 26, the host 1 desires to write data A6 and data A7 in the sixth and seventh RUs of AU1. In order to perform this writing, as shown in FIG. 22, the host 1 supplies the memory card 2 with a write command, and subsequently data A6 and data A7 associated with the sixth and seventh RUs of AU1. When this write request is received, as shown in FIG. 27, the memory card 2 stores data A6 and data in the sixth and seventh RUs in the work AU1, which are the same as the RUs in which data A6 and data A7 are written in AU1. Write A7 respectively.

  Since the write request has ended, the host 1 supplies a sequential write end command to the memory card 2 as shown in FIG. When this command is received, as shown in FIG. 21, the memory card 2 performs the closing process on all the work AUs (only the work AU1 in this example), and then shifts to the random write mode.

  As described above, according to the memory card according to the first embodiment, the random write mode and the sequential write mode are provided. In the sequential write mode, when data update is requested, data that is not updated in the RU that belongs to the AU to which the updated RU belongs is not copied to the new AU. Therefore, in the sequential write mode, data is always written to consecutive unwritten RUs. Such a writing speed is the maximum writing speed that the flash memory 21 can achieve. The host 1 has a great merit of being able to write at maximum performance. The maximum writing speed depends on the performance of the flash memory 21 and is almost constant. Therefore, the time required to complete the requested write can be easily calculated from the maximum write speed and the number of necessary AUs (RU) calculated from the data capacity that the host 1 requests to write. Further, since the calculation of the writing time is easy, the time required for this calculation is short.

  Further, in the memory card 2, data is written in successive RU pages in the order of logical addresses of write data. Such data writing can bring out the maximum writing speed of the memory 21. Further, since the data is not copied in the sequential write mode, the memory card 2 can continue to write only in response to the write request. Since the writing speed is the maximum writing speed of the memory 21 as described above, the memory card 2 can continue writing at the maximum writing speed in the sequential writing mode.

  Further, the memory card 2 can maintain the maximum writing speed in the sequential writing mode. Therefore, as in the second example, two or more file data can be stored in parallel by providing a dedicated work AU for each file data for two or more separate file data. Is possible.

  Moreover, according to the memory card according to the first embodiment, a work AU close command is provided. By this command, the memory card 2 writing the file data in parallel can perform the closing process on an arbitrary work AU without waiting for the supply of the sequential write end command. As a result, the work AU for file data that has been written can be released, and another work AU for file data can be newly provided. This is effective because the number of streams that can be written simultaneously is limited when this function is realized by hardware.

(Second Embodiment)
In the second embodiment, a dedicated command for shifting to a specific write preparation state is provided. The memory card according to the second embodiment has the same structure as that of the first embodiment (FIGS. 1 to 5), and the operation is different.

[1] First Example The operation of the first example of the second embodiment will be described with reference to FIGS. FIG. 28 shows a first example of commands and data received by the memory card according to the second embodiment. FIGS. 29 to 34 sequentially show one state at the time of writing in the first example in the memory card 2 according to the second embodiment. In FIG. 29 to FIG. 34, the AU excluding the work AU represents the AU recognized by the file system 12, and also represents the AU storing the data in the AU in the memory card 2. ing.

  First, as shown in FIG. 29, data 1 to data 8 are written in the first to eighth RUs of AU1, and data 9 to data 16 are written to the first to eighth RUs of AU2. Subsequently, as shown in FIG. 28, the host 1 supplies a write preparation command to the memory card 2. When the memory card 2 receives the write preparation command, it prepares to shift to a state where writing can be started immediately. The memory card 2 is in preparation by transmitting, for example, a signal indicating a busy state to the host 1 while performing processing for shifting to a real-time write (immediate write) enabled state (real-time write enabled mode). Tell the effect. When the busy state is released, the host 1 starts writing.

  As shown in FIG. 29, the host 1 desires to write data 20 to 22 in the fourth to sixth RUs of AU1. In order to perform this writing, as shown in FIG. 28, the host 1 supplies the memory card 2 with a write command and subsequently data 20 to data 22 associated with the fourth to sixth RUs of AU1.

  When the memory card 2 in the real-time writable state receives the write request, as shown in FIG. 29, the work AU (work AU1) for the write target AU (AU1) is received except when a continuation command described later is received. ).

  This write request requests a write from an RU that is not the head of the AU. The memory card 2 in the immediate write state has the RU (first to third RU) data higher than the write data RU among the AUs (AU1) to which the write data RUs (fourth to sixth RUs in this example) belong. Does not copy to work AU (work AU1). Therefore, as shown in FIG. 30, the memory card 2 writes data 20 to data 22 in the fourth to sixth RUs in the work AU, which are the same as the RUs in which data 20 to data 22 are written in AU1.

  The host 1 updates data 7 and data 8 of the seventh and eighth RUs of AU1 with data 23 and data 24, and updates data 9 to data 11 of AU2 with data 25 to data 27. Hope to do. In order to perform this update, as shown in FIG. 28, the host 1 sends a write command, data 23 associated with the seventh and eighth RUs of AU1, data 24, and first to third RUs of AU2 to the memory card 2. The data 25 to the data 27 associated with are supplied. When this write request is received, as shown in FIG. 32, the memory card 2 stores the data 23 and data in the seventh and eighth RUs in the work AU, which are the same as the RUs in which data 23 and data 24 are written in AU1. Write 24 each. At this time, since the data was written in the last RU of the work AU1, the memory card 2 performs a closing process on the work AU. Further, the memory card 2 prepares a new work AU for AU2.

  As shown in FIG. 33, the memory card 2 writes the data 25 to data 27 in the first to third RUs in the work AU, which are the same as the RUs in which the data 25 to data 27 are written in the AU2.

  Since the write request has been completed, the host 1 supplies a close command to the memory card 2 as shown in FIG. As in the first embodiment, the close command has an argument for specifying the work AU to be closed, and further has an argument for setting whether or not there is a copy. In the close command supplied in FIG. 28, no copy is specified. As shown in FIG. 33, when the memory card 2 receives this command, the data 12 to the RU (third to eighth RU) that are not updated in the AU (AU2) to be written by the immediately preceding write command. The close process is performed on the work AU2 without copying the data 16 to the work AU2.

  In the second embodiment, operations other than the real-time writable state are the same as the random write mode of the first embodiment.

[2] Second Example Next, recording a plurality of file data in parallel by applying the first example will be described with reference to FIGS. FIG. 34 shows a second example of commands and data received by the memory card according to the second embodiment. 35 to 39 sequentially show one state at the time of writing in the second example in the memory card 2 according to the second embodiment. 35 to 39, the AU excluding the work AU represents the AU recognized by the file system 12, and also represents the AU storing the data in the AU in the memory card 2. ing.

  As shown in FIG. 34, the memory card 2 shifts to a real-time writable state by a write preparation command received from the host 1.

  As shown in FIG. 35, the host 1 desires to write data A1 to data A5 in the first to fifth RUs of AU1. In order to perform this writing, as shown in FIG. 34, the host 1 supplies the memory card 2 with a write command and subsequently data A1 to data A5 associated with the first to fifth RUs of AU1. Data X1 to X8 are written in the first to eighth RUs of AU1.

  As described above, the memory card 2 in the real-time writable state prepares a new work AU except when a continuation command described later is received. For this reason, as shown in FIG. 36, the memory card 2 prepares a work AU1 for AU1. Subsequently, the memory card 2 writes data A1 to data A5 in the first to fifth RUs in the work AU1, which are the same as the RUs in which data A1 to data A5 are written in AU1, respectively.

  The host 1 desires to write in parallel file data different from the file data of which data A1 to data A5 constitute a part. For this reason, it is scheduled to continue writing to the work AU1. For this purpose, the host 1 supplies a continuation command to the memory card 2 as shown in FIG. The continuation command can be realized by providing an argument for designating a close processing instruction or a work AU continuation instruction in the close command. Alternatively, a command different from the close command may be provided. As shown in FIG. 36, when the memory card 2 receives the continuation command, the memory card 2 does not perform the closing process on the work AU1, but instead selects the work AU1 for the AU1 that has received the write request immediately before this command. Continue to hold.

  As shown in FIG. 36, the host 1 desires to write data B1 to data B3 to the first to third RUs of AU2. In order to perform this writing, as shown in FIG. 34, the host 1 supplies the memory card 2 with a write command and subsequently data B1 to data B3 associated with the first to third RUs of AU2.

  As described above, when the memory card 2 in the real-time writable state receives the write command, it creates a new work AU except when the continuous use of the work AU is requested by the continuation command. Since the data B1 to data B3 belong to an AU (AU2) different from the AU (AU1) to which the data A1 to A3 belong, as shown in FIG. 37, when the memory card 2 receives the write data B1 to data B3, Work AU2 is prepared. The memory card 2 writes data B1 to data B3 in the first to third RUs in the work AU2 that are the same as the RUs in which data B1 to data B3 are written in AU2.

  Subsequently, in order to write data following the data A5, the host 1 supplies a continuation command to the memory card 2 as shown in FIG. As shown in FIG. 37, when the memory card 2 receives the continuation command, the memory card 2 continues to hold the work AU2 for the AU that was the target of the write request immediately before this command.

  As shown in FIG. 37, the host 1 desires to write data A6 and data A7 in the sixth and seventh RUs of AU1. In order to perform this writing, as shown in FIG. 34, the host 1 supplies the memory card 2 with a write command, and subsequently data A6 and data A7 associated with the sixth and seventh RUs of AU1.

  As shown in FIG. 38, since the memory card 2 maintains the work AU1 for AU1, the memory card 2 does not create a new work AU in response to the write command. Instead, the memory card 2 writes the data A6 and the data A7 in the sixth and seventh RUs in the work AU1 that are the same as the RUs in which the data A6 and data A7 are written in the AU1, respectively.

  Subsequently, in order to write data following the data B3, the host 1 supplies a continuation command to the memory card 2 as shown in FIG. As shown in FIG. 38, when the memory card 2 receives the continuation command, the memory card 2 continues to hold the work AU1 for the AU that was the target of the write request immediately before this command.

  Next, as shown in FIG. 38, the host 1 desires to write data B4 and data B5 in the fourth and fifth RUs of AU2. In order to perform this writing, as shown in FIG. 34, the host 1 supplies the memory card 2 with a write command, and subsequently data B4 and data B6 associated with the fourth and fifth RUs of AU2.

  As shown in FIG. 39, since the memory card 2 maintains the work AU2 for the AU2, the memory card 2 has the data B4 and the data B5 written in the AU2 within the work AU2 being maintained. Data B4 and data B5 are written in the fourth and fifth RUs, which are the same as the RUs that are in progress

  As shown in FIG. 38, the host 1 desires to write data B6 to the sixth RU of AU2. When the host 1 requests to write to the RU in the AU including the RU written immediately before, the host 1 can do this by continuously supplying the write command without supplying the continuation command. Therefore, in order to perform this writing, as shown in FIG. 34, the host 1 supplies the memory card 2 with the write command and subsequently the data B6 associated with the sixth RU of AU2. When receiving the write request, the memory card 2 writes the data B6 in the sixth RU in the work AU2 that is the same as the RU in which the data B6 is written in the AU2.

  Since the write request has been completed, the host 1 supplies a close command to the memory card 2 as shown in FIG. In the example of FIG. 34, all the work AUs are specified as the arguments of the work AUs to be closed by the close command, and the designation of no copy is also described in the arguments. As shown in FIG. 39, when the memory card 2 receives this command, the memory card 2 closes the work AU1 and the work AU2 without copying the data X8 of the RU (eighth RU) not updated in the AU1 to the work AU1. To do.

[3] Third Example Next, another example of applying a first example and recording a plurality of file data in parallel will be described with reference to FIGS. FIG. 40 shows a third example of commands and data received by the memory card according to the second embodiment. 41 to 47 sequentially show one state at the time of writing of the third example in the memory card 2 according to the second embodiment. The data A1 to A7 in these figures are moving image data, and the data B1 to data B3 and the data C1 to data C3 are typically still image data. In FIG. 41 to FIG. 48, AUs excluding work AUs represent AUs recognized by the file system 12, and also represent AUs that store data in the AUs in the memory card 2. ing.

  As shown in FIG. 40, the memory card 2 shifts to a real-time writable state by a write preparation command received from the host 1.

  As shown in FIG. 41, the host 1 desires to write data A1 to data A5 in the first to fifth RUs of AU1. In order to perform this writing, as shown in FIG. 40, the host 1 supplies the memory card 2 with a write command and subsequently data A1 to data A5 associated with the first to fifth RUs of AU1. Data X1 to X8 are written in the first to eighth RUs of AU1.

  As described above, the memory card 2 in the real-time writable state prepares a new work AU except when a continuation command is received. Therefore, as shown in FIG. Work AU1 is prepared. Subsequently, the memory card 2 writes data A1 to data A5 in the first to fifth RUs in the work AU1, which are the same as the RUs in which data A1 to data A5 are written in AU1, respectively.

  The host 1 desires to write in parallel file data different from the file data of which data A1 to data A5 constitute a part. For this purpose, the host 1 supplies a continuation command to the memory card 2 as shown in FIG. As shown in FIG. 42, when the memory card 2 receives the continuation command, the memory card 2 continues to hold the work AU1.

  As shown in FIG. 42, the host 1 desires to write data B1 to data B3 to the first to third RUs of AU2. In order to perform this writing, as shown in FIG. 40, the host 1 supplies the memory card 2 with a write command and subsequently data B1 to data B3 associated with the first to third RUs of AU2. Data Y1 to Y8 are written in the first to eighth RUs of AU2.

  Since the data B1 to data B3 belong to an AU different from the previously written AU1, as shown in FIG. 43, when the memory card 2 receives the write data B1 to B3, the work AU2 is prepared. The memory card 2 writes data B1 to data B3 in the first to third RUs in the work AU2 that are the same as the RUs in which data B1 to data B3 are written in AU2.

  Since the writing of the file data composed of the data B1 to B3 is completed, the host 1 supplies a close command to the memory card 2 as shown in FIG. This close command specifies no copy as an argument. Therefore, as shown in FIG. 44, when the memory card 2 receives this command, the data of the RUs (fourth to eighth RUs) that have not been updated in the AU2 to be written by the immediately preceding write command. The close process is performed on the work AU2 without copying Y4 to data Y8 to the work AU2.

  As shown in FIG. 44, the host 1 desires to write data A6 and data A7 in the sixth and seventh RUs of AU1. In order to perform this writing, as shown in FIG. 40, the host 1 supplies the memory card 2 with a write command, and subsequently data A6 and data A7 associated with the sixth and seventh RUs of AU1.

  As shown in FIG. 44, since the memory card 2 maintains the work AU1 for the AU1, the memory card 2 does not create a new work AU in response to the write command. Instead, the memory card 2 writes the data A6 and the data A7 in the sixth and seventh RUs in the work AU1 that are the same as the RUs in which the data A6 and data A7 are written in the AU1, respectively.

  Writing of the file data composed of the data A1 to A7 is completed, and as shown in FIG. 45, the host 1 desires to write the data C1 to C3 to the first to third RUs of AU3. In order to perform this writing, as shown in FIG. 40, the host 1 supplies the memory card 2 with a write command and subsequently data C1 to data C3 associated with the first to third RUs of AU2. Data Z1 to Z8 are written in the first to eighth RUs of AU3.

  The data C1 to data C3 belong to a different AU from the previously written AU1. Further, data X8 that has not been updated remains in AU1. In this state, the memory card 2 that has received the write command without receiving the continuation command copies the unupdated data in the AU 1 that has written last to the work AU. That is, as shown in FIG. 46, the memory card 2 copies the data X8 to the eighth RU in the work AU1 that is the same as the RU assigned the data X8 in AU1. Thereafter, since the memory card 2 has not received a close command having an instruction to close the work AU1, the memory card 2 does not perform the close process on the work AU1. Note that this copying operation is after the end of real-time writing, and therefore does not affect writing or calculation of writing time. Copying data X8 in AU1 to work AU1 can also be performed using a close command. That is, prior to supplying a write command for writing data C1 to data C3, the host 1 supplies the memory card 2 with a close command designated as copy in the argument. When the memory card 2 receives such a close command, the data X8 of the RU (eighth RU) after the last written RU (seventh RU) in the target AU (AU1) is used as the same eighth RU of the work AU1. Copy to.

  Subsequently, the memory card 2 prepares a work AU3 for AU3. Data C1 to C3 are written from the head RU of AU3, so copying is not necessary. Therefore, as shown in FIG. 47, the memory card 2 writes data C1 to data C3 in the first to third RUs in the work AU3, which are the same as the RUs in which data C1 to C3 are written in AU3.

  Since the writing of the file data composed of the data A1 to A7 and the file data composed of the data C1 to C3 is completed, the host 1 supplies a close command to the memory card 2 as shown in FIG. . In this close command, an instruction for no copy is specified as an argument, and an instruction for performing close processing on all the work AUs (work AU1 and AU3 in this example) is specified as an argument. Therefore, as shown in FIG. 47, when the memory card 2 receives this command, the memory card 2 performs the closing process on the work AU1 and also the data of the RUs (fourth to eighth RUs) not updated in the work AU3. A close process is performed on the work AU3 without copying Z4 to data Z8 to the work AU3.

  As described above, according to the memory card according to the second embodiment, the real-time write state is defined. When the memory card in the real-time write state receives a write command, it prepares a work AU consisting only of unwritten RUs and writes the write data to the RUs in the work AU in the order of the logical addresses of the write data. The speed of writing to such consecutive unwritten RUs is the maximum writing speed that the flash memory 21 can achieve. The maximum writing speed depends on the performance of the flash memory 21 and is almost constant. Therefore, the time required to complete the requested write can be easily calculated from the maximum write speed and the number of necessary AUs (RU) calculated from the data capacity that the host 1 requests to write. Further, since the calculation of the writing time is easy, the time required for this calculation is short.

  In the memory card according to the second embodiment, a continuation command is provided. With the continuation command, another work AU can be prepared without performing the closing process on the work AU. For this reason, by providing a dedicated work AU for each file data with respect to data of two or more separate files, it becomes possible to store two or more file data in parallel.

  Note that the continuation command only causes the temporary writing to the created work AU to be stopped. For this reason, even if the memory card receives a continuation command as in the second example, it is eventually the same as writing only to unwritten consecutive RUs without pausing as in the first example. is there.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

The figure which shows the main functional blocks of the memory card based on 1st Embodiment with the functional block of a host apparatus. The figure which illustrates the detail of a register. The figure which shows the structure of memory space. The figure which shows the storage area which the host has recognized, and the storage area of a memory card. FIG. 6 is a transition diagram of modes that the memory card of the first embodiment can take. The figure which illustrates one state at the time of writing of the 1st example in the memory card of a 1st embodiment. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 1st example of the command and data which the memory card of 1st Embodiment receives. The figure which shows one state at the time of writing of the 1st example in the memory card of 1st Embodiment. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 2nd example of the command and data which the memory card of 1st Embodiment receives. The figure which shows one state at the time of writing of the 2nd example in the memory card of 1st Embodiment. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 3rd example of the command and data which the memory card of 1st Embodiment receives. The figure which shows one state at the time of writing of the 3rd example in the memory card of 1st Embodiment. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 1st example of the command and data which the memory card of 2nd Embodiment receives. A figure showing one state at the time of writing of the 1st example in a memory card of a 2nd embodiment. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 2nd example of the command and data which the memory card of 2nd Embodiment receives. A figure showing one state at the time of writing of the 2nd example in a memory card of a 2nd embodiment. The figure which illustrates the state following FIG. FIG. 36 is a diagram illustrating a state following the state; The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which shows the 3rd example of the command and data which the memory card of 2nd Embodiment receives. A figure showing one state at the time of writing of the 3rd example in a memory card of a 2nd embodiment. The figure which illustrates the state following FIG. 42 is a diagram illustrating the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG. The figure which illustrates the state following FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Host device, 2 ... Memory card, 11 ... Software, 12 ... File system, 13 ... SD interface, 21 ... Flash memory, 22 ... Controller, 31 ... SD interface, 32 ... MPU, 33 ... ROM, 34 ... RAM, 35 ... NAND interface, 36 ... register, 41 ... memory area, 42 ... page buffer, PG ... page, BLK ... block, RU ... RU, AU ... AU.

Claims (10)

A memory having a plurality of storage areas;
When the write data is received, the write data is written to the storage area while managing the correspondence between the logical address of the write data and the storage area for storing the write data, and the write data of an unspecified size is set to the logical address A first mode that holds data that was not to be written in a management unit storage area that can be written to the storage area without any restriction in order and that is composed of a plurality of consecutive storage areas, and has a specific size; A controller having a second mode for writing the plurality of write data to the storage area in order of increasing logical addresses and handling unwritten data in the management unit storage area as invalid data;
A memory device comprising:   The memory device according to claim 1, wherein the controller includes a register that holds information regarding a writing speed to the storage area.   The controller shifts to the second mode when receiving a command instructing transition to the second mode, and shifts to the first mode when receiving a command instructing transition to the first mode. The memory device of claim 1. When the controller receives a write request for write data to which a plurality of consecutive logical addresses are assigned in the second mode, the controller temporarily prepares corresponding to the logical address area to which the logical address of the write data belongs. Write the write data to the work area
Whether writing to the last storage area in the work area is completed, or when the first command is received, copying the old data before the write data write request to the unwritten area by the argument Determining whether to do so, assigning a logical address to the work area and discarding the management unit storage area that had stored the old data before the write request of the write data,
The memory device according to claim 3. The controller is
Write a plurality of first write data having a predetermined relationship with each other and assigned logical addresses belonging to a certain management unit area to the work area,
Writing second write data having a predetermined relationship with each other and assigned with a logical address belonging to a management unit area different from the logical address of the first write data to a work area different from the work area;
The memory device of claim 4, wherein:   When the controller receives the first command when there are a plurality of work areas, all or a specified one of the plurality of work areas is allocated to the management unit storage area that holds the old data. 5. The memory device according to claim 4, wherein the assigned logical address is assigned to the work area and the management unit storage area storing the old data of the write data is discarded. A memory having a plurality of storage areas;
When write data is received, the write data is written to the storage area while managing the correspondence between the logical address of the write data and the storage area for storing the write data, and is composed of a plurality of consecutive logical addresses A controller that recognizes the logical address area and transitions to a real-time writable state upon receipt of the first command;
Comprising
When the controller in the real-time writable state receives a write request, each controller writes a plurality of write data to a work area temporarily prepared corresponding to the management unit storage area to which the logical address of the write data belongs. Write to the storage area in the work area in order of increasing logical address, and write to the last storage area in the work area is completed, or when a second command is received, a logical address is assigned to the work area. A memory device characterized by that.   8. The memory device according to claim 7, wherein a plurality of streams can be written by having one work area in the first mode and having a plurality of work areas in the second mode. The controller writes write data whose write position is designated by the logical address belonging to one management unit storage area to a plurality of continuous storage areas in the management unit storage area;
After the controller writes the last series of data,
When the second command instructing retention of old data before the write request of the write data by an argument is received, the write to the storage area having a larger address than the storage area written last in the work area A logical address is assigned to the work area after copying the data in the management unit storage area that holds the old data before the write request for data,
When the second command for instructing to discard the old data before the write request of the write data is received by an argument, the old data is stored in the storage area having a larger address than the last written storage area in the work area. Assigning a logical address to the work area without copying the data in the management unit storage area holding the data;
9. The memory device of claim 8, wherein:   When the second command distinguished by an argument is received when there are a plurality of work areas, the old data before the write request for the write data is copied to the unwritten storage area for each of the plurality of work areas. The management unit storage area in which the logical data assigned to the management unit storage area that has held the old data is assigned to the work area and the old data before the write request for the write data is stored. The memory device of claim 8, wherein the memory device is discarded.

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