JP2010136278A - Pwm waveform producing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for producing a PWM (Pulse Width Modulation) wave with a high resolution even in a low-speed processor only by adding a simple circuit. <P>SOLUTION: A PWM waveform producing apparatus 1 includes: a PWM circuit 100 for producing a first pulse signal and a second pulse signal, which are synchronized with a reference clock and have variable active time; a first slope circuit 110B for adding a slope to a falling edge of the first pulse signal; a second slope circuit 110A for adding the slope to a rising edge of the second pulse signal so that each slope is crossed; and a comparator 120 for producing a comparison signal between an output voltage from the first slope circuit 110B and an output voltage from the second slope circuit 110A. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a PWM waveform generation apparatus including a PWM waveform generation circuit that modulates a pulse width.

  In general, a technique is known in which the amplitude of an input voltage is converted (modulated) into a constant pulse width using a PWM (Pulse Width Modulation) waveform generation circuit to generate a PWM waveform.

  As an analog PWM control method that has been used in the past, for example, by setting the position to turn on the pulse signal in a triangular wave or sawtooth wave that operates at a fixed period, and comparing this with the command value, There is a method for controlling the width.

  However, in recent years, the above technique has been digitized, and a processor has been developed that includes a reference clock, a counter, and the like and executes an algorithm for controlling a command value.

  In this method, a pulse width corresponding to a command value is calculated for every fixed period corresponding to a carrier period, and control is performed by turning on / off a bit (for example, see Non-Patent Document 1).

Transistor Technology SPECIAL No.98 “Design of Power Electronics Circuits” P117-119

  However, in such a circuit, if the frequency is increased, the bit width of the counter is reduced, so that the resolution is lowered. If the resolution is raised, the bit width is increased, so that the frequency is lowered. It becomes an off relationship. Therefore, in order to increase the resolution while maintaining the frequency, it is necessary to move the counter at a high speed. However, in this case, there is a problem that the power consumption and cost of the circuit are increased.

  Therefore, the present invention pays attention to such problems of the prior art, and an object of the present invention is to provide an apparatus that generates a PWM wave with high resolution even in a low-speed processor by adding a simple circuit.

  A PWM wave generation device according to the present invention for solving the above problem is a pulse signal output circuit for outputting a first pulse signal and a second pulse signal of the same period generated in synchronization with the same reference clock. A first slope circuit that adds a slope to the falling edge of the first pulse signal and outputs it; a second slope circuit that adds a slope to the rising edge of the second pulse signal and outputs; The output signal from the first slope circuit and the output signal from the second slope circuit are compared, and the first pulse signal and the rising edge are synchronized and fall at the intersection of the slopes, or the slope signal And a PWM signal output circuit for outputting a PWM signal whose rising edge is synchronized with the falling edge of the second pulse signal.

  According to the present invention, a PWM wave can be generated with high resolution even with a low-speed processor.

  First, a PWM circuit using a general counter will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a general PWM circuit 200.

  The PWM circuit 200 includes a CPU 202, an N-bit counter 203, a compare register 204A, a compare register 204B, and an output circuit 205.

The CPU 202 sets various control information. Here, CPU 202 sets a comparison value _{M 2} for storing the comparison value _{M 1} and compare register 204B stores the compare register 204A. Note that comparison values M ₁ defines the cycle of the PWM wave generated, comparison value M ₂ defines the active time (Duty ratio). Also, changing the comparison value M ₂ is executed at the timing counter value of the N-bit counter 203 to be described later is reset.

  When the N-bit counter 203 receives a pulse (reference clock) having a predetermined frequency as a PWM carrier output from an oscillator or the like, the N-bit counter 203 counts this and outputs the result as a counter value.

Compare register 204A has a counter value of the N-bit counter 203, a comparison value M ₁ stored therein, by comparing, generating a coincidence signal when the two values match, outputs to the output circuit 205 To do. The compare register 204A resets the counter value of the N-bit counter 203 to zero in synchronization with the coincidence signal.

Compare register 204B includes a counter value of the N-bit counter 203, a comparison value M ₂ which stores, compares, and generating a coincidence signal when the two values match, outputs to the output circuit 205 To do.

  When receiving the coincidence signal input from the compare register 204A, the output circuit 205 sets the output level to “1”, and upon receiving the coincidence signal input from the compare register 204B, sets the output level to “0”. Outputs a PWM wave.

FIG. 2 is an explanatory diagram of a PWM signal output from the PWM circuit 200. From the output terminal of the PWM circuit 200 (not shown), through the output circuit 205, PWM wave counter value active time to reach the comparison value M ₂ from zero, and a one cycle until it reaches the comparison value M ₁ Is output.

  The switching frequency when the circuit has N-bit resolution is obtained from the following equation (1).

  According to Equation 1, for example, assuming that the operation clock and the reference clock of the CPU of the PWM circuit 200 are 10 MHz, when the resolution is 9 bits, the switching frequency is approximately 19.5 kHz and the resolution is 10 bits. The switching frequency is about 9.8 kHz. As described above, in a general system in which the reference clock is fixed, the frequency and the resolution are in an inversely proportional relationship.

  Next, the PWM waveform generator 1 of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the PWM waveform generation apparatus 1 according to the present invention.

  The PWM waveform generation apparatus 1 includes a 2-channel PWM circuit 100, 2-channel slope circuits 110A and 110B, and a comparator 120.

  In the PWM waveform generation device 1 according to the present invention, first, two PWM pulses whose rising edges are synchronized are output by the two-channel PWM circuit 100. Therefore, a general two-channel PWM circuit 100 will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of the PWM circuit 100 included in the PWM waveform generation device 1.

  The PWM circuit 100 has substantially the same configuration as that of the PWM circuit 200, but is different in that it further includes a compare register 104C. Therefore, this point will be mainly described.

The CPU 102 sets a comparison value M ₁ stored in the compare register 104A, a comparison value M ₂ stored in the compare register 104B, and a comparison value M ₃ stored in the compare register 104C. Note that the comparison value M ₁ is the period of the PWM wave generated, comparison value M ₂ is the active time of the output PWM2, comparison value M ₃ are defining the active time of the output PWM1.

The operations of the compare register 104A and the compare register 104B are the same as those of the compare register 204A and the compare register 204B. Here, also for the compare registers 104C, similar to the compare register 104B, a counter value of the N-bit counter 103, as compared with the comparison value M ₃ for storing the match signal when the two values match Is output to the output circuit 105.

  FIG. 5 is an explanatory diagram of PWM1 and PWM2, which are output signals generated by the PWM circuit 100. FIG.

  Upon receiving the coincidence signal from the compare register 104A, the output circuit 105A and the output circuit 105B set the output level to “1”.

  Further, upon receiving the coincidence signal input from the compare register 104B, the output circuit 105A sets the output level to “0” and outputs PWM2 as shown in FIG.

  Further, upon receiving the coincidence signal input from the compare register 104C, the output circuit 105B sets the output level to “0” and outputs PWM1 as shown in FIG.

  In this way, the PWM circuit 100 outputs two PWM pulses whose rising edges are synchronized and which have different duty ratios. PWM1 is input to the slope circuit 110B, and PWM2 is input to the slope circuit 110A.

  FIG. 6 shows configurations of the slope circuit 110A and the slope circuit 110B. The slope circuits 110A and 110B generate an output signal Vs2 and an output signal Vs1 having a slope at the rising edge (PWM2) or falling edge (PWM1) of the pulse waveform as shown in FIG. 7 based on the input PWM1 and PWM2. .

  The anode of the diode D1 and the cathode of the diode D2 are connected to the input terminal to which the PWM2 of the slope circuit 110A is input. The anode of the diode D2 is connected to the resistor R1 of the integrating circuit.

  The integrating circuit inputs the reference signal Vref1 to the resistor R1, the operational amplifier OP1, the feedback capacitor C1 of the operational amplifier OP1 in which the resistor R1 is connected to the inverting input terminal (−), and the non-inverting input terminal (+) of the operational amplifier OP1. It consists of a variable resistor VR1 and a power source.

  The slope of the output signal Vs2 from the integration circuit can be adjusted by changing the reference signal Vref1 applied to the operational amplifier OP1. Of course, the slope of the slope waveform can also be adjusted by the resistor R1.

  The output signal of the integration circuit, that is, the output signal Vs2 from the slope circuit 110A is input to the inverting input terminal (−) of the comparator 120.

  The slope circuit 110B has substantially the same configuration as that described above, but differs from the slope circuit 110A in that an inverter is provided and the two diodes have opposite directions.

  An inverter NOT1 is connected to the input side of PWM1 of the slope circuit 110B. The slope circuit 110B includes a diode D3 whose cathode is connected to the inverter NOT1, an anode connected to the capacitor C2 of the integrating circuit, and a diode whose anode is connected to the input terminal and whose cathode is connected to the resistor R1 of the integrating circuit. D4 is connected.

  Note that the configuration of the integration circuit to which the diodes D3 and D4 are connected is the same as that described above, and thus detailed description thereof is omitted. The output signal Vs1 output from the integrating circuit of the slope circuit 110B, that is, the output signal from the slope circuit 110B is input to the non-inverting input terminal (+) of the comparator 120.

  In FIG. 7, PWM2 input to the slope circuit 110A and the output signal Vs2 from the slope circuit 110A are indicated by solid lines, and PWM1 input to the slope circuit 110B and the output signal Vs1 from the slope circuit 110B are indicated by broken lines. It shows with.

  When PWM2 input to the slope circuit 110A becomes L, the diode D1 is turned off and the diode D2 is turned on due to the potential difference. Then, current flows from the capacitor C1 and the resistor R1 to the diode D2, and an output signal Vs2 in which only the rising edge is inclined based on the time constant is obtained.

  Similarly, for the slope circuit 110B, when PWM1 is inverted by the inverter NOT1 and the input signal becomes H, the diode D4 is turned on, the diode D3 is turned off, and only the falling is inclined based on the time constant. An output signal Vs2 is obtained.

  Note that the slope circuits 110A and 110B shown in FIG. 6 are merely examples, and any circuit configuration can be used as long as a slope can be added, that is, the output signal can have a rising and falling slope. Good.

  The output signal Vs2 and the output signal Vs1 are then input to the comparator 120.

  If the voltage input from the non-inverting input terminal (+) is higher than the voltage input from the inverting input terminal (−), the operational amplifier has a high gain, and therefore the output of the comparator 120 becomes a positive maximum voltage. Reach. Conversely, if the voltage input from the non-inverting input terminal (+) is lower than the voltage input from the inverting input terminal (−), the output becomes the negative maximum voltage.

  Therefore, the comparator 120 outputs PWM3 as shown in FIG. 8 as a comparison output between Vs2 and Vs1. Specifically, PWM3 rises when the output signal Vs2 rises due to the reversal of the amount of input voltage to each terminal at the position where the rising output signal Vs1 falls, and the output signal Vs2 rises when the falling output signal Vs1 rises (the intersection of the slopes). ) Falls due to the reversal of the input voltage to each terminal.

  PWM3 generated in this way can be a pulse whose rising edge is synchronized with PWM1 and PWM2 and whose falling edge is delayed by a minimum pulse width determined by the frequency. That is, according to the PWM waveform generation device 1 according to the present embodiment, it is possible to modulate the pulse width of the PWM 3 with a duty ratio having a resolution higher than the resolution determined from the reference clock.

  Hereinafter, the amount of delay at the fall of PWM3 will be described. Here, since the slope of the slope of the output signal Vs2 is larger than that of the output signal Vs1 (the slope time is long), the falling position of the output signal Vs1 is made constant, and the rising position of the output signal Vs2 is changed. A case where the delay amount is changed will be described.

  FIG. 9 is an explanatory diagram for explaining the delay and resolution when the duty of the output signal Vs2 is changed with respect to the output signal Vs1.

  In the PWM waveform generation apparatus 1 according to the present invention, it is assumed that the reference clock is set to 10 MHz, the falling slope time of the output signal Vs1 is set to 0.1 usec, and the rising slope time of the output signal Vs2 is set to 0.2 usec.

Therefore, when the duty of PWM2 input to the slope circuit 110A (that is, the comparison value M ₂ ) is changed and the falling position of PWM2 is delayed by 0.1 usec which is the minimum pulse width, it is output from the slope circuit 110A. The rising position of the output signal Vs2 is also delayed by 0.1 usec (A to B shown in FIG. 9) which is the minimum pulse width.

  Then, the intersection of the output signal Vs1 and the output signal Vs2 is delayed by 1/3 of the minimum pulse width of 0.1 usec (A ′ to B ′ shown in FIG. 9). That is, the delay amount of 0.1 / 3 usec is obtained in PWM3 from the delay amount 0.1 usec of the output signal Vs2.

  Therefore, as in this example, in a configuration in which one slope time is the minimum pulse width and the other slope time is twice the minimum pulse width, the reference clock remains constant and a resolution equivalent to three times (30 MHz) is achieved. It is possible to realize. In this example, the delay amount is adjusted by changing the duty of PWM2. However, the delay amount can also be adjusted by changing the duty of PWM1.

  Further, such resolution can be adjusted as follows.

  For example, assuming that the slope of the falling slope of the output signal Vs1 is constant, the larger the slope of the rising slope of the output signal Vs2, the more the rising slope of the output signal Vs2 when the rising position is changed with the minimum pulse width is output. Since it intersects with the falling slope of signal Vs1 at many points, it is possible to output PWM3 with higher resolution.

  For example, in the example shown in FIG. 10, when the active time of PWM2 is moved with the minimum pulse width, both slopes can be crossed at four places in the minimum pulse width. Therefore, in this example, it is possible to realize a resolution that is five times the minimum pulse width.

  Of course, if the rising slope and the falling slope are at the crossing position, the resolution can be adjusted by making the slope of the rising slope of the output signal Vs2 constant and making the slope of the falling slope of the output signal Vs1 variable. Also good.

  Note that the slope of the slope of the output signal Vs2 can be adjusted by the reference signal Vref1 and the resistor R1 applied to the operational amplifier OP1, and the slope of the slope of the output signal Vs1 can be adjusted by the reference signal Vref2 and the resistor R2.

  Further, since the signal is generated based only on the value of the N-bit counter 103, the duty setting and the output timing of the PWM waveform are synchronized, and linear setting is possible with respect to output fluctuation.

  The embodiment of the present invention has been described above.

  According to the above-described embodiment, a PWM signal having a higher resolution can be obtained by adding a simple circuit to the two PWM signals having a falling slope and a rising slope and obtaining a comparison signal thereof without reducing the frequency. An output can be obtained. Therefore, it is possible to reduce power consumption and cost without using a high-speed processor, logic LSI, external circuit, or the like.

  Further, the finally output PWM signal can adjust the resolution by the slope of the two signals and the delay amount at the rising (and falling) position.

Block diagram showing the configuration of a general PWM circuit 200 4 is an explanatory diagram of a PWM signal output by the PWM circuit 200. The block diagram which shows the structure of the PWM waveform generation apparatus 1 which concerns on this invention 1 is a block diagram showing a configuration of a PWM circuit 100 included in a PWM waveform generation device 1. FIG. 3 is an explanatory diagram of PWM1 and PWM2 that are output signals generated by the PWM circuit 100. FIG. A circuit diagram showing composition of slope circuit 110A and slope circuit 110B. Explanatory drawing which shows the output signal from 110 A of slope circuits, and the slope circuit 110B. Explanatory drawing of the output signal PWM3 obtained by the PWM waveform generation apparatus 1. FIG. Explanatory drawing for demonstrating the delay and resolution when changing Duty of Vs2 with respect to Vs1. Explanatory drawing for demonstrating the delay and resolution when changing Duty of Vs2 with respect to Vs1.

Explanation of symbols

1: PWM waveform generator, 100/200: PWM circuit, 102/202: CPU, 103/203: N-bit counter, 104A / 104B / 104C / 204A / 204B: Compare register, 105/205: Output circuit, 110A / 110B: Slope circuit, 120: Comparator

Claims (6)

A pulse signal output circuit that outputs a first pulse signal and a second pulse signal of the same period generated in synchronization with the same reference clock;
A first slope circuit for adding a slope to the falling edge of the first pulse signal and outputting the slope;
A second slope circuit that adds a slope to the rising edge of the second pulse signal and outputs the slope;
The output signal from the first slope circuit and the output signal from the second slope circuit are compared, and the rising edge is synchronized with the first pulse signal and falls at the intersection of the slopes, or the slope A PWM signal output circuit for outputting a PWM signal whose rising edge is synchronized with the rising edge of the second pulse signal. The PWM waveform generator according to the first aspect,
The pulse signal output circuit is
A counter that counts the number of clocks of the reference clock and outputs a counter value;
The first pulse signal falls when the counter value is a predetermined first value,
The PWM pulse generator according to claim 2, wherein the second pulse signal falls when the counter value is a predetermined second value different from the first value. The PWM waveform generation device according to claim 1 or 2,
The PWM waveform generation device according to claim 1, wherein the first slope circuit and the second slope circuit include an adjusting unit that adjusts an inclination of the slope. The PWM waveform generation device according to any one of claims 1 to 3,
The resolution of the PWM signal is determined by the slope of the slope,
The PWM waveform generating device, wherein the resolution increases as the slope of the slope increases. The PWM waveform generation device according to any one of claims 1 to 4,
The PWM waveform generation apparatus, wherein the rising slope of the second pulse signal has a larger slope than the falling slope of the first pulse signal. The PWM waveform generation device according to claim 5,
The resolution of the PWM signal is determined by the second slope circuit adjusting the slope of the second slope,
The PWM waveform generating device, wherein the active time of the PWM signal is determined by the pulse signal output circuit modulating the active time of the second pulse signal.

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