JP2010136005A - Amplifying circuit, reference voltage generation circuit, integrated circuit device, electro-optical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a highly accurate voltage after minimizing a harmful effect of a parasitic capacitance, or the like. <P>SOLUTION: This amplifying circuit includes an operational amplifier OP, a capacitor CA for charge storage provided between an input node NI and a first input terminal NEG of the operational amplifier OP, and a capacitor CC for phase compensation provided in an output terminal of the operational amplifier OP, wherein the capacitor CA for charge storage is configured by a first type of a capacitor Type 1 in which electrodes of both ends are formed of a metal layer or polysilicon layer, the capacitor CC for phase compensation is configured by a second type of a capacitor Type 2 in which one electrode is formed of a polysillicon layer and the other electrode is formed of an impurity layer, and the capacitor CC for phase compensation is arranged under the capacitor CA for charge storage in a planar view. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier circuit, a reference voltage generation circuit, an integrated circuit device, an electro-optical device, an electronic apparatus, and the like.

  Conventionally, as a liquid crystal panel (electro-optical device, display panel) used in an electronic device such as a cellular phone, a liquid crystal panel of a simple matrix type and an active matrix type liquid crystal using a switching element such as a thin film transistor (Thin Film Transistor). The panel is known.

In recent years, the number of data lines of the liquid crystal panel has increased due to the increase in the screen size of the liquid crystal panel and the increase in the number of pixels, while the accuracy of the voltage applied to each data line is required. Furthermore, due to the demand for lighter and smaller battery-powered electronic devices equipped with a liquid crystal panel, it is also required to reduce the power consumption and the chip size of the amplifier circuit that drives the data lines of the liquid crystal panel. As an integrated circuit device including an amplifier circuit for driving such a data line of a liquid crystal panel, there are conventional techniques disclosed in Patent Documents 1 and 2, for example.
JP 2005-175811 A JP 2005-175812 A

  In such an integrated circuit device, for example, an amplifier circuit for driving a data line of a liquid crystal panel and generating a gradation voltage is provided. So far, a so-called voltage follower-connected amplifier circuit has been used as such an amplifier circuit.

  However, the voltage follower-connected amplifier circuit has a problem in that the output voltage of the data line varies due to the offset voltage of the operational amplifier.

  For this reason, the present applicant has developed an amplifier circuit of a type using a charge storage capacitor. However, in an amplifier circuit using such a charge storage capacitor, there is a problem that an error occurs in the output voltage if the capacitance value of the capacitor has voltage dependency. On the other hand, in such an amplifier circuit, it is desirable to provide a phase compensation capacitor to prevent the oscillation, and how such a charge storage capacitor and a phase compensation capacitor can be efficiently laid out. It becomes a challenge.

  According to some aspects of the present invention, it is possible to provide an amplifier circuit, a reference voltage generation circuit, an integrated circuit device, an electro-optical device, and an electronic device that can achieve both phase compensation and high-accuracy voltage output.

  One aspect of the present invention is an operational amplifier, a charge storage capacitor provided between an input node and a first input terminal of the operational amplifier, a phase compensation capacitor provided at an output terminal of the operational amplifier, The charge storage capacitor is formed of a first type capacitor in which electrodes at both ends are formed of a metal layer or a polysilicon layer, and the phase compensation capacitor has one electrode of a polysilicon layer and the other of the other This is related to an amplifying circuit composed of a second type capacitor formed of an impurity layer.

According to one aspect of the present invention, an appropriate output voltage corresponding to an input voltage can be obtained by using a first type capacitor having no voltage dependence on a capacitance value as a charge storage capacitor provided at an input node of an amplifier circuit. Can be output. In addition, by using the second type capacitor that has a voltage dependency in the capacitance value but can obtain a larger capacitance in the same area as a phase compensation capacitor that is not significantly affected by the voltage dependency, The layout efficiency of the amplifier circuit can be improved while preventing oscillation.

  At this time, in one aspect of the present invention, the phase compensation capacitor may be disposed below the charge storage capacitor in plan view.

  In this way, by effectively using the space below the charge storage capacitor and arranging the phase compensation capacitor, the charge storage capacitor and the phase compensation capacitor can be efficiently used using a small area. Layout can be arranged.

  In one embodiment of the present invention, a first switch element provided between an input node of the amplifier circuit and a first node, a node of the first node and a first input terminal of the operational amplifier A first capacitor provided between the first node and the summing node, a second switch element provided between the first node and the analog reference power source, and a second node between the second node and the summing node. A second capacitor provided; a third switch element provided between the second node and an output node of the amplifier circuit; and provided between the second node and the analog reference power source. A fourth switch element; and a fifth switch element provided between the output node and the summing node, wherein the first capacitor and the second capacitor are the first type. It may be the charge storage capacitor composed of a capacitor.

  In this way, since the output voltage can be continuously output by using the first capacitor and the second capacitor, the amplifier circuit can have an offset cancel function.

  In the aspect of the invention, the phase compensation capacitor may be disposed below the first capacitor and the second capacitor.

  In this way, by effectively using the space below the first capacitor and the second capacitor and arranging the phase compensation capacitor, the first capacitor and the efficient use of a small area can be achieved. The second capacitor and the phase compensation capacitor can be laid out.

  In one embodiment of the present invention, a first capacitor region in which the first capacitor is formed and a second capacitor region in which the second capacitor is formed are arranged along a first direction. When the direction opposite to the first direction is the third direction, the first and second switch elements are disposed on the third direction side of the first and second capacitor regions, When the third and fourth switch elements are arranged on the first direction side of the first and second capacitor regions, and the direction orthogonal to the first direction is the second direction, A summing node line that is a line of the summing node may be wired on the second direction side of the first, second, third, and fourth switch elements.

  According to this configuration, since the first and second switch elements are arranged on the third direction side of the first capacitor region, the first and second switches are connected to the input voltage from the previous circuit by a short path. Can be supplied to the element. In addition, since the third and fourth switch elements are disposed on the first direction side of the second capacitor region, the connection between the subsequent circuit and the third and fourth switch elements can be realized by a short path. Therefore, the layout efficiency can be improved, and the parasitic capacitance that adversely affects the performance can be minimized. According to the invention, the summing node line is wired on the second direction side of the first to fourth switch elements. Accordingly, the distance between the first and second node lines and the summing node line can be increased, and adverse effects caused by parasitic capacitance between these nodes can be minimized.

  In one aspect of the present invention, a first analog reference power supply line for supplying a voltage of the analog reference power supply to the second switch element is provided along the second direction. A second analog reference power line that is wired on the third direction side of the capacitor region and supplies the voltage of the analog reference power source to the fourth switch element along the second direction. Wiring may be performed on the first direction side of the first and second capacitor regions.

  In this way, the analog reference power can be supplied to the second and fourth switch elements by, for example, a short path, and the inner area of the first and second analog reference power lines can be shielded from the outer area. become. Accordingly, it is possible to prevent a situation in which voltage fluctuation or the like in the outer region is transmitted to the summing node through the parasitic capacitance and adversely affects the circuit characteristics.

  In one embodiment of the present invention, the auxiliary capacitor includes an auxiliary capacitor that is electrically connected to one end of the auxiliary capacitor. The auxiliary capacitor includes one electrode formed of a polysilicon layer and the other electrode formed of an impurity layer. It may be configured by a second type capacitor.

  In this way, the voltage variation of the summing node can be suppressed, and the second type capacitor that can obtain a larger capacity in the same area is used as an auxiliary capacitor that is not significantly affected by the voltage dependency. As a result, the layout efficiency of the amplifier circuit can be improved while suppressing the voltage fluctuation of the summing node.

  In the aspect of the invention, the auxiliary capacitor may be disposed below the first capacitor and the second capacitor.

  In this way, the first and second capacitors can be efficiently utilized using a small area by arranging the auxiliary capacitor by effectively utilizing the space below the first capacitor and the second capacitor. And an auxiliary capacitor can be laid out.

  In one embodiment of the present invention, charge corresponding to an input voltage is stored in the charge storage capacitor in a sampling period, and the charge storage capacitor performs a flip-around operation of the charge storage capacitor in a hold period. It is good also as outputting the voltage according to.

  By so doing, so-called offset-free can be realized by providing the amplifier circuit with a function of performing a flip-around operation.

  In one embodiment of the present invention, a sampling switch element provided between an input node and a connection node, the connection node, and a summing node that is a node of a first input terminal of the operational amplifier. A sampling capacitor provided in between; a feedback switch element provided between an output terminal of the operational amplifier and the summing node; and provided between the connection node and the output terminal of the operational amplifier. A flip-around switch element, and an auxiliary capacitor to which the summing node is electrically connected at one end thereof, wherein the sampling capacitor is the charge storage capacitor configured by the first type capacitor. It may be there.

  In this case, the amplifier circuit has a function of performing a flip-around operation, and the capacitor of the first type having no voltage dependency on the capacitance value is used as the charge storage capacitor provided at the input node of the amplifier circuit. A so-called offset-free operation can be realized after outputting an appropriate output voltage corresponding to the input voltage.

  In one embodiment of the present invention, the auxiliary capacitor includes an auxiliary capacitor that is electrically connected to one end of the auxiliary capacitor. The auxiliary capacitor includes one electrode formed of a polysilicon layer and the other electrode formed of an impurity layer. It may be configured by a second type capacitor.

  In this way, the second type capacitor, which has a voltage dependency on the capacitance value but can obtain a larger capacitance in the same area, is used as an auxiliary capacitor that is not significantly affected by the voltage dependency. The layout efficiency of the amplifier circuit can be improved while suppressing the voltage fluctuation of the node.

  According to another aspect of the present invention, an operational amplifier, a charge storage capacitor provided between an input node and a first input terminal of the operational amplifier, and the summing node are electrically connected to one end thereof. The charge storage capacitor is formed of a first type capacitor in which electrodes at both ends are formed of a polysilicon layer or a metal layer, and one electrode is a polysilicon layer. Thus, the present invention relates to an amplifier circuit composed of a second type capacitor in which the other electrode is formed of an impurity layer.

According to another aspect of the present invention, an appropriate output corresponding to an input voltage can be obtained by using a first type capacitor having no voltage dependence on a capacitance value as a charge storage capacitor provided at an input node of an amplifier circuit. The voltage can be output. Further, the voltage variation of the summing node can be obtained by using the second type capacitor, which has a voltage dependency on the capacitance value but can obtain a larger capacitance in the same area, as an auxiliary capacitor that is not significantly affected by the voltage dependency. In addition, the layout efficiency of the amplifier circuit can be improved.

  In the aspect of the invention, the auxiliary capacitor may be disposed below the charge storage capacitor.

  In this way, by effectively using the space below the charge storage capacitor and arranging the auxiliary capacitor, the charge storage capacitor and the auxiliary capacitor can be efficiently laid out using a small area.

  According to another aspect of the present invention, there is provided a reference voltage generation circuit that generates a plurality of reference voltages. The first power supply and the second power supply are voltage-divided, and a plurality of divided voltages are applied to a plurality of voltage division nodes. An amplifier having a voltage generation circuit for output and the amplifier circuit according to any one of the above, wherein the amplifier circuit performs impedance conversion of the plurality of divided voltages from the voltage generation circuit and outputs the plurality of reference voltages And a reference voltage generation circuit.

  According to another aspect of the present invention, there is provided an integrated circuit device for driving an electro-optical panel, the reference voltage generation circuit according to any one of the above, and the plurality of reference voltages from the reference voltage generation circuit. The present invention relates to an integrated circuit device including a data driver that receives a plurality of gradation voltages and image data and drives a plurality of data lines of the electro-optical panel.

  Another aspect of the invention relates to an electro-optical device including any of the integrated circuit devices described above and an electro-optical panel.

  Another aspect of the invention relates to an electronic apparatus including the electro-optical device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as means for solving the present invention. Not necessarily.

1. Amplifier circuit 1.1. Basic Configuration FIG. 1 shows the basic configuration of the amplifier circuit of this embodiment. Note that the amplifier circuit according to the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The amplifier circuit of this embodiment is provided in, for example, a gradation voltage generation circuit or a data driver of an integrated circuit device that drives an electro-optical panel (electro-optical device). As shown in FIG. 1, the input voltage VIN In response to this, the output voltage VQ is output to drive a drive target (for example, a data line), and includes a charge storage capacitor CA and a phase compensation capacitor CC. An operational amplifier OP can also be included.

  The operational amplifier OP has a summing node NEG connected to its inverting input terminal (first input terminal in a broad sense) and an AGND (analog reference power supply) to its non-inverting input terminal (second input terminal in a broad sense). The output voltage VQ is output to the output node NQ (output terminal).

  The charge storage capacitor CA is provided between the input node NI and the first input terminal (summing node NEG) of the operational amplifier OP.

  In the present embodiment, the charge storage capacitor CA is configured by a first type capacitor Type 1 as shown in FIG. The first type capacitor Type 1 is a capacitor in which electrodes at both ends are formed of a metal layer (or polysilicon layer). For example, in the first type capacitor Type1, the first electrode (terminal TMA) is formed of a first metal layer META such as an aluminum layer, and the second electrode (terminal TMB) is a second layer such as an aluminum layer. This is an MIM (Metal Insulator Metal) type capacitor formed by providing an interlayer insulating layer ISA between the first and second metal layers META and METB. Note that a polysilicon layer can be used instead of the metal layer as the electrode of the charge storage capacitor CA. For example, the first and second electrodes of the first type capacitor Type 1 can be formed of first and second polysilicon layers.

  The phase compensation capacitor CC is provided at the output terminal of the operational amplifier OP. In the present embodiment, the phase compensation capacitor CC is a second type capacitor in which one electrode (terminal TMC1) is a polysilicon layer and the other electrode (terminal TMC2) is an impurity layer (for example, a diffusion layer). Composed. As shown in the cross-sectional structure of FIG. 2B, the phase compensation capacitor CC (or an auxiliary capacitor described later) is formed using the gate capacitance of the transistor.

  Specifically, in FIG. 2B, a high-concentration N-type well DNWL (deep N-well) is formed on a silicon substrate, and a P-type well PWL is formed on the N-type well DNWL. The P-type well PWL is supplied with a low-potential-side power supply voltage via a P + impurity layer (diffusion layer).

  An NCU that is an N + cross under impurity layer is formed on the P-type well PWL. A polysilicon layer that is a gate of the transistor is formed above the NCU. The polysilicon layer becomes the upper electrode of the capacitor, and the impurity layer of the NCU becomes the lower electrode. If the capacitor structure using the NCU is used as described above, a large capacitance value can be obtained with a small layout area.

  In the second type capacitor (gate capacitance, NCU) having such a configuration, since the capacitance value has voltage dependency, the capacitance value changes according to the applied voltage. Therefore, if the second type capacitor Type 2 is used for the charge storage capacitor CA provided at the input node NI of the amplifier circuit, the charge stored in accordance with the voltage also changes, so that an error occurs in the output voltage of the amplifier circuit. Will occur. Accordingly, it becomes impossible to output an appropriate output voltage VQ corresponding to the input voltage VI. On the other hand, if the first type capacitor Type 1 is used, such a problem can be prevented and an appropriate output voltage VQ can be output.

  On the other hand, since the phase compensation capacitor CC performs phase compensation with a certain margin, there is no problem even if the capacitance has voltage dependency. Therefore, even if the second type capacitor Type 2 is used as the phase compensation capacitor CC, no significant problem occurs. In addition, the second type capacitor Type 2 can obtain a larger capacitance in the same area than the first type capacitor Type 1 by reducing the thickness of the oxide film, for example, and can improve the layout efficiency. .

1.2. First Configuration Example FIG. 3 shows a first configuration example of the amplifier circuit of this embodiment. Note that the amplifier circuit of the present embodiment is not limited to the configuration shown in FIG. 3, and various modifications such as omitting some of the components (for example, operational amplifiers) or adding other components are possible. It is.

  As shown in FIG. 3, the amplifier circuit is a circuit that receives an input voltage VIN, outputs an output voltage VQ, and drives a drive target (for example, a data line), and includes first and second capacitors C1 and C2. The first to fifth switch elements SW1 to SW5 are included. An operational amplifier OP can also be included. Furthermore, a phase compensation capacitor CC that prevents oscillation by compensating the phase of the operational amplifier OP is included.

  The first capacitor C1 is provided between the summing node NEG (negative node, inverting input terminal node, charge storage node) and the first node N1. The second capacitor C2 is provided between the summing node NEG and the second node N2. Each of these capacitors C1 and C2 functions as a charge storage capacitor CA and can be constituted by a plurality of unit capacitors, for example. In the present embodiment, as the first and second capacitors C1 and C2, the first type capacitor (Type1) described with reference to FIGS. 1 and 2A is employed.

  The first switch element SW1 is provided between the input node NI of the input voltage VIN to the amplifier circuit and the first node N1. The second switch element SW2 is provided between the first node N1 and AGND (analog reference power supply in a broad sense). The third switch element SW3 is provided between the second node N2 and the output node NQ of the amplifier circuit. The fourth switch element SW4 is provided between the second node N2 and AGND (AGND node). The fifth switch element SW5 is provided between the summing node NEG and the output node NQ.

  These switch elements SW1 to SW5 can be constituted by, for example, CMOS transistors. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown). AGND is, for example, an intermediate voltage (for example, AGND = (VDD + VSS) / 2) between the high potential side power source VDD (second power source) and the low potential side power source VSS (first power source).

  The phase compensation capacitor CC is provided at the output terminal of the operational amplifier OP. By providing such a phase compensation capacitor CC, it is possible to prevent oscillation of the operational amplifier OP. In the present embodiment, the second type capacitor (Type 2) described in FIGS. 1 and 2B is employed as the phase compensation capacitor CC.

  The operational amplifier OP has a summing node NEG connected to its inverting input terminal (first input terminal in a broad sense) and an AGND (analog reference power supply) to its non-inverting input terminal (second input terminal in a broad sense). The output voltage VQ is output to the output node NQ (output terminal).

  As shown in FIG. 3, in the amplifier circuit, the switch elements SW2, SW4, and SW5 are turned on in an initialization period, which is a period for setting an initialization voltage to the charge storage capacitors C1 and C2.

  When the switch element SW2 is turned on in the initialization period, the other end of the capacitor C1 whose one end is electrically connected to the summing node NEG is set to AGND (analog reference power supply voltage VA). Similarly, when the switch element SW4 is turned on, the other end of the capacitor C2 whose one end is electrically connected to the summing node NEG is set to AGND (VA). When the switch element SW5, which is a feedback switch element, is turned on, the output of the operational amplifier OP is fed back to the inverting input terminal, and the node NEG is set to AGND by the imaginary short function of the operational amplifier OP.

  Further, as shown in FIG. 4, in the amplifier circuit, the switch elements SW1 and SW3 are turned on in an output period in which an output voltage is output and a drive target is driven.

  When the switch element SW1 is turned on in the output period, the other end of the capacitor C1 whose one end is connected to the summing node NEG is set to the input voltage VIN. Further, when the switch element SW3 is turned on, the other end of the capacitor C2 whose one end is connected to the summing node NEG is set to the output voltage VQ (output of OP).

  FIG. 5 shows an example of signal waveforms for explaining the operation of the amplifier circuit. In FIG. 5, VA is an AGND voltage, for example, VA = (VDD + VSS) / 2. However, VA may be a voltage between VDD and VSS, and is not limited to (VDD + VSS) / 2.

  In the initialization period of FIG. 3, since the feedback switch element SW5 is turned on, the node NEG of the inverting input terminal of OP is at the voltage of AGND of the non-inverting input terminal by the imaginary short function of the operational amplifier OP. It becomes equal to a certain VA. However, since the operational amplifier OP has an offset due to process variations and the like, a voltage difference of the offset voltage ΔV is generated between the voltage of the node NEG and VA as shown in FIG.

  In the amplifier circuit, the offset voltage ΔV is stored in the initialization period of FIG. 3, and the offset voltage ΔV is canceled and the output voltage VQ is output in the output period of FIG. .

  As shown in FIG. 5, during the output period, when the input voltage VIN changes to the high potential side (VDD side), the output voltage VQ changes to the low potential side (VSS side), and VIN changes to the low potential side. Then, VQ changes to the high potential side.

  FIG. 6A shows a basic configuration of the amplifier circuit. As shown in FIG. 6A, the amplifier circuit 60 has one end connected to the summing node NEG, the other end set to the analog reference voltage VA in the initialization period, and the input voltage VIN in the output period. The first capacitor C1 set to be included. Further, it is only necessary to include a second capacitor C2 whose one end is connected to the summing node NEG, the other end is set to the analog reference voltage VA in the initialization period, and set to the output voltage VQ in the output period.

  Note that the summing node NEG (the connection node between C1 and C2) is set to a given voltage (for example, VA, VA−ΔV) in the initialization period, and in the high impedance state (floating state) in the output period, the initialization period Any node may be used as long as it is set to the same potential as that. In order to realize such a function of the summing node NEG, the operational amplifier OP is used in FIGS. 3 and 4, but such a function may be realized by a circuit other than the operational amplifier OP.

  Next, the relationship between the input voltage VIN and the output voltage VQ in the amplifier circuit is described with reference to FIGS. 6B and 6C.

  As shown in FIG. 6B, in the initialization period, VA is set at one end of the capacitors C1 and C2, and VA−ΔV is set at the other end. Here, ΔV is an offset voltage of the operational amplifier OP.

On the other hand, as shown in FIG. 6C, in the output period, VIN is set at one end of the capacitor C1, and VA−ΔV is set at the other end, VQ is set at one end of the capacitor C2, and VA−ΔV is set at the other end. Is set. Therefore, the following equation is established by the law of charge conservation.
C1 × {(VA− (VA−ΔV)} + C2 × {(VA− (VA−ΔV)}
= C1 × {VIN− (VA−ΔV)} + C2 × {VQ− (VA−ΔV)} (1)

Therefore, the following formula is established.
VQ = VA− (C1 / C2) × (VIN−VA) (2)

  As apparent from the above equation (2), since the offset voltage ΔV does not appear in the output voltage VQ, so-called offset free can be realized.

  For example, as an amplifier circuit, charge corresponding to the input voltage is accumulated in the sampling capacitor during the sampling period, and a flip-around operation of the sampling capacitor is performed during the hold period to output a voltage corresponding to the accumulated charge. An amplifier circuit is conceivable.

  However, in this flip-around amplifier circuit, the output of the amplifier circuit is in a high-impedance state during the sampling period, resulting in a loss in driving time.

  On the other hand, in the amplifier circuit shown in FIGS. 3 and 4, by using two capacitors C1 and C2, the output voltage VQ can be continuously output. That is, in the output period after the initialization period, there is no sampling period, and the output voltage VQ corresponding to the input voltage VIN is output according to the above equation (2), so that the drive target can be continuously driven. Become.

  As described above, in the amplifier circuit of this embodiment shown in FIGS. 3 and 4, charges corresponding to the offset voltage of the operational amplifier OP are stored in the capacitors C1 and C2 in the initialization period. Thereby, in the output period, the offset voltage of the operational amplifier OP can be canceled and output.

  Further, after passing through the initializing period once, the amplifier circuit of this embodiment always outputs an output voltage corresponding to the input voltage in the output period like an operational amplifier having a voltage follower connection. Specifically, an output voltage in which the input voltage is inverted and the offset is canceled is output. Therefore, since there is no sampling period and hold period unlike the sample hold circuit, the output of the amplifier circuit does not enter a high impedance state during the output period. For this reason, timing control becomes easier and a longer driving time can be secured as compared with the sample hold circuit as the comparative example.

  Further, in the present embodiment, by applying the amplifier circuit of FIGS. 3 and 4 to, for example, a gradation voltage generation circuit to be described later, it is possible to reduce variations in gradation voltage caused by variations in offset voltage of the operational amplifier. . Further, by applying this amplifier circuit to a data driver described later, it is possible to reduce variations in data voltage caused by variations in offset voltage, and to prevent occurrence of display unevenness. Further, the input voltage is inverted by the gradation voltage generation circuit and is inverted again by the data driver, so that a normal data voltage can be supplied to the data line after all. Furthermore, by applying the amplifier circuit of this embodiment that enables continuous output of the output voltage VQ to both the gradation voltage generation circuit and the data driver, it is possible to facilitate timing control and ensure a long driving time. It can be realized at the same time.

  In the present embodiment, the first type capacitors (Type 1) shown in FIG. 2A are used as the charge storage capacitors C1 and C2. Accordingly, since the voltage dependency of the capacitance value of the capacitor can be ignored, VQ = VA− (C1 / C2) × (VIN−VA) in the above equation (2) is accurately established, and the output voltage VQ has an error. Can be prevented.

  On the other hand, in the present embodiment, the second type capacitor (Type 2) of FIG. 2B is used as the phase compensation capacitor CC. This second type capacitor has an advantage that a large capacitance value can be obtained with a small layout area, although the capacitance value has voltage dependency. Therefore, by using the first type as the capacitors C1 and C2 and using the second type as the capacitor CC in this way, both high-accuracy output voltage and phase compensation with a small layout area can be realized. become able to.

1.3. Second Configuration Example FIGS. 7 and 8 show a second configuration example of the amplifier circuit of this embodiment. 7 and 8, a switch element SW7 and a resistor R1 are further provided between the output node NQ of the operational amplifier OP and the phase compensation capacitor CC as compared with FIGS. 7 and 8, a switch element SW6 for preventing the output voltage during the initialization period from being transmitted to the subsequent circuit is provided at the output node NQ (NQ ') of the amplifier circuit. The switch element SW6 is turned off in the initialization period of FIG. 7, and is turned on in the output period of FIG.

  Further, in FIGS. 7 and 8, an auxiliary capacitor CAX having one end connected to the summing node NEG is provided. Providing such an auxiliary capacitor CAX can suppress voltage fluctuations at the summing node NEG, which is a node of the inverting input terminal of the operational amplifier OP, and can further stabilize the output voltage VQ.

  Specifically, at the moment of transition from the initialization period of FIG. 7 to the output period of FIG. 8, the voltage of the summing node NEG varies as shown in FIG. In this case, if the auxiliary capacitor CAX is not provided, the voltage of the summing node NEG varies instantaneously by the potential difference between the node N2 and the node NQ (NQ ') at the end of the initialization period. If the voltage of the summing node NEG at this time exceeds VDD or VSS, which is the substrate voltage of the switch element SW5, the charges accumulated in the capacitors C1 and C2 are lost. In order to prevent this, an auxiliary capacitor CAX is provided in FIGS. In this way, the capacitor C2 and the capacitor CAX connected in series are provided between the nodes NQ and AGND, and the voltage variation of the summing node NEG is suppressed to the range of VDD to VSS, and C1, The situation where the accumulated charge of C2 is lost can be prevented.

  In the present embodiment, the second type capacitor shown in FIG. 2B is used as the auxiliary capacitor CAX. In this way, the auxiliary capacitor CAX having a high capacitance value can be obtained with a small layout area, and the output voltage VQ can be stabilized.

  In the present embodiment, as the operational amplifier OP, for example, an amplifier of a type that does not include a phase compensation capacitor is used. That is, in the output period, as shown in FIG. 8, since the switch element SW6 is turned on, the output of the operational amplifier OP is connected to a drive target such as a data line serving as a load. Therefore, this load (for example, 20 pF) functions as a phase compensation capacitor and can prevent oscillation of the operational amplifier OP.

  However, since the switch element SW6 is turned off in the initialization period of FIG. 7, a load such as a data line is not connected to the operational amplifier OP, and the loads of the operational amplifier OP are capacitors C1 and C2 and auxiliary capacitors. Only CAX (for example, 1 pF load). Therefore, the load on the operational amplifier OP decreases, and the operational amplifier OP may oscillate.

  Therefore, in FIG. 7 and FIG. 8, in the initialization period, one end is electrically connected to the output node NQ ′, and a phase compensation capacitor CC is provided to prevent oscillation by compensating the phase of the operational amplifier OP. . Specifically, a phase compensation capacitor CC and a phase compensation switch element SW7 are provided between the node NQ 'and the low potential side power supply. In the initialization period of FIG. 7, the switch element SW7 is turned on and one end of the phase compensation capacitor CC is connected to the output node NQ ′, while in the output period of FIG. 8, the switch element SW7 is turned off and connected. Shut off.

  If the phase compensation capacitor CC and the phase compensation switch element SW7 are provided, the phase compensation capacitor CC compensates for the phase of the operational amplifier OP during the initialization period in which the load of the operational amplifier OP is reduced. It is possible to effectively prevent oscillation of the operational amplifier OP. In FIG. 7, resistors R1 and R2 for phase compensation (for preventing oscillation) are further provided.

  As described above, in the second configuration example of the present embodiment shown in FIGS. 7 and 8, the switch element SW6 provided at the output node NQ (NQ ′) of the amplifier circuit is turned off during the initialization period. The capacity of the capacitor added to the output of the operational amplifier OP is reduced. Therefore, in the initialization period, the phase compensation switch element SW7 is turned on so that the phase compensation capacitor CC is connected to the output of the operational amplifier OP.

  On the other hand, in the output period, since the parasitic capacitance of the gradation voltage output line is added to the operational amplifier OP of the gradation voltage generation circuit, phase compensation can be performed by this parasitic capacitance. Further, since the parasitic capacitance of the data line of the electro-optical panel is added to the output of the operational amplifier OP of the data driver, phase compensation can be performed by this parasitic capacitance.

  FIG. 9 shows a circuit configuration example of the operational amplifier OP included in the amplifier circuit of the present embodiment. The operational amplifier OP shown in FIGS. 3, 4, 7, and 8 is an amplifier that performs class AB amplification. In FIG. 9, the transistors TA1 to TA4 and the current source IS1 constitute an amplifier differential stage. Further, the gates of the P-type transistor TA17 and the N-type transistor TA18 constituting the output stage are controlled by an auxiliary circuit constituted by the transistors TA7 to TA14, thereby enabling a class AB amplification operation.

1.4. Layout Layout Example FIG. 10 shows a layout layout example of the amplifier circuit of this embodiment. In FIG. 10, the direction opposite to the first direction D1 is the third direction D3, the direction orthogonal (crossing) to the first direction D1 is the second direction D2, and the direction opposite to the second direction D2 Is the fourth direction D4.

  In FIG. 10, the first capacitor region C1R in which the capacitor C1 of FIGS. 7 and 8 is formed and the second capacitor region C2R in which the capacitor C2 is formed are arranged along the direction D1. A modification in which the capacitor regions C1R and C2R are arranged along the direction D2 is also possible.

  In the present embodiment, the phase compensation capacitor CC includes the first capacitor region C1R and the second capacitor in which the first capacitor C1 and the second capacitor C2 that are the charge storage capacitors CA are formed in plan view. Arranged below region C2R. In other words, the phase compensation capacitor region CCR in which the phase compensation capacitor CC is formed is formed by effectively using the space below the first capacitor region C1R and the second capacitor region C2R.

  The switch elements SW1 and SW2 are arranged on the D3 direction side of the capacitor regions C1R and C2R. The switch elements SW3 and SW4 are disposed on the D1 direction side of the capacitor regions C1R and C2R. The switch element SW5 is disposed on the D2 direction side of the switch elements SW3 and SW4.

  The line LNEG of the summing node NEG is wired on the D2 direction side of the switch elements SW1, SW2, SW3, and SW4. Specifically, the line LNEG (at least a part of the wirings; the connection wiring in the upper layer of the wiring layer constituting the capacitor) is wired along the D1 direction on the D2 direction side of SW1, SW2, SW3, and SW4.

  According to the layout arrangement of FIG. 10, since the switch elements SW1 and SW2 are arranged on the D3 direction side of the capacitor region C1R, the input voltage VIN from the previous stage circuit is transferred to the switch elements SW1 and SW2 (capacitor C1) through a short path. Can supply. Further, since the switch elements SW3 and SW4 are arranged on the D1 direction side of the capacitor region C2R, the connection between the subsequent circuit (for example, operational amplifier) and the switch elements SW3 and SW4 (capacitor C2) can be realized by a short path. Therefore, layout efficiency can be improved, and parasitic capacitance and parasitic resistance that adversely affect performance can be minimized.

  In FIG. 10, a summing node line LNEG is wired on the D2 direction side of the switch elements SW1 to SW4. Therefore, the distance between the lines of the nodes N1 and N2 and the summing node line LNEG can be increased. Therefore, when the parasitic capacitance value between the nodes N1 and NEG is CP1, and the parasitic capacitance value between the nodes N2 and NEG is CP2, the difference value CPD between the parasitic capacitance values CP1 and CP2 is minimized. Is possible.

  That is, when the difference value CPD of the parasitic capacitance increases, C1 / C2 changes in VQ = VA− (C1 / C2) × (VIN−VA) described in the above equation (2), and the output voltage VQ is It will fluctuate. Further, when a plurality of data lines are driven by a plurality of drive circuits as will be described later, the output voltage VQ varies between the drive circuits due to process variations, resulting in a problem that display quality deteriorates.

  In this case, if the wiring shape is formed symmetrically, the adverse effect of the difference value CPD can be eliminated. However, for example, if there is a wiring portion that is not symmetrical as shown by A1 in FIG. The influence of the difference value CPD cannot be ignored.

  In this regard, in FIG. 10, since the distance between the lines of the nodes N1 and N2 and the summing node line LNEG can be separated, the absolute values of the parasitic capacitance values CP1 and CP2 between the nodes N1 and N2 and NEG can be reduced. . Therefore, even if there is a portion where the symmetry is broken as shown by A1, since the absolute value of the difference value CPD is small, the adverse effect of the difference value CPD can be minimized.

  Further, in the layout arrangement of FIG. 10, when a line along the direction D2 passing between the capacitor regions C1R and C2R is used as a symmetry axis, a layout arrangement that is line-symmetric with respect to this symmetry axis is possible. Therefore, adverse effects such as the difference value CPD can be further reduced.

  In FIG. 10, a first analog reference power supply line LA1 for supplying a voltage of AGND (analog reference power supply) to the switch element SW2 is wired along the D2 direction on the D3 direction side of the capacitor regions C1R and C2R. . On the other hand, a second analog reference power line LA2 for supplying the voltage AGND to the switch element SW4 is wired along the D2 direction on the D1 direction side of the capacitor regions C1R and C2R.

  As shown in FIG. 10, if the AGND lines LA1 and LA2 are wired, AGND can be supplied to the switch elements SW2 and SW4 through a short path, and the area inside the lines LA1 and LA2 can be shielded from the outside area by AGND. It becomes like this. Therefore, for example, it is possible to effectively prevent a situation in which fluctuations in the input voltage VIN and output voltage at the input node NI are transmitted to the node NEG via the parasitic capacitance and adversely affect circuit characteristics. In addition, since the lines LA1 and LA2 can be line-symmetrically arranged with respect to the above-described symmetry axis, a line-symmetric layout is possible, and adverse effects such as the difference value CPD can be reduced.

  For the line LNEG of the summing node NEG, it is desirable to further wire a shield line set to the potential of AGND on the left side, the right side, or the upper side or the lower side.

  FIG. 11 is a cross-sectional view for explaining an example layout layout of the amplifier circuit shown in FIGS. As shown in FIG. 11, a polysilicon layer PLY that is a gate of the transistor is formed above the NCU that is an N + cross under impurity layer via a gate insulating film layer IS0. The polysilicon layer PLY serves as the upper electrode of the phase compensation capacitor CC, and the NCU impurity layer serves as the lower electrode.

  A metal layer META is formed above the polysilicon layer PLY via a first interlayer insulating layer IS1, and above the metal layer META, a metal layer METB1 and a metal layer METB2 via a second interlayer insulating layer IS2. Is formed. The first capacitor C1 is formed by the metal layer META, the metal layer METB1, and the second interlayer insulating layer IS2. The second capacitor C2 is formed by the metal layer META, the metal layer METB2, and the second interlayer insulating layer IS2. In this way, the phase compensation capacitor CC is disposed below the first capacitor C1 and the second capacitor C2 that serve as charge storage capacitors.

  Thus, if the layout is made such that the phase compensation capacitor CC that is the second type capacitor Type2 is formed below and the first type capacitor Type1 is formed above the second type capacitor Type2, a small area is obtained. The first capacitor C1 and the second capacitor C2 and the phase compensation capacitor CC, which are efficient charge storage capacitors, can be laid out.

1.5. Third Configuration Example FIGS. 12 and 13 show a third configuration example of the amplifier circuit of this embodiment. The amplifier circuit of the third configuration example is used in a gradation voltage generation amplifier circuit included in the gradation amplifier section of the gradation voltage generation circuit (see FIG. 18), as shown in FIGS. 7. Compared to the second configuration example of the present embodiment shown in FIG. 8, a third capacitor C3 is further provided at one end of which an output node NQ of the amplifier circuit is electrically connected via a resistor R3. Yes. An eighth switch element SW8 is provided between the output node NQ of the amplifier circuit and the connection node NCC between the seventh switch element SW7 and the phase compensation capacitor CC. Here, the third capacitor C3 is a capacitor for phase compensation (output stabilization) of the amplifier circuit.

  In the initialization period, as shown in FIG. 12, the switch element SW6 and the eighth switch element SW8 provided on the output node NQ side are turned off, and the phase compensation switch element SW7 is turned on. As described above, in the initialization period, the switch element SW6 serving as the output switch of the amplifier circuit is turned off, so that the capacitance of the capacitor added to the output node NQ of the operational amplifier OP is reduced. Therefore, by turning on the phase compensation switch SW7, the phase compensation capacitor CC is connected to the output node NQ 'on the output terminal side of the operational amplifier OP, and the phase compensation of the operational amplifier OP is performed.

  On the other hand, during the output period, as shown in FIG. 13, the switch element SW6 and the eighth switch element SW8 are turned on, and the phase compensation switch element SW7 is turned off. In other words, in the output period, in addition to the parasitic capacitance added to the operational amplifier OP, the third capacitor C3 and the phase compensation capacitor CC are also effectively used, so that the phase compensation is performed by the parasitic capacitance and the capacitors C3 and CC. (Output stabilization) becomes possible. For example, when the amplifier circuit is used for a data driver or a gradation voltage generation circuit to be described later, a parasitic capacitance (for example, a data line or gradation) added to the output of the operational amplifier OP of the data driver or the gradation voltage generation circuit. By effectively utilizing the third capacitor C3 and the phase compensation capacitor CC in addition to the parasitic capacitance of the voltage line, phase compensation can be performed by the parasitic capacitance and the capacitors C3 and CC. Further, for example, when the gradation voltage output from the operational amplifier OP of the gradation amplifier section of the gradation voltage generation circuit is not selected at all by the D / A conversion circuit of the data driver, the output node In some cases, the load applied to NQ becomes the smallest, and the operational amplifier OP of the gradation amplifier unit becomes the minimum load during output. In preparation for such a situation, in the third configuration example, as described above, phase compensation at the time of output is performed.

  In the present embodiment, the third capacitor C3 is not affected so much by the voltage dependence as the phase compensation capacitor CC, so the second type capacitor (Type2) in FIG. Used. Thus, like the phase compensation capacitor CC, as the third capacitor C3, the second type capacitor (Type 2) that has a voltage dependency on the capacitance value but can obtain a larger capacitance in the same area is used. Thus, the layout efficiency of the amplifier circuit can be improved while preventing the operational amplifier OP from oscillating.

  FIG. 14A shows an overall layout arrangement example of the third configuration example of the amplifier circuit of the present embodiment. In FIG. 14A, the direction opposite to the first direction D1 is the third direction D3, the direction orthogonal (crossing) to the first direction D1 is the second direction D2, and the second direction D2 The opposite direction is the fourth direction D4.

  In FIG. 14, the first capacitor region C1R where the capacitor C1 of FIGS. 12 and 13 is formed and the second capacitor region C2R where the capacitor C2 is formed are arranged along the direction D1. A modification in which the capacitor regions C1R and C2R are arranged along the direction D2 is also possible.

  In the present embodiment, the phase compensation capacitor region CCR in which the phase compensation capacitor CC is formed has a first capacitor C1 and a second capacitor C2 that are charge storage capacitors CA in plan view. The first capacitor region C1R and the second capacitor region C2R are disposed below. In other words, the phase compensation capacitor region CCR in which the phase compensation capacitor CC is formed is formed by effectively using the space below the first capacitor region C1R and the second capacitor region C2R.

  The first switch element region SWR1 in which the switch elements SW1 and SW2 are formed is disposed on the D3 direction side of the capacitor regions C1R and C2R. The second switch element region SWR2 in which the switch elements SW3, SW4, and SW5 are formed is arranged on the D1 direction side of the capacitor regions C1R and C2R.

  The auxiliary capacitor region CAXR in which the auxiliary capacitor CAX is formed is disposed on the D1 direction side of the first switch element region SWR1.

  The operational amplifier region OPR in which the operational amplifier OP is formed is disposed on the D1 direction side of the auxiliary capacitor region CAXR.

  The third capacitor region C3R in which the third capacitor C3 is formed is disposed on the D1 direction side of the operational amplifier region OPR.

  In the capacitor regions CAXR and C3R, in order to obtain a large capacitance value with a small layout area, it is desirable to form the auxiliary capacitor CAX and the third capacitor C3 in both the first type and the second type.

  According to the layout arrangement of FIG. 14A, the switch elements SW1 and SW2 are arranged on the D3 direction side of the capacitor region C1R. C1). In addition, since the switch elements SW3 and SW4 are arranged on the D1 direction side of the capacitor region C2R, the connection between the subsequent circuit (for example, an operational amplifier) and the switch elements SW3 and SW4 (capacitor C2) can be realized by a short path. Therefore, layout efficiency can be improved, and parasitic capacitance and parasitic resistance that adversely affect performance can be minimized.

  As a modification of the present embodiment, as shown in FIG. 14B, the auxiliary capacitor region CAXR in which the auxiliary capacitor CAX is formed includes the first capacitor C1 and the second capacitor C2 in plan view. It may be arranged below the first capacitor region C1R and the second capacitor region C2R. In other words, a layout having the auxiliary capacitor region CAXR in which the auxiliary capacitor CAX is formed may be used by effectively utilizing the space below the first capacitor region C1R and the second capacitor region C2R.

1.6. Fourth Configuration Example FIGS. 15A, 15B, and 16 show a fourth configuration example of the amplifier circuit of this embodiment. The amplifying circuit of the fourth configuration example stores the charge according to the input voltage (input signal) in the sampling capacitor during the sampling period, and performs the flip-around operation of the sampling capacitor during the hold period and accumulates it. This is applied to a flip-around type sample-and-hold circuit that outputs a voltage corresponding to the charged charges to its output node. This flip-around sample-and-hold circuit can be used, for example, for a gradation generation amplifier and a drive amplifier included in an integrated circuit device. As shown in FIG. 15A, the amplifier circuit of the fourth configuration example accumulates electric charge according to the input voltage VI in the sampling capacitor CS in the sampling period, and as shown in FIG. In the hold period, a flip-around operation of the sampling capacitor CS is performed to output a voltage VQ corresponding to the accumulated charge.

  As shown in FIG. 16, the amplifier circuit of the fourth configuration example includes an operational amplifier OP, a sampling switch element SS, a sampling capacitor CS, a feedback switch element SF, a flip-around switch element SA, and an auxiliary circuit. A capacitor CAX and a phase compensation capacitor CC are included. It should be noted that modifications such as omitting some of these components or adding other components are possible. In addition, the switch elements SS, SA, and SF can be configured by CMOS transistors such as transfer gates, for example.

  An analog reference power supply voltage AGND is set to the non-inverting input terminal (second input terminal) of the operational amplifier OP1.

  The sampling switch element SS is provided between the input node NI of the sample hold circuit and the connection node NS. The sampling capacitor CS is a charge storage capacitor configured by the first type capacitor of the present embodiment provided between the connection node NS and the summing node NEG. The feedback switch element SF is provided between the node NQ of the output terminal of the operational amplifier OP and the summing node NEG. The flip-around switch element SA is provided between the connection node NS and the node NQ of the output terminal of the operational amplifier OP.

  In the fourth configuration example, an auxiliary capacitor CAX is provided at one end so that the summing node NEG is electrically connected. In the present embodiment, the auxiliary capacitor CAX is composed of a second type capacitor Type 2 in which one electrode is a polysilicon layer and the other electrode is an impurity layer.

  In the sampling period, the sampling switch element SS and the feedback switch element SF are turned on, and the flip-around switch element SA is turned off. Accordingly, the sampling operation of the amplifier circuit can be realized as the flip-around sample-and-hold circuit described with reference to FIG.

  On the other hand, in the hold period, the sampling switch element SS and the feedback switch element SF are turned off, and the flip-around switch element SA is turned on. Accordingly, the hold operation of the amplifier circuit can be realized as the flip-around type sample-and-hold circuit described with reference to FIG.

  If such a flip-around sample-and-hold circuit is used, so-called offset free can be realized. Therefore, for example, when a sample and hold circuit to which the amplifier circuit of the present embodiment is applied is applied to, for example, a data line driving circuit, variations in output voltage between data lines can be minimized. Thereby, a highly accurate voltage with little variation can be supplied to the data line, and display quality can be improved. In addition, since DAC driving for directly driving the data line by the D / A conversion circuit is not necessary, high-speed driving and simplification of control can be realized.

2. Reference Voltage Generation Circuit FIG. 17 shows a configuration example of a reference voltage generation circuit including the amplifier circuit of this embodiment. Note that the reference voltage generation circuit of the present embodiment is not limited to the configuration of FIG. 17, and various modifications such as omitting some of the components or adding other components are possible.

  The reference voltage generation circuit 11 of the present embodiment is a circuit that generates a plurality of reference voltages V1 to Vn. Specifically, the reference voltage generation circuit 11 performs resistance division between the high potential side voltage VGMH and the low potential side voltage VGML, and supplies the divided voltages VD1 to VDn to the divided nodes N1 to Nn (n is an integer of 2 or more). A ladder resistor circuit (voltage generation circuit in a broad sense) 12 that outputs and an amplifier unit 14 that impedance-converts divided voltages VD1 to VDn at the divided nodes N1 to Nn and outputs reference voltages V1 to Vn can be included.

  The ladder resistor circuit 12 generates a voltage provided between a high potential side power source VGMH (first power source in a broad sense) serving as a reference voltage and a low potential side power source VGML (second power source in a broad sense). Circuit. The ladder resistor circuit 12 includes a plurality of resistor circuits (variable resistors) R0 to Rn connected in series, and each of the voltage dividing nodes N1 to Nn divided by the plurality of resistor circuits R0 to Rn. The voltage is output as divided voltages VD1 to VDn.

  The amplifier unit 14 performs impedance conversion on the divided voltages VD1 to VDn at the divided nodes N1 to Nn of the ladder resistor circuit 12 serving as a voltage generation circuit. In the present embodiment, the amplifier unit 14 includes reference voltage generating amplifier circuits GAM1 to GAMn corresponding to the divided voltages VD1 to VDn input from the ladder resistor circuit 12 via the plurality of divided voltage output lines VDL1 to VDLn, The reference voltage generating amplifier circuits GAM1 to GAMn perform impedance conversion of the divided voltages VD1 to VDn. The plurality of divided voltages VD1 to VDn impedance-converted by the reference voltage generating amplifier circuits GAM1 to GAMn are used as a plurality of reference voltages V1 to Vn as a plurality of reference voltage output lines (grayscale voltage output lines) VL1. To VLn.

3. Integrated Circuit Device FIG. 18 shows a configuration example of the integrated circuit device 10 of the present embodiment, and particularly shows a configuration example of a gradation voltage generation circuit and a data driver included in the integrated circuit device 10. Note that the integrated circuit device 10 of the present embodiment is not limited to the configuration of FIG. 18, and various modifications may be made such as omitting some of the components or adding other components.

  The integrated circuit device 10 of the present embodiment has a function of driving the electro-optical panel 400 (electro-optical device) and outputs a plurality of gradation voltages (reference voltages in a broad sense) V1 to Vn. (Reference voltage generation circuit in a broad sense) 110, data for driving the electro-optical panel 400 in response to a plurality of gradation voltages V1 to Vn and image data (gradation data, display data) GD supplied from the outside. And a driver 50.

  The electro-optical panel 400 (electro-optical device) includes a plurality of data lines (for example, source lines), a plurality of scanning lines (for example, gate lines), and a plurality of pixels specified by the data lines and the scanning lines. Then, the display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element or an EL element) in each pixel region. The electro-optical panel 400 (display panel in a narrow sense) can be constituted by, for example, an active matrix type panel using a switching element such as a TFT or a TFD. The electro-optical panel may be a panel other than the active matrix system, or may be a panel using a light emitting element such as an organic EL (Electro Luminescence) or inorganic EL other than the liquid crystal panel.

  The gradation voltage generation circuit 110 is a circuit that generates and supplies a plurality of gradation voltages V1 to Vn to be supplied to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit (voltage generation circuit in a broad sense) 112 and a gradation amplifier unit 114.

  The ladder resistor circuit 112 includes a high potential side power source VGMH (first power source in a broad sense) for generating gradation voltages and a low potential side power source VGML (second power source in a broad sense) for generating gradation voltages. Between. The ladder resistor circuit 112 has a plurality of resistor circuits (variable resistors) R0 to Rn connected in series, and each of the voltage dividing nodes N1 to Nn divided by the plurality of resistor circuits R0 to Rn. The voltage is output as divided voltages VD1 to VDn.

  The gradation amplifier unit 114 performs impedance conversion on the divided voltages VD1 to VDn at the divided nodes N1 to Nn of the ladder resistor circuit 112 serving as a voltage generation circuit. In the present embodiment, the gradation amplifier unit 114 includes gradation voltage generation amplification circuits GAM1 to GAMn corresponding to the divided voltages VD1 to VDn input from the ladder resistor circuit 112, and the gradation voltage generation amplification circuit GAM1. ˜GAMn performs impedance conversion of the divided voltages VD1 to VDn. The plurality of divided voltages VD1 to VDn impedance-converted by the gradation voltage generation amplifiers GAM1 to GAMn are supplied as the plurality of gradation voltages V1 to Vn via the plurality of gradation voltage output lines VL1 to VLn. Is output.

  The data driver 50 is a circuit that supplies data signals (voltage, current) for driving the data lines SL1 to SLm (m is an integer of 2 or more) of an electro-optical panel 400 (electro-optical device) such as a liquid crystal panel. . Specifically, the data driver 50 determines a plurality of gradation voltages (for example, 256 levels) based on a plurality of gradation voltages (reference voltages) V1 to Vn and image data (gradation data, display data) GD. A voltage (data voltage) corresponding to the image data GD is selected from V1 to Vn and output to the data lines SL1 to SLm of the electro-optical panel 400. For example, in the case of the integrated circuit device 10 with a built-in memory, the image data GD is received from the display memory. On the other hand, in the case of the integrated circuit device 10 without a memory, the image data GD is supplied from the outside (for example, a display controller). Note that the number of gradations in this embodiment is arbitrary.

  The data driver 50 includes D / A conversion circuits 52-1 to 52-m and data line driving circuits 54-1 to 54-m. As shown in FIG. 18, one D / A conversion circuit and one data line driving circuit may be provided corresponding to each data line, and one D / A conversion circuit is provided with a plurality of data line driving circuits ( For example, the data line driving circuit for one or a plurality of pixels may be shared. Further, the data line driving circuit may drive a plurality of data lines in a time division manner. Further, part or all of the data driver 50 may be integrally formed on the electro-optical panel.

  At least one D / A conversion circuit 52-1 to 52-m is provided in the data driver 50, and a plurality of gradation voltages V1 to Vn supplied from the gradation voltage generation circuit 110 and image data GD (gradation data). ) Is input and the voltage after D / A conversion is output. In the present embodiment, for example, the image data GD is received, the gradation voltage corresponding to the image data GD is selected from the gradation voltages V1 to Vn, and the data line driving circuit 54 is selected as the selected gradation voltages VSL1 to VSLm. Output to -1 to 54-m.

  At least one data line driving circuit 54-1 to 54-m is provided in the data driver 50, and the selected gradation voltage VSL1 after D / A conversion supplied from the D / A conversion circuits 52-1 to 52-m is provided. Are converted into data voltages VS1 to VSm for driving the data lines SL1 to SLm of the electro-optical panel 400. In the present embodiment, the data line driving circuits 54-1 to 54-m include data driver amplification circuits DAM1 to DAMm, and these data driver amplification circuits DAM1 to DAMm are D / A conversion circuits 52-1 to 52-52. Impedance conversion of the selected gradation voltages VSL1 to VSLm from −m is performed. Then, the selected gradation voltages VSL1 to VSLm after impedance conversion are supplied to the data lines SL1 to SLm of the electro-optical panel 400 as the data voltages VS1 to VSm, thereby driving the data lines SL1 to SLm.

  In the present embodiment, the gradation voltage generation amplification circuits GAM1 to GAMn included in the gradation amplifier unit 114 of the gradation voltage generation circuit 110 and the data driver amplification included in the data line driving circuits 54-1 to 54-m. As the circuits DAM1 to DAMm, an amplifier circuit of a type that always outputs an output voltage (for example, an inverted voltage of the input voltage) corresponding to the input voltage can be used. For example, a method using a sample-and-hold type amplifier circuit as an amplifier circuit included in the gradation voltage generation circuit 110 or the data driver 50 can be considered. However, in this method, the output of the amplifier circuit is in a high impedance state during the sampling period. Therefore, timing control becomes complicated. On the other hand, in this embodiment, since the output of the amplifier circuit does not enter a high impedance state during the output period, timing control can be simplified. Further, by providing the amplifier circuit with an offset cancel function, variation in data voltage caused by variation in offset voltage can be reduced, and occurrence of display unevenness of the electro-optical panel 400 can be prevented.

  In the present embodiment, an output voltage corresponding to the input voltage is always output as the amplifier circuit included in the gradation amplifier unit 114 and the data line driving circuits 54-1 to 54-m of the gradation voltage generation circuit 110. For example, the amplifier circuit of this embodiment may be applied only to the gradation amplifier unit 114.

4). Electro-Optical Device FIG. 19 shows an outline of the configuration of the electro-optical device according to this embodiment. The electro-optical device 300 (liquid crystal device; display device in a broad sense) includes an electro-optical panel 400 (liquid crystal panel or LCD (Liquid Crystal Display) panel in a narrow sense), a data driver 50, a scan driver 70, a display controller 40, and a power supply circuit. 90 is included. Note that it is not necessary to include all these circuit blocks in the electro-optical device 300, and some of the circuit blocks may be omitted.

  Here, the electro-optical panel 400 (electro-optical device) includes a plurality of scanning lines, a plurality of data lines, and pixel electrodes specified by the scanning lines and the data lines. In this case, an active matrix liquid crystal device can be formed by connecting a thin film transistor TFT (Thin Film Transistor, switching element in a broad sense) to a data line and connecting a pixel electrode to the TFT.

  More specifically, the electro-optical panel 400 is a liquid crystal panel formed on an active matrix substrate (for example, a glass substrate). In the active matrix substrate, a plurality of scanning lines G1 to GM (M is a natural number of 2 or more) arranged in the Y direction and extending in the X direction and data lines S1 to S1 arranged in the X direction and extending in the Y direction, respectively. SN (N is a natural number of 2 or more) is arranged.

The display controller 40 has a central processing unit (not shown).
The data driver 50, the scan driver 70, and the power supply circuit 90 are controlled according to the contents set by a host such as a CPU. More specifically, the display controller 40 sets, for example, the operation mode and internally generated vertical synchronization signals and horizontal synchronization signals to the data driver 50 and the scan driver 70, and supplies the power supply circuit 90 with the power supply circuit 90. Thus, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 90 generates various voltage levels (gradation voltages) necessary for driving the electro-optical panel 400 and the voltage level of the counter electrode voltage VCOM of the counter electrode CE based on a reference voltage supplied from the outside. .

  In the electro-optical device 300 having such a configuration, the data driver 50, the scan driver 70, and the power supply circuit 90 cooperate with each other based on the gradation data supplied from the outside under the control of the display controller 40. Drive.

  In FIG. 19, one pixel is composed of 3 dots to display each RGB color component, and a data line is provided for each color component. However, one pixel is a dot of 2 dots, 4 dots or more. It may consist of numbers.

  In FIG. 19, the electro-optical device 300 includes the display controller 40, but the display controller 40 may be provided outside the electro-optical device 300. Alternatively, the host may be included in the electro-optical device 300 together with the display controller 40. Further, some or all of the data driver 50, the scan driver 70, the display controller 40, and the power supply circuit 90 may be formed on the electro-optical panel 400.

  In FIG. 19, the data driver 50, the scan driver 70, and the power supply circuit 90 may be integrated to constitute the integrated circuit device 10 as a semiconductor device (integrated circuit, IC).

5). Next, an electronic apparatus to which the above-described electro-optical device (an integrated circuit device, an amplifier circuit, a data driver, a power circuit, etc.) is applied will be described.

5.1. Projection Display Device As an electronic apparatus configured using the above electro-optical device, there is a projection display device. FIG. 20 is a block diagram illustrating a configuration example of a projection display device to which the electro-optical device according to the above-described embodiment is applied.

  The projection display device 700 includes a display information output source 710, a display information processing circuit 720, a display drive circuit 730 (display driver), a liquid crystal panel 740 (electro-optical panel in a broad sense), a clock generation circuit 750, and a power supply circuit 760. Consists of. The display information output source 710 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 720. The display information processing circuit 720 can include an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 730 includes a gate driver and a source driver, and drives the liquid crystal panel 740. The power supply circuit 760 supplies power to each circuit described above.

5.2. Cellular phone There is a cellular phone as an electronic apparatus configured using the above-described electro-optical device. FIG. 21 is a block diagram illustrating a configuration example of a mobile phone to which the electro-optical device according to the above-described embodiment is applied. In FIG. 21, the same parts as those in FIG. 19 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and supplies image data captured by the CCD camera to the display controller 40 in the YUV format.

  The mobile phone 900 includes an electro-optical panel 400. The electro-optical panel 400 is driven by the data driver 50 and the scan driver 70. The electro-optical panel 400 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels.

  The display controller 40 is connected to the data driver 50 and the scanning driver 70, and supplies RGB data gradation data to the data driver 50.

  The power supply circuit 90 is connected to the data driver 50 and the scan driver 70 and supplies a driving power supply voltage to each driver. The counter electrode voltage VCOM is supplied to the counter electrode of the electro-optical panel 400.

  The host 940 is connected to the display controller 40. The host 940 controls the display controller 40. Further, the host 940 can supply the gradation data received via the antenna 960 to the display controller 40 after demodulating by the modem 950. The display controller 40 causes the data driver 50 and the scan driver 70 to display on the electro-optical panel 400 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the electro-optical panel 400 based on operation information from the operation input unit 970.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

  For example, in the specification or the drawings, it is described at least once together with different terms having a broader meaning or the same meaning (first input terminal, second input terminal, analog reference power supply voltage, first power supply, second power supply, etc.). The terms (inverted input terminal, non-inverted input terminal, AGND, VSS, VDD, etc.) can be replaced with the different terms anywhere in the specification or the drawings. Further, the configurations and operations of the amplifier circuit, the reference voltage generation circuit, the integrated circuit device, the electro-optic storage, the electronic device, and the like are not limited to those described in this embodiment, and various modifications can be made. Furthermore, the present invention is not limited to the above-described driving of the liquid crystal electro-optical panel, but can also be applied to driving of electroluminescence and plasma display devices.

The basic structure of the amplifier circuit of this embodiment. 2A is a cross-sectional view of a first type capacitor included in the amplifier circuit, and FIG. 2B is a cross-sectional view of a second type capacitor included in the amplifier circuit. 1 is a first configuration example of an amplifier circuit according to an embodiment. 1 is a first configuration example of an amplifier circuit according to an embodiment. The signal waveform example for demonstrating operation | movement of an amplifier circuit. 6A is a principle configuration diagram of the amplifier circuit of the present embodiment, and FIGS. 6B and 6C are diagrams showing the relationship between the input voltage and the output voltage in the amplifier circuit of the present embodiment. . 2 shows a second configuration example of an amplifier circuit according to the present embodiment. 2 shows a second configuration example of an amplifier circuit according to the present embodiment. An example of the configuration of an operational amplifier. 10 is a layout example of a second configuration example of the amplifier circuit according to the present embodiment. Sectional drawing for demonstrating the layout example of a 2nd structural example of the amplifier circuit of this embodiment. The 3rd structural example of the amplifier circuit of this embodiment. The 3rd structural example of the amplifier circuit of this embodiment. FIG. 14A and FIG. 14B are layout arrangement examples of the third configuration example of the amplifier circuit of this embodiment. FIG. 15A and FIG. 15B are operation explanatory diagrams of a fourth configuration example of the amplifier circuit of the present embodiment. 4 shows a fourth configuration example of an amplifier circuit according to the present embodiment. 2 is a configuration example of a reference voltage generation circuit including an amplifier circuit according to the present embodiment. 1 is a configuration example of an integrated circuit device including an amplifier circuit according to the present embodiment. 1 is a diagram illustrating an outline of a configuration of an electro-optical device according to an embodiment. 1 is a block diagram of a configuration example of a projection display device to which an electro-optical device according to an embodiment is applied. 1 is a block diagram of a configuration example of a mobile phone to which an electro-optical device according to an embodiment is applied.

Explanation of symbols

SW1 to SW7, first to seventh switch elements, C1, C2, first and second capacitors,
CA charge storage capacitor, CAX auxiliary capacitor, CC phase compensation capacitor, CS sampling capacitor, NEG summing node, OP operational amplifier,
10 integrated circuit device, 40 display controller, 42 control circuit,
50 data drivers, 52 D / A conversion circuits, 54 data line drive circuits,
60 amplifier circuit, 70 scan driver, 90 power supply circuit, 110 gradation voltage generation circuit,
112 voltage generation circuit (ladder resistance circuit), 114 gradation amplifier section,
300 electro-optic device, 400 electro-optic panel,
700 Electronic equipment (projection display device), 900 Electronic equipment (mobile phone)

Claims (17)

An operational amplifier;
A charge storage capacitor provided between an input node and a first input terminal of the operational amplifier;
A phase compensation capacitor provided at an output terminal of the operational amplifier,
The charge storage capacitor is composed of a first type capacitor in which electrodes at both ends are formed of a metal layer or a polysilicon layer,
The phase compensation capacitor is constituted of a second type capacitor in which one electrode is a polysilicon layer and the other electrode is an impurity layer. In claim 1,
The phase compensation capacitor is:
An amplifier circuit arranged below the charge storage capacitor in a plan view. In claim 1 or 2,
A first switch element provided between an input node and a first node of the amplifier circuit;
A first capacitor provided between the first node and a summing node which is a node of a first input terminal of the operational amplifier;
A second switch element provided between the first node and an analog reference power supply;
A second capacitor provided between a second node and the summing node;
A third switch element provided between the second node and an output node of the amplifier circuit;
A fourth switch element provided between the second node and the analog reference power supply;
A fifth switch element provided between the output node and the summing node;
Including
The amplifier circuit according to claim 1, wherein the first capacitor and the second capacitor are the charge storage capacitors formed of the first type capacitors. In claim 3,
The phase compensation capacitor is:
An amplifier circuit arranged below the first capacitor and the second capacitor. In claim 3 or 4,
A first capacitor region in which the first capacitor is formed and a second capacitor region in which the second capacitor is formed are disposed along a first direction;
When the direction opposite to the first direction is the third direction, the first and second switch elements are disposed on the third direction side of the first and second capacitor regions,
The third and fourth switch elements are disposed on the first direction side of the first and second capacitor regions;
When the direction orthogonal to the first direction is the second direction, the summing node line that is the summing node line is the second of the first, second, third, and fourth switching elements. An amplifier circuit, characterized in that it is wired on the direction side. In claim 5,
A first analog reference power supply line for supplying a voltage of the analog reference power supply to the second switch element is provided in the third direction of the first and second capacitor regions along the second direction. Wired to the side,
A second analog reference power supply line for supplying a voltage of the analog reference power supply to the fourth switch element is in the first direction of the first and second capacitor regions along the second direction. An amplifier circuit characterized by being wired on the side. In any one of Claims 3 thru | or 6.
An auxiliary capacitor to which the summing node is electrically connected at one end;
The auxiliary capacitor is
An amplifier circuit comprising the second type capacitor, wherein one electrode is a polysilicon layer and the other electrode is an impurity layer. In claim 7,
The auxiliary capacitor is
An amplifier circuit arranged below the first capacitor and the second capacitor. In claim 1 or 2,
In the sampling period,
Accumulate charges according to the input voltage in the charge storage capacitor,
In the hold period,
An amplifier circuit that performs a flip-around operation of the charge storage capacitor and outputs a voltage corresponding to the stored charge. In claim 9,
A sampling switch element provided between the input node and the connection node;
A sampling capacitor provided between the connection node and a summing node which is a node of a first input terminal of the operational amplifier;
A feedback switch element provided between the output terminal of the operational amplifier and the summing node;
A flip-around switch element provided between the connection node and the output terminal of the operational amplifier;
The amplifier circuit according to claim 1, wherein the sampling capacitor is the charge storage capacitor including the first type capacitor. In claim 10,
An auxiliary capacitor to which the summing node is electrically connected at one end;
The auxiliary capacitor is
An amplifier circuit comprising the second type capacitor, wherein one electrode is a polysilicon layer and the other electrode is an impurity layer. An operational amplifier;
A charge storage capacitor provided between an input node and a first input terminal of the operational amplifier;
An auxiliary capacitor to which the summing node is electrically connected at one end thereof,
The charge storage capacitor is composed of a first type capacitor in which electrodes at both ends are formed of a polysilicon layer or a metal layer,
The auxiliary capacitor is composed of a second type capacitor in which one electrode is a polysilicon layer and the other electrode is an impurity layer. In claim 12,
The auxiliary capacitor is
An amplifier circuit disposed below the charge storage capacitor. A reference voltage generation circuit for generating a plurality of reference voltages,
A voltage generating circuit that voltage-divides the first power supply and the second power supply and outputs a plurality of divided voltages to a plurality of voltage dividing nodes;
An amplifier having the amplifier circuit according to any one of claims 1 to 13, wherein the amplifier circuit performs impedance conversion of the plurality of divided voltages from the voltage generation circuit and outputs the plurality of reference voltages;
A reference voltage generation circuit comprising: An integrated circuit device for driving an electro-optic panel,
A reference voltage generation circuit according to claim 14,
An integrated circuit including a data driver that receives a plurality of gradation voltages as the plurality of reference voltages from the reference voltage generation circuit and image data and drives a plurality of data lines of the electro-optical panel. Circuit device.   An electro-optical device comprising the integrated circuit device according to claim 15.   An electronic apparatus comprising the electro-optical device according to claim 16.

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