JP2010135891A - Noise testing system and noise testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To superimpose differential noise for test on a differential signal, with high accuracy. <P>SOLUTION: Noise generated by a noise generator 10 is distributed to a positive side delay circuit 31 and a negative side delay circuit 32 by a divider 20. Noises output by the positive side delay circuit 31 and the negative side delay circuit 32 are applied to respective signal lines, on the positive side and the negative side, constituting a differential transmission path via a coupling capacitor and a resistance. The resistance value of the resistor is set fully higher than a characteristic impedances of the respective signal lines on the positive side and on the negative side. Respective delay amounts of the positive side delay circuit 31 and the negative side delay circuit 32 are set so that they have delay differences from each other determined by a frequency of the noise generated by the noise generator 10 and amplitude of the differential noise to be applied to the differential transmission path through the respective resistances. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a noise test system and a noise test method for superimposing test noise on a differential signal from a transmitter to a receiver.

  In recent years, signal transmission speeds have been further increased in buses in various devices such as computers and communication interface circuits between devices. For example, PCI Express (PCI: Peripheral Components Interconnect), which is a kind of computer interface standard, realizes a transmission rate of several Gbps by performing serial communication using a differential transmission method. Recently, a circuit called SERDES (SERializer / DESerializer) that mutually converts both serial / parallel interfaces is used as an interface circuit. In this SERDES, high-speed signal transmission of 1 Gbps or more is often performed.

  When performing such high-speed transmission, it is inevitable that various noise components such as a switching power supply are mixed in the transmission signal. For this reason, it has become necessary to conduct a high-accuracy proof stress test against differential noise and common mode noise using a device that performs high-speed transmission.

  Here, as a conventional noise tolerance test method in a communication device, for example, a common mode choke coil is inserted on a signal line, and a coil with a midpoint tap of a transformer is interposed between this coil and the communication device under test via a capacitor. Was inserted, and an impedance element was connected to another coil wound around the same core as this coil, and a test voltage was applied to the midpoint of the midpoint tapped coil (for example, Patent Document 1).

In addition, as a conventional technique related to the above, a plurality of grounding means for reflecting an input signal are provided on a transmission line having a uniform characteristic impedance, and a reflected wave delayed according to the grounding position on the transmission line is detected. There has been a variable delay circuit configured as described above (see, for example, Patent Document 2).
Japanese Patent No. 2755584 JP-A-4-178002

  As described above, a high-accuracy noise tolerance test is required for devices that perform high-speed transmission. In particular, recently, a tolerance test against differential noise has been demanded, but no test apparatus capable of superimposing differential noise on a high-speed transmission signal with high accuracy has been considered. In addition, when a common mode choke coil is arranged in the transmission line as in the above-mentioned Patent Document 1, if a signal is transmitted at a high speed, the signal quality deteriorates, so that the noise tolerance test cannot be performed accurately. .

  The present invention has been made in view of such a point, and provides a noise test system and a noise test method capable of superimposing a test differential noise on a differential signal with high accuracy. Objective.

  In order to achieve the above object, a noise test system is provided that superimposes test noise on a differential signal from a transmitter to a receiver. In this noise test system, the first delay circuit and the second delay circuit in which the input signal is delayed for a predetermined time and at least one of the delay amounts is variable, and the noise generated from the noise generator are the same. A signal distributor that distributes to the first delay circuit and the second delay circuit with the same phase and amplitude, and a terminal opposite to the signal distributor of the first delay circuit and the second delay circuit A first coupling capacitor and a second coupling capacitor for AC coupling to a first signal transmission path and a second signal transmission path included in a differential transmission path through which the differential signal is transmitted, respectively , Having the same resistance value sufficiently higher than the characteristic impedance of the first signal transmission line and the second signal transmission line, and between the first coupling capacitor and the first signal transmission line, 2 results Having a first resistor and a second resistor connected in series between the capacitor and the second signal transmission path.

  Here, the noise generated from the noise generator and distributed to the first delay circuit by the signal distributor is input to the first resistor via the first coupling capacitor and attenuated by the first resistor. Applied to the first signal transmission path. Further, a part of the noise component input to the first resistor is reflected and input to the second delay circuit via the first delay circuit and the signal distributor. On the other hand, the noise generated from the noise generator and distributed to the second delay circuit by the signal distributor is input to the second resistor via the second coupling capacitor, attenuated by the second resistor, and then attenuated by the second resistor. 2 is applied to the signal transmission path. Further, a part of the noise component input to the second resistor is reflected and input to the first delay circuit via the second delay circuit and the signal distributor. With such a configuration, noise applied to the first signal transmission path and the second signal transmission path respectively includes noise components generated from the noise generator, the first delay circuit, and the second delay. The noise components reflected by the circuit are multiplexed, and differential noise is generated by these noise components. The amplitude of the differential noise applied to the differential transmission path is varied by varying the delay amounts of the first delay circuit and the second delay circuit.

  Moreover, in order to achieve the said objective, the noise test method in said noise test system is provided. In this noise test method, each delay amount of the first delay circuit and the second delay circuit is determined from the frequency of noise generated from the noise generator and the amplitude of differential noise superimposed on the differential signal. It is set so as to have a delay difference.

  In the above noise test system, differential noise can be superimposed with high accuracy on a high-speed differential signal of 1 Gbps or higher.

Hereinafter, embodiments will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a schematic configuration of a noise test system according to an embodiment.
The noise test system according to the present embodiment includes a noise generator 10, a divider 20, a positive delay circuit 31, a negative delay circuit 32, and a noise superimposing circuit 40. This noise test system is connected to an external transmitter 50 and a receiver 60, and superimposes differential noise for testing on a differential signal transmitted between them.

  The noise generator 10 generates noise that is a basis of differential noise superimposed on the differential signal transmitted from the transmitter 50 to the receiver 60. As this noise, for example, a sine wave or a rectangular wave of about several tens of MHz to several hundreds of MHz is generated.

The divider 20 distributes the noise generated from the noise generator 10 to the positive delay circuit 31 and the negative delay circuit 32 with the same phase and the same amplitude.
The positive-side delay circuit 31 and the negative-side delay circuit 32 each delay the input signal by a predetermined time. In this embodiment, both of these can change the delay amount, but only one of them may be variable in delay amount. As a configuration for making the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 variable, for example, a configuration in which a plurality of delay lines having different delay amounts are selectively connected may be employed.

  The noise superimposing circuit 40 is inserted into a signal transmission path from the transmitter 50 to the receiver 60, and applies noise input through the positive delay circuit 31 and the negative delay circuit 32 to the signal transmission path. A specific configuration example of the noise superimposing circuit 40 will be described later.

  Here, the transmitter 50 transmits the differential signal to the receiver 60 at a high speed such as 1 Gbps or higher. The transmitter 50 and the receiver 60 are devices capable of such high-speed communication such as SERDES, for example. The transmitter 50 and the receiver 60 may each be realized as a communication interface circuit that performs such high-speed communication, or may be realized as a host device such as a computer having the communication interface.

  Positive and negative signal lines 51 and 52 for transmitting differential signals are connected to the transmitter 50, and the signal lines 51 and 52 are connected to input terminals 41 and 42 of the noise superimposing circuit 40, respectively. Has been. The receiver 60 is connected to positive and negative signal lines 61 and 62 for receiving differential signals. The signal lines 61 and 62 are connected to the output terminals 43 and 62 of the noise superimposing circuit 40, respectively. 44 are connected to each other.

  The noise superimposing circuit 40 superimposes the noise input through the positive delay circuit 31 and the negative delay circuit 32 on the signals transmitted from the signal lines 51 and 52 to the signal lines 61 and 62, respectively. Here, by making the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 unbalanced, differential noise is superimposed on the differential signal transmitted from the transmitter 50 to the receiver 60. Thereby, for example, the receiver 60 can execute a tolerance test against differential noise.

FIG. 2 is a diagram illustrating a more detailed circuit configuration example of the noise test system.
The noise superimposing circuit 40 includes coupling capacitors C41 and C42, resistors R43 and R44, and signal lines 45 and 46.

  The signal line 45 connects the input terminal 41 and the output terminal 43, and the signal line 46 connects the input terminal 42 and the output terminal 44. Thus, the signal lines 45 and 46 constitute a part of the differential transmission path from the transmitter 50 to the receiver 60.

  The coupling capacitor C41 is provided for AC (Alternate Current) coupling of the signal line from the positive delay circuit 31 to the positive signal line 45. Similarly, the coupling capacitor C42 is provided to AC-couple the signal line from the negative-side delay circuit 32 to the negative-side signal line 46.

  The resistor R 43 has a resistance value sufficiently higher than the characteristic impedance of the positive signal line between the transmitter 50 and the receiver 60, that is, the signal lines 51, 45, 61, and the signal line via the positive delay circuit 31. Attenuates the noise applied to 45. The resistor R44 is sufficiently higher than the characteristic impedance of the negative signal line between the transmitter 50 and the receiver 60, that is, the signal lines 52, 46, and 62, and has the same resistance value as the resistor R43, and has a negative delay. Noise applied to the signal line 46 via the circuit 32 is attenuated.

  In addition, by making the resistance values of the resistors R43 and R44 sufficiently higher than the characteristic impedances of the signal lines on the positive side and the negative side, the configuration for noise superimposition including these resistors R43 and R44 can be realized as a differential transmission line. Disappears as a stub. In order to obtain such an effect more reliably, it is desirable to connect the ends of the resistors R43 and R44 and the signal lines 45 and 46 as close as possible. The resistance values of the resistors R43 and R44 are desirably set to be 20 times or more the characteristic impedance of the signal lines on the positive side and the negative side, for example.

  FIG. 2 also illustrates the circuit configuration of the divider 20. The divider 20 shown in FIG. 2 is configured as a so-called resistance distributor in which three distribution resistors R21 to R23 each having the same resistance value are connected in a ring shape. Noise from the noise generator 10 is supplied to a connection portion between the distribution resistor R21 and the distribution resistor R22. The noise is distributed from the other ends of the distribution resistors R21 and R22 to the positive delay circuit 31 and the negative delay circuit 32 with the same phase and the same amplitude.

  The noise superimposing circuit 40 includes, for example, coupling capacitors C41 and C42, resistors R43 and R44, signal lines 45 and 46, input terminals 41 and 42, and output terminals 43 and 44 on a base material such as a printed board. It is realized by arranging. Further, the positive delay circuit 31, the negative delay circuit 32, the divider 20, and the like may be integrally disposed on the base material.

  In the present embodiment, it is assumed that transmitter 50 and receiver 60 are provided as separate devices. However, for example, this noise test system may be configured to be used for a noise tolerance test of a SoC (System On a Chip) in which these functions are provided on the same semiconductor chip. In this case, it is good also as a structure which connects one end of resistance R43, R44 with a probe etc. with respect to the signal wire | line or connection terminal which connects the transmission part and receiving part on SoC.

  Here, as an example in the present embodiment, the characteristic impedance of each signal line on the positive side and the negative side of the signal transmission path between the transmitter 50 and the receiver 60 is 50Ω. The resistance values of the resistors R43 and R44 are both 1 kΩ, and the resistance values of the distribution resistors R21 to R23 provided in the divider 20 are 50 Ω, respectively. Note that the capacitances of the coupling capacitors C41 and C42 may be 0.22 μF, for example.

  In this case, the amplitude of noise applied to the signal line 45 through the positive delay circuit 31 is attenuated to about 1/20 by the resistor R43. Further, the remaining noise component having an amplitude of about 19/20 is input to the positive delay circuit 31 from the reverse direction as a reflection signal by the resistor R43 and delayed, and then input to the negative delay circuit 32 via the divider 20. Is done. Therefore, at least the noise component from the noise generator 10 and the noise component reflected from the positive side are multiplexed in the noise applied to the signal line 46 through the negative delay circuit 32.

  On the other hand, the amplitude of noise applied to the signal line 46 through the negative delay circuit 32 is attenuated to about 1/20 by the resistor R44. Further, the remaining noise component having an amplitude of about 19/20 is input to the negative delay circuit 32 from the reverse direction as a reflection signal by the resistor R44 and is delayed, and then to the positive delay circuit 31 via the divider 20. Entered. Therefore, at least the noise component from the noise generator 10 and the noise component reflected from the negative side are multiplexed in the noise applied to the signal line 45 through the positive delay circuit 31.

  In such a configuration, when the delay amounts of the positive-side delay circuit 31 and the negative-side delay circuit 32 are the same, both the positive-side and negative-side signal lines 45 and 46 have the same amplitude and phase. A noise component is applied. Therefore, in the differential transmission path from the transmitter 50 to the receiver 60, the superimposed noise components on the positive side and the negative side are canceled out and no differential noise component is generated.

  On the other hand, when there is a difference between the delay amount of the positive delay circuit 31 and the delay amount of the negative delay circuit 32, the noise components applied to the signal lines 45 and 46 are different. For this reason, a differential noise component that is a difference between these noise components is generated in the differential transmission path from the transmitter 50 to the receiver 60. At this time, the differential noise component can be superimposed on the transmission signal without affecting the digital signal transmitted from the transmitter 50 to the receiver 60 through the signal lines 45 and 46.

  Further, as will be described later, in accordance with the setting of the frequency of the noise generated from the noise generator 10 and the setting of each delay amount of the positive-side delay circuit 31 and the negative-side delay circuit 32, a differential with a desired amplitude is obtained. Noise can be superimposed on the transmission signal. That is, according to the noise test circuit described above, desired differential noise corresponding to the difference in delay amount between the positive delay circuit 31 and the negative delay circuit 32 is transmitted from the transmitter 50 to the receiver 60 at high speed. It is possible to accurately superimpose on a digital signal.

  In the description of the present embodiment, the delay amount expressed as “the delay amount of the positive delay circuit 31” includes the signal line from the positive delay circuit 31 to the divider 20 and the coupling capacitor C41 from the positive delay circuit 31. It is assumed that the delay amount by the signal line up to is also included. Similarly, the delay amount expressed as “the delay amount of the negative delay circuit 32” includes the delay amount due to the signal line from the negative delay circuit 32 to the divider 20 and the signal line from the negative delay circuit 32 to the coupling capacitor C42. Is also included.

  Next, an example of a signal waveform observed when noise is superimposed on a high-speed signal transmitted from the transmitter 50 to the receiver 60 using the above-described noise test system will be described. 3 to 12 below, a 3 Gbps signal is transmitted from the transmitter 50, and a 75 MHz sine wave is generated as noise from the noise generator 10.

First, a signal waveform example of each part in the apparatus when the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are the same is shown.
FIG. 3 is a diagram illustrating a waveform of noise output from each delay circuit when there is no delay difference between the positive side and the negative side.

  In FIG. 3, a waveform 101 is a noise waveform observed between the positive delay circuit 31 and the noise superimposing circuit 40. In this waveform 101, a noise component output from the positive delay circuit 31 to the noise superimposing circuit 40 and a reflected noise component reflected from the resistor R43 in the noise superimposing circuit 40 are multiplexed. A waveform 102 is a noise waveform observed between the negative delay circuit 32 and the noise superimposing circuit 40. In this waveform 102, the noise component output from the negative delay circuit 32 to the noise superimposing circuit 40 and the reflected noise component reflected from the resistor R44 in the noise superimposing circuit 40 are multiplexed. When the delay amounts of the positive side delay circuit 31 and the negative side delay circuit 32 are the same, as shown in FIG. 3, these waveforms 101 and 102 substantially coincide with each other in amplitude and phase.

FIG. 4 is a diagram showing waveforms appearing on the signal lines on the positive side and the negative side when there is no delay difference between the positive side and the negative side.
In FIG. 4, a waveform 111 indicates a signal waveform observed on the positive signal line 45. A waveform 112 shows a signal waveform observed on the signal line 46 on the negative side. Here, a pulse signal having a frequency higher than that of the noise generated from the noise generator 10 is output from the transmitter 50 to the signal line 45. Further, a signal having a phase opposite to that of the signal output to the positive signal line 45 is output from the transmitter 50 to the signal line 46. On the other hand, as shown in FIG. 3, the noises output from the positive delay circuit 31 and the negative delay circuit 32 have the same phase. Therefore, as shown in FIG. 4, the same common mode noise is applied to the signal lines 45 and 46 via the resistors R43 and R44, respectively, and is superimposed on the transmission signals on the positive side and the negative side, respectively. .

FIG. 5 is a diagram illustrating a waveform of a differential signal received by the receiving device when there is no delay difference between the positive side and the negative side.
When the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are the same, as shown in FIG. 4, the same common mode noise is superimposed on the transmission signals on the positive side and the negative side. . For this reason, in the waveform 121 of the differential signal based on each transmission signal, the superimposed noise is canceled and only the transmission signal component from the transmitter 50 appears.

  FIG. 6 is a diagram showing an eye pattern based on a differential signal when there is no delay difference between the positive side and the negative side. FIG. 7 is a diagram showing a waveform of jitter appearing in the differential signal when there is no delay difference between the positive side and the negative side.

  As described above, the superimposed noise component does not appear in the differential signal. Therefore, from this differential signal, an eye pattern with an open eye as shown in FIG. 6 is obtained, and it can be seen that the transmission signal can be accurately received by the receiver 60. Further, as shown in FIG. 7, only a very small jitter of about several ps is applied to the differential signal.

  Next, signal waveform examples of each part in the apparatus when the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are different are shown. Here, as an example, when the electrical length corresponding to the delay amount of the positive delay circuit 31 is 1000 mm, the electrical length corresponding to the delay amount of the negative delay circuit 32 is 2000 mm, and a difference of 1000 mm is given to the electrical length The signal waveform of is shown.

FIG. 8 is a diagram illustrating a waveform of noise output from each delay circuit when there is a delay difference between the positive side and the negative side.
In FIG. 8, a waveform 201 is a noise waveform observed between the positive delay circuit 31 and the noise superimposing circuit 40. A waveform 202 is a noise waveform observed between the negative delay circuit 32 and the noise superimposing circuit 40. As shown in FIG. 8, when the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are set to different values, noise waveforms having different amplitudes and phases are generated on the positive side and the negative side, respectively. The

FIG. 9 is a diagram illustrating waveforms appearing on the signal lines on the positive side and the negative side when there is a delay difference between the positive side and the negative side.
As in the case of FIG. 4, the transmitter 50 outputs a pulse signal having a frequency higher than the noise generated from the noise generator 10 to the signal line 45, and the positive side of the signal line 46 is positive. A signal having a phase opposite to that of the signal output to the signal line 45 is output. However, as shown in FIG. 8, noises having different waveforms are applied to the signal lines 45 and 46, respectively. For this reason, as shown in FIG. 9, the waveforms 211 and 212 appearing on the signal lines 45 and 46, respectively, have different shapes according to the waveform of the applied noise.

  According to FIG. 9, the shapes of the waveforms 211 and 212 are obtained by shifting the pulse shape of the original transmission signal by the amplitude of noise applied to the positive side and the negative side, respectively. Thus, it can be seen that noise is superimposed without particularly affecting the original transmission signal.

FIG. 10 is a diagram illustrating a waveform of a differential signal received by the receiving device when there is a delay difference between the positive side and the negative side.
As described above, different noises are applied to the signal lines 45 and 46, respectively. Therefore, these noises appear as differential noises in the differential signal waveform 221 without being canceled out. Here, when the waveform 221 in FIG. 10 is compared with the waveform 121 in FIG. 5, the waveform 221 has a waveform 121 that does not include differential noise, and the noise applied to the positive side and the negative side is synthesized. The shape is shifted by the amplitude of the sine wave. Thus, it can be seen that the sine wave noise is superimposed while the waveform of the original differential signal being transmitted is maintained.

  Further, as described above, by changing the difference between the delay amounts of the positive delay circuit 31 and the negative delay circuit 32, noises having different phases and amplitudes are applied to the positive and negative signal lines, respectively. be able to. Therefore, the phase and amplitude of the noise component included in the differential signal can be arbitrarily set according to the difference in delay amount between the positive delay circuit 31 and the negative delay circuit 32.

  As described above, according to the noise test circuit of the present embodiment, desired differential noise can be obtained without affecting the amplitude and phase of a high-speed differential transmission signal of 1 Gbps or more. Waveforms can be superimposed. Therefore, a tolerance test against differential noise can be performed with high accuracy on the receiving side that receives a high-speed transmission signal.

  FIG. 11 is a diagram showing an eye pattern based on a differential signal when there is a delay difference between the positive side and the negative side. According to FIG. 11, it can be seen that the eye opening is narrower than in the case of FIG. 6 because noise and jitter are superimposed on the differential signal.

  FIG. 12 is a diagram showing a waveform of jitter appearing in the differential signal when there is a delay difference between the positive side and the negative side. As can be seen from FIG. 12, periodic jitter due to sine wave noise is applied to the differential signal.

  The receiver 60 receives the transmission signal on which the noise and jitter are superimposed in this manner, thereby enabling a tolerance test against the noise and jitter. Further, by changing the difference between the delay amounts of the positive delay circuit 31 and the negative delay circuit 32, various noise and jitter components can be generated, and these can be superimposed on the transmission signal. For example, as shown in FIG. 12, high-resolution jitter of about 10 psec can be generated. Therefore, a highly accurate noise tolerance test using a broadband transmission signal and superimposed noise can be easily performed.

Next, the characteristics of the noise test system will be further described.
FIG. 13 is a diagram illustrating a configuration example of an equivalent circuit for characteristic verification. In FIG. 13, the same reference numerals are given to the components corresponding to FIG. 2.

  Here, using the equivalent circuit for characteristic verification shown in FIG. 13 based on the above-described noise test system, the frequency characteristic of the noise test system is verified. In the circuit shown in FIG. 13, instead of connecting the transmitter 50 and the receiver 60 as in the above-described noise test system, the transmission ends of the signal lines 45 and 46 on the positive side and the negative side are connected to resistors R45 and R46, respectively. Terminated by. The resistance values of these resistors R45 and R46 are set to 50Ω, respectively, so as to match the characteristic impedance of the signal transmission path between the transmitter 50 and the receiver 60.

  First, FIGS. 14 to 17 are graphs showing frequency characteristics based on the S parameter when the frequency of the sine wave noise generated by the noise generator 10 is changed. Here, as shown in FIG. 13, the input terminal corresponding to the position between the distribution resistor R21 and the distribution resistor R22 of the divider 20 is PORT1, and the reception ends of the signal lines on the positive side and the negative side are respectively PORT2 and PORT2. PORT3. Further, S21 indicating a transfer coefficient between PORT2 and PORT1 and S31 indicating a transfer coefficient between PORT3 and PORT1 are used as S parameters.

  FIG. 14 is a diagram showing the phase difference characteristics of S21 and S31 when there is no delay difference between the positive side and the negative side. FIG. 15 is a diagram showing the gain difference characteristics of S21 and S31 when there is no delay difference between the positive side and the negative side.

  14 and 15 show characteristics when the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are the same. Here, as an example, the electrical length (transmission line length) corresponding to each delay amount of the positive delay circuit 31 and the negative delay circuit 32 is 1000 mm. At this time, as shown in FIG. 14, no phase difference occurs between S21 and S31 regardless of the frequency of the noise generated from the noise generator 10. Further, as shown in FIG. 15, there is no gain difference between S21 and S31. As can be seen from these drawings, if the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are the same, no differential noise is applied to the differential transmission path.

  In the noise test system of the present embodiment, by setting the delay amounts of the positive side delay circuit 31 and the negative side delay circuit 32 to be the same as described above, the signal lines on the positive side and the negative side are set. It is also possible to perform a proof stress test when common mode noise is applied.

  FIG. 16 is a diagram showing the phase difference characteristics of S21 and S31 when there is a delay difference between the positive side and the negative side. FIG. 17 is a diagram illustrating the gain difference characteristics of S21 and S31 when there is a delay difference between the positive side and the negative side.

  16 and 17, the electrical length corresponding to the delay amount of the positive side delay circuit 31 is set to 1000 mm, while the electrical length corresponding to the delay amount of the negative side delay circuit 32 is set to 2000 mm. The characteristic when it is given is shown. At this time, as shown in FIG. 16, a phase difference is periodically generated between S21 and S31 according to the frequency of the noise generated from the noise generator 10. Further, as shown in FIG. 17, a gain difference is also periodically generated between S21 and S31 according to the frequency of the noise generated from the noise generator 10. According to these figures, when the delay amounts of the positive-side delay circuit 31 and the negative-side delay circuit 32 are different, the differential transmission path has a phase and amplitude corresponding to the frequency of noise generated from the noise generator 10. It can be seen that differential noise is applied.

  Next, characteristics of differential noise when the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 are changed will be described. FIG. 18 is a diagram illustrating the amplitude of the differential noise when the delay difference between the positive side and the negative side is changed. FIG. 19 is a diagram illustrating the jitter of the differential noise when the delay difference between the positive side and the negative side is changed.

  18 and 19, as an example, the electrical length corresponding to the delay amount of the positive delay circuit 31 is fixed to 1000 mm, and the electrical length corresponding to the delay amount of the negative delay circuit 32 is changed from 1000 mm to 3000 mm. The characteristic when it is made to show is shown. FIG. 18 shows the relative amplitude of the differential noise when the amplitude of the noise generated from the noise generator 10 is “1”.

  Under such conditions, as shown in FIG. 18, the amplitude of the differential noise is “0” when the difference in electrical length between the positive side and the negative side is 0 mm and 2000 mm, and is maximum when the difference is 1000 mm. . From this, it can be seen that the amplitude of the differential noise to be superimposed on the high-speed transmission signal on the differential transmission path can be arbitrarily determined based on the respective delay amounts on the positive side and the negative side.

  10 described above shows the waveform of the differential signal under the condition that the amplitude of the differential noise in FIG. 18 is maximized. According to FIG. 10, differential noise having an amplitude of less than 100 mV is obtained. Therefore, from FIG. 10 and FIG. 18, the amplitude of the differential noise can be set with a high resolution on the order of several mV based on the respective delay amounts on the positive side and the negative side.

  Further, as shown in FIG. 19, the jitter generated in the differential noise is also “0” when the difference between the electrical lengths of the positive side and the negative side is 0 mm and 2000 mm, and is maximum when the difference is 1000 mm. From this, it can be seen that the jitter of the differential noise superimposed on the high-speed transmission signal on the differential transmission path can be arbitrarily determined based on the delay amounts on the positive side and the negative side. Furthermore, the correlation coefficient between the amplitude and jitter of the differential noise corresponding to the difference in delay amount is 0.99 or more. Therefore, it can be seen that highly accurate jitter according to the amplitude of the differential noise can be applied to the differential transmission path.

  Note that FIG. 12 described above shows a jitter waveform under the condition that the amplitude of the differential noise is maximized in FIGS. 18 and 19. According to FIG. 12, it can be seen that a jitter of about 10 psec can be generated. Therefore, from FIG. 12, FIG. 18 and FIG. 19, jitter of the order of several psec can be generated based on the delay amounts on the positive side and the negative side.

  The receiver 60 receives a transmission signal on which noise and jitter set with high resolution are superimposed. This makes it possible to perform a high-accuracy proof test against noise and jitter.

  Here, the frequency of noise generated from the noise generator 10 is F, the wavelength of the noise is λ, the dielectric constant of the signal line is εr, the relative dielectric constant of the signal line is μr, and the speed of light at the vacuum dielectric constant is Co. And At this time, if μr = 1, the relationship of the following formula (1) is established.

As an example, when F = 75 [MHz], εr = 4, and Co = 3 × 10 ⁸ , (λ / 2) = 1 [m] is obtained from the equation (1). This indicates that when the difference in electrical length is 1 m, that is, the phase difference between the noise applied to the positive side and the negative side is 1 m (phase angle: π), the amplitude of the differential noise becomes maximum. Yes. Since the phase characteristic is repeated at 2π cycles, that is, every 2 m in terms of phase, the amplitude of differential noise becomes maximum when the difference in electrical length becomes 1 m, 3 m, 5 m,. Becomes “0” when becomes 0 m, 2 m, 4 m,.

  Further, when F = 150 [MHz] in the above equation (1), the wavelength is halved compared to the above case. For this reason, the amplitude of differential noise becomes maximum when the difference in electrical length is 0.5 m, 1.5 m, 2.5 m,..., And the difference in electrical length is 1 m, 2 m, 3 m,. Becomes "0".

  Thus, when changing the frequency of the noise generated by the noise generator 10, the amplitude of the differential noise superimposed on the transmission signal can be easily calculated by calculating the difference in electrical length from the wavelength. Is possible. As shown in FIGS. 18 and 19, since the amplitude of the differential noise and the generated jitter have a high correlation, the amount of jitter generated according to the change of the noise frequency can be calculated. is there. Therefore, a differential noise having an arbitrary amplitude and jitter is generated by combining the frequency of the noise generated by the noise generator 10 and each delay amount of the positive delay circuit 31 and the negative delay circuit 32 to generate a differential. It can be applied to the transmission line.

  Also, such parameter combinations can be prepared in advance as table information, for example. The user who conducts the test refers to this table information to set the circuit parameters for the noise test system and the noise so that the differential noise having the desired amplitude and jitter is applied to the differential transmission line. It is possible to set the operation of the generator 10.

  As shown in FIGS. 8 to 10, the differential noise is generated based on noise generated by multiplexing the original noise component and the reflected noise component on the positive side and the negative side, respectively. For this reason, the amplitude of the differential noise also changes depending on the resistance values of the resistors R43 and R44. Therefore, in order to generate differential noise having a desired amplitude and jitter, the frequency of the noise generated from the noise generator 10, the delay amounts of the positive delay circuit 31 and the negative delay circuit 32, and the resistor R43 , R44 resistance values may be set.

Next, a modified example of the above-described noise test system and an example of a noise tolerance test procedure using this apparatus will be described.
FIG. 20 is a diagram illustrating a configuration example of a noise test system having a noise test control function. In FIG. 20, the components corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals.

  In the noise test system shown in FIG. 20, the divider 20, the positive delay circuit 31, the negative delay circuit 32, and the noise superimposing circuit 40a obtained by modifying the noise superimposing circuit 40 in the configuration shown in FIGS. The noise test apparatus 300 is provided on the same base material. The noise superimposing circuit 40a is provided with variable resistors R43a and R44a instead of the resistors R43 and R44 provided in the noise superimposing circuit 40 shown in FIG. The variable resistors R43a and R44a can change their resistance values within a sufficiently large range as compared with the characteristic impedance of the signal transmission path from the transmitter 50 to the receiver 60. Note that the variable resistors R43a and R44a may be configured to selectively connect a plurality of resistors having different resistance values, for example.

  The noise test system of FIG. 20 further includes a test control device 400 that can control the entire test using the noise test device 300. The test control apparatus 400 includes an input unit 410, a noise setting unit 420, a signal transmission / reception control unit 430, and a storage unit 440.

  For example, an input device such as a keyboard and a mouse is connected to the input unit 410. The input unit 410 outputs signals corresponding to user input operations to these input devices to the noise setting unit 420 and the signal transmission / reception control unit 430.

  The noise setting unit 420 sets noise to be applied to the signal transmission path from the transmitter 50 to the receiver 60 according to the signal from the input unit 410. Specifically, the frequency and amplitude of noise generated from the noise generator 10, the delay amount in the positive delay circuit 31 and the negative delay circuit 32, the resistance value in the variable resistors R43a and R44a, and the like are set. The noise setting unit 420 performs such a setting operation while referring to the noise setting table 441 stored in the storage unit 440.

  The signal transmission / reception control unit 430 generates a transmission signal from the transmitter 50, supplies the transmission signal to the transmitter 50, and causes the receiver 60 to transmit the transmission signal. In addition, the reception state of the transmission signal at the receiver 60 is detected, and information on the test result such as the reception result is described as the test result information 442 and recorded in the storage unit 440.

  The storage unit 440 is configured by a nonvolatile recording medium such as an HDD (Hard Disk Drive). In the present embodiment, the noise setting table 441 and the test result information 442 are stored in the storage unit 440.

  In the noise setting table 441, a combination of the frequency of noise generated from the noise generator 10, the delay amounts of the positive delay circuit 31 and the negative delay circuit 32, and the resistance values of the variable resistors R43a and R44a, In the noise superimposing circuit 40a, the noise is applied in advance in association with the amplitude and jitter of the noise applied to the differential transmission path.

  In the test result information 442, for example, whether or not the receiver 60 can receive a signal with respect to the specification of the transmission signal from the transmitter 50 to the receiver 60 and the specification of the differential noise superimposed on the transmission signal. Associated and held.

  Note that such a test control apparatus 400 is realized by, for example, a computer apparatus. In this case, the functions of the noise setting unit 420 and the signal transmission / reception control unit 430 are realized, for example, by executing a processing program stored in the storage unit 440 by a CPU (Central Processing Unit).

FIG. 21 is a flowchart illustrating an example of a control procedure of a noise tolerance test performed by the test control device.
[Step S11] The frequency of noise to be generated by the noise generator 10 is designated by the user through the input unit 410. The noise setting unit 420 sets the noise generator 10 so as to generate noise having a designated frequency.

  [Step S12] The amplitude or jitter of noise applied to the differential transmission path is designated by the user through the input unit 410. The noise setting unit 420 refers to the noise setting table 441, and each delay of the positive delay circuit 31 and the negative delay circuit 32 corresponding to the specified noise amplitude and the noise frequency specified in step S11. The amount and each resistance value of the variable resistors R43a and R44a are read. Based on the read value, the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 and the resistance values of the variable resistors R43a and R44a are set.

  Note that the resistance values of the variable resistors R43a and R44a are always set to the same value. Further, depending on the user's designation from the input unit 410, one of the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 or the resistance values of the variable resistors R43a and R44a is fixed and only the other is changed. You may do it.

  [Step S13] The specification of the transmission signal is specified by the user through the input unit 410, and the start of the test is requested. The signal transmission / reception control unit 430 generates a transmission signal having a specified specification, supplies the transmission signal to the transmitter 50, and starts transmission to the receiver 60. At the same time, the noise setting unit 420 causes the noise generator 10 to generate noise having the specification set in step S11.

  Thereby, the transmission signal is transmitted to the differential transmission path from the transmitter 50 to the receiver 60, and the differential noise having the amplitude or jitter specified by the user is superimposed on the transmission signal. For example, the receiver 60 notifies the signal transmission / reception control unit 430 whether or not the transmission signal has been correctly received.

[Step S14] The signal transmission / reception control unit 430 receives the information notified from the receiver 60, converts the information into a predetermined format, and records the information in the test result information 442.
[Step S15] The noise setting unit 420 determines whether or not a change in the amplitude or jitter of the differential noise applied to the differential transmission path is requested by the user through the input unit 410. If no change in amplitude or jitter is requested, the process of step S16 is executed. On the other hand, when a change in amplitude or jitter is requested, the process of step S12 is executed again. At this time, in step S12, a parameter corresponding to the newly requested amplitude of the differential noise is read from the noise setting table 441 into the noise setting unit 420. Then, the noise test apparatus 300 is set based on the parameters.

  [Step S16] The noise setting unit 420 determines whether or not a change in the frequency of noise generated by the noise generator 10 is requested by the user through the input unit 410. If the change of the noise frequency is not requested, the process of step S17 is executed. On the other hand, when the change of the noise frequency is requested, the process of step S11 is executed again. At this time, the noise setting unit 420 requests the noise generator 10 to generate a newly requested noise frequency.

  [Step S17] The noise setting unit 420 determines whether or not the end of the test is requested by the user through the input unit 410. If the end of the test is not requested, the determination process in step S15 is executed again. On the other hand, when the end of the test is requested, the control process for each unit is ended.

  In the above processing, for example, when variable widths of the amplitude or jitter of differential noise and the frequency of noise from the noise generator 10 are input in advance by the user, within the range of the variable width, for example. Test control may be automatically executed while changing each parameter. In this case, in steps S15 to S17, the determination process may be automatically performed based on whether or not the parameter setting with the specified variable width is completed.

  In the above processing, the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 and the resistance values of the variable resistors R43a and R44a are changed with the frequency of the noise generated by the noise generator 10 fixed. As a result, the amplitude or jitter of the differential noise is changed. However, on the contrary, the frequency of noise generated by the noise generator 10 is changed in a state where the delay amounts of the positive delay circuit 31 and the negative delay circuit 32 and the resistance values of the variable resistors R43a and R44a are fixed. Thus, the amplitude or jitter of the differential noise may be changed.

Needless to say, some or all of the above test procedures can be executed by a user's manual operation.
In FIG. 20, the divider 20, the positive delay circuit 31, the negative delay circuit 32, and the noise superimposing circuit 40 a are integrally provided in the noise test apparatus 300, but at least a part of them is a separate apparatus. It may be configured. Alternatively, the noise generator 10 and the test control device 400 may be integrated with the noise test device 300.

Regarding the above embodiment, the following additional notes are disclosed.
(Supplementary note 1) In a noise test system in which test noise is superimposed on a differential signal from a transmitter to a receiver,
A first delay circuit and a second delay circuit, each of which delays an input signal by a predetermined time and at least one of the delay amounts is variable;
A signal distributor that distributes the noise generated from the noise generator to the first delay circuit and the second delay circuit with the same phase and the same amplitude;
A first signal transmission line and a second signal transmission line each having a terminal opposite to the signal distributor of the first delay circuit and the second delay circuit in a differential transmission line through which the differential signal is transmitted; A first coupling capacitor and a second coupling capacitor for AC coupling to the signal transmission path, respectively;
Having the same resistance value sufficiently higher than the characteristic impedance of the first signal transmission path and the second signal transmission path, and between the first coupling capacitor and the first signal transmission path, A first resistor and a second resistor connected in series between the coupling capacitor and the second signal transmission line, respectively,
A noise test system comprising:

  (Supplementary Note 2) Between the signal delay amount by the first delay circuit and the signal delay amount by the second delay circuit, the frequency of noise generated from the noise generator, the first resistor, and The noise test system according to claim 1, wherein a delay difference determined based on an amplitude of differential noise applied to the differential transmission path through the second resistor is set.

  (Additional remark 3) Each resistance value of the said 1st resistance and the said 2nd resistance is made variable in the range sufficiently higher than the characteristic impedance of the said 1st signal transmission path and the said 2nd signal transmission path, respectively. The noise test system according to appendix 1 or 2, wherein

(Additional remark 4) The information input part which receives the input information for designating the amplitude of the differential noise applied to the said differential transmission line,
Different delays for the first delay circuit and the second delay circuit based on the amplitude of the differential noise specified through the information input unit and the frequency of the noise generated from the noise generator A delay amount setting unit for setting the amount;
The noise test system according to appendix 1 or 2, further comprising:

  (Supplementary Note 5) The delay amount setting unit includes an amplitude of differential noise applied to the differential transmission line, a frequency of noise generated from the noise generator, the first delay circuit, and the second delay circuit. The noise test system according to appendix 4, wherein each delay amount of the first delay circuit and the second delay circuit is set with reference to a setting table in which each delay amount of the delay circuit is associated with each other. .

(Appendix 6) In a noise test method in which test noise is superimposed on a differential signal from a transmitter to a receiver,
Each delay amount of the first delay circuit and the second delay circuit to which the noise generated from the noise generator and distributed with the same phase and the same amplitude by the signal distributor is input is generated from the noise generator. Set to have a delay difference determined based on the frequency of the noise and the amplitude of the differential noise superimposed on the differential signal,
The differential signal is transmitted to a differential transmission path between the transmitter and the receiver, and noise is generated from the noise generator, with respect to the first signal transmission path included in the differential transmission path The noise output from the terminal opposite to the signal distributor of the first delay circuit has a resistance value sufficiently higher than the characteristic impedance of the first coupling capacitor and the first signal transmission line. And is output from a terminal on the opposite side of the signal distributor of the second delay circuit with respect to the second signal transmission path provided in the differential transmission path. Applying noise through a second coupling capacitor and a second resistor having the same resistance value as the first resistor,
A noise test method characterized by the above.

  (Additional remark 7) Each resistance value of the said 1st resistance and the said 2nd resistance is made variable in the range sufficiently higher than the characteristic impedance of the said 1st signal transmission path and the said 2nd signal transmission path, respectively. In this case, the respective delay amounts of the first delay circuit and the second delay circuit, and the resistance values of the first resistor and the second resistor are noise frequencies generated from the noise generator. The noise test method according to claim 6, wherein the noise test method is set based on the differential noise amplitude superimposed on the differential signal.

  (Supplementary Note 8) The delay amounts of the first delay circuit and the second delay circuit include the amplitude of differential noise applied to the differential transmission path, and the frequency of noise generated from the noise generator. The noise test method according to claim 6, wherein the noise test method is set based on a setting table in which the delay amounts of the first delay circuit and the second delay circuit are associated with each other.

It is a figure which shows schematic structure of the noise test system which concerns on embodiment. It is a figure which shows the further detailed circuit structural example of a noise test system. It is a figure which shows the waveform of the noise output from each delay circuit when there is no delay difference of a positive side and a negative side. It is a figure which shows the waveform which appears on each signal line of a positive side and a negative side, when there is no delay difference of a positive side and a negative side. It is a figure which shows the waveform of the differential signal received with a receiver, when there is no delay difference of a positive side and a negative side. It is a figure which shows the eye pattern based on a differential signal in case there is no delay difference of a positive side and a negative side. It is a figure which shows the waveform of the jitter which appears in a differential signal when there is no delay difference of a positive side and a negative side. It is a figure which shows the waveform of the noise output from each delay circuit when there exists a delay difference of a positive side and a negative side. It is a figure which shows the waveform which appears on each signal line of a positive side and a negative side, when there exists a delay difference of a positive side and a negative side. It is a figure which shows the waveform of the differential signal received with a receiver when there exists a delay difference of a positive side and a negative side. It is a figure which shows the eye pattern based on a differential signal in case there exists a delay difference of a positive side and a negative side. It is a figure which shows the waveform of the jitter which appears in a differential signal when there exists a delay difference of a positive side and a negative side. It is a figure which shows the structural example of the equivalent circuit for characteristic verification. It is a figure which shows the phase difference characteristic of S21, S31 when there is no delay difference of a positive side and a negative side. It is a figure which shows the gain difference characteristic of S21, S31 when there is no delay difference of a positive side and a negative side. It is a figure which shows the phase difference characteristic of S21, S31 when there exists a delay difference of a positive side and a negative side. It is a figure which shows the gain difference characteristic of S21, S31 when there exists a delay difference of a positive side and a negative side. It is a figure which shows the amplitude of differential noise when the delay difference of positive side and negative side is changed. It is a figure which shows the jitter of differential noise when changing the delay difference of a positive side and a negative side. It is a figure which shows the structural example of the noise test system provided with the control function of the noise test. It is a flowchart which shows the example of the control procedure of the noise tolerance test by a test control apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Noise generator 20 Divider 31 Positive side delay circuit 32 Negative side delay circuit 40 Noise superimposition circuit 41,42 Input terminal 43,44 Output terminal 45,46,51,52,61,62 Signal line 50 Transmitter 60 Receiver C41 , C42 Coupling capacitor R21 to R23 Distribution resistance R43, R44 Resistance

Claims (6)

In a noise test system that superimposes test noise on the differential signal from the transmitter to the receiver,
A first delay circuit and a second delay circuit, each of which delays an input signal by a predetermined time and at least one of the delay amounts is variable;
A signal distributor that distributes the noise generated from the noise generator to the first delay circuit and the second delay circuit with the same phase and the same amplitude;
A first signal transmission line and a second signal transmission line each having a terminal opposite to the signal distributor of the first delay circuit and the second delay circuit in a differential transmission line through which the differential signal is transmitted; A first coupling capacitor and a second coupling capacitor for AC coupling to the signal transmission path, respectively;
Having the same resistance value sufficiently higher than the characteristic impedance of the first signal transmission path and the second signal transmission path, and between the first coupling capacitor and the first signal transmission path, A first resistor and a second resistor connected in series between the coupling capacitor and the second signal transmission line, respectively,
A noise test system comprising:   Between the signal delay amount by the first delay circuit and the signal delay amount by the second delay circuit, the frequency of noise generated from the noise generator, the first resistor, and the second resistor 2. The noise test system according to claim 1, wherein a delay difference determined based on an amplitude of differential noise applied to the differential transmission path through a resistor is set.   The resistance values of the first resistor and the second resistor are variable in a range sufficiently higher than the characteristic impedance of the first signal transmission line and the second signal transmission line, respectively. The noise test system according to claim 1 or 2. An information input unit for receiving input information for designating an amplitude of differential noise applied to the differential transmission path;
Different delays for the first delay circuit and the second delay circuit based on the amplitude of the differential noise specified through the information input unit and the frequency of the noise generated from the noise generator A delay amount setting unit for setting the amount;
The noise test system according to claim 1, further comprising:   The delay amount setting unit includes an amplitude of differential noise applied to the differential transmission path, a frequency of noise generated from the noise generator, and each of the first delay circuit and the second delay circuit. The noise test system according to claim 4, wherein each delay amount of the first delay circuit and the second delay circuit is set with reference to a setting table in which a delay amount is associated. In the noise test method for superimposing test noise on the differential signal from the transmitter to the receiver,
Each delay amount of the first delay circuit and the second delay circuit to which the noise generated from the noise generator and distributed with the same phase and the same amplitude by the signal distributor is input is generated from the noise generator. Set to have a delay difference determined based on the frequency of the noise and the amplitude of the differential noise superimposed on the differential signal,
The differential signal is transmitted to a differential transmission path between the transmitter and the receiver, and noise is generated from the noise generator, with respect to the first signal transmission path included in the differential transmission path The noise output from the terminal opposite to the signal distributor of the first delay circuit has a resistance value sufficiently higher than the characteristic impedance of the first coupling capacitor and the first signal transmission line. And is output from a terminal on the opposite side of the signal distributor of the second delay circuit with respect to the second signal transmission path provided in the differential transmission path. Applying noise through a second coupling capacitor and a second resistor having the same resistance value as the first resistor,
A noise test method characterized by the above.

Images