JP2010135626A - Overvoltage protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small overvoltage protection element. <P>SOLUTION: The overvoltage protection element is provided with: an electrode 3 having an ohmic contact in a sub-collector region 13; an anode region 4 formed on the sub-collector region 13 and having second conductivity reverse to first conductivity; an anode electrode 18 having an ohmic contact on the anode region 4; a base mesa region 5 formed separately from the anode region 4 and having the second conductivity; an emitter mesa region 7 formed on the base mesa region 5 and having the first conductivity; an emitter mesa region 8 formed separately from the emitter mesa region 7 and having the first conductivity; an emitter electrode 10 having an ohmic contact on the emitter mesa region 8; an emitter electrode 9 having an ohmic contact on the emitter mesa region 7; a wiring 16 for connecting the electrode 3 to the emitter electrode 10; and a wiring 17 for connecting the anode electrode 18 to the emitter electrode. The wiring 16 and the wiring 17 are used as output terminals. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an overvoltage protection element.

  In a bipolar transistor fabricated by epitaxial growth on a conventional GaAs (gallium arsenide) substrate or a heterojunction bipolar transistor, an overvoltage protection element having a protection effect against a positive overvoltage and a reverse overvoltage is manufactured. In addition, a circuit including a plurality of elements has been configured.

  Conventionally, a plurality of transistors separated by an element isolation structure in which the conductive layer closest to the substrate has a mesa structure (a plateau structure) or an element isolation structure in which a non-conductive region is formed using ion implantation Alternatively, a plurality of diodes are manufactured, and an overvoltage protection circuit is configured by these elements. For this reason, the circuit occupation area has become large.

  In order to fabricate the mesa structure and the non-conductive region by ion implantation, it is necessary to provide a constant interval between elements. In addition, in the case of an overvoltage protection circuit, it is originally assumed that a high voltage is applied. Therefore, when the interval between elements is narrow, the operation assumed by the overvoltage protection circuit is caused by a leakage current (leakage current). May not. For this reason, the spacing between the elements is designed with a further margin.

  FIG. 10 is a circuit diagram of a conventional overvoltage protection circuit. FIG. 2. In the circuit of FIG. 10, three elements are used.

  FIG. 11 is a plan view of another conventional overvoltage protection circuit 700. FIG. 7. In the overvoltage protection circuit 700, the transistor 250 and the transistor 270 of the circuit of FIG. 10 are manufactured as elements indicated by reference numeral 701 in a common collector layer region, thereby achieving miniaturization. However, a transistor (an element indicated by reference numeral 702) corresponding to the transistor 290 is formed in another region 702. An element isolation structure is provided by providing an interval L between the element denoted by reference numeral 701 and the element denoted by reference numeral 702.

  Consider a case where an overvoltage pulse due to static electricity is applied to the circuit of FIG. 10 with the terminal 210 on the signal side (positive voltage side) and the terminal 212 on the negative voltage side.

  In this case, the voltage at which leakage between the base and the emitter of the transistor 270 to which the reverse voltage is applied is, for example, 10.7 V (volts). This value is determined by the sum of the reverse breakdown voltage of the base-emitter junction of the GaAs heterojunction bipolar transistor assumed as the transistor 270 and the base-emitter voltage of 1.2 V when the collector current of the transistor 250 is conducted. Is done.

  A current flows from the emitter terminal of the transistor 270 to the base terminal of the transistor 270 at a voltage higher than the voltage at which leakage starts. Thus, a current is supplied to the base of the transistor 250 and a current flows from the collector terminal 253 of the transistor 250 to the emitter terminal 259 of the transistor 250. Therefore, an overvoltage higher than the voltage at which the leakage starts is not applied, and overvoltage protection is performed.

  In the circuit of FIG. 10, when the terminal 212 is on the positive voltage side, the terminal 210 is on the negative voltage side, and an overvoltage pulse due to static electricity is applied, current flows from the base of the transistor 290 to the emitter of the transistor 290, and Current flows from the transistor to the collector of the transistor 250. That is, current is passed through the forward bias path of the PN junction to perform overvoltage protection.

  FIG. 12 shows that the maximum value Vin_max gradually increases as shown by a solid line from a signal source having an input impedance of 50Ω to a circuit in which input and output are matched to 50Ω, that is, a load circuit having a load impedance of 50Ω. It is the graph which showed the simulation result of the circuit which inputs the input voltage signal Vin. In addition, a simulation result of the output voltage signal Vout generated at the terminal 210 when the circuit of FIG. 10 is connected in parallel with the load circuit so that the terminal 210 is on the positive voltage side is indicated by a broken line. A terminal 212 in FIG. 10 is connected to the ground wiring side that is a negative voltage with respect to the signal wiring of the circuit. The frequency of the input voltage signal Vin and the voltage signal Vout was 2.5 GHz.

  13 shows the maximum value Vin_max of the input voltage signal (solid line in FIG. 12) Vin on the horizontal axis and the maximum value Vout_max of the voltage signal (broken line in FIG. 12) Vout generated at the terminal 210 on the left vertical axis (vertical axis Y1). ) Is a graph showing the ratio R of the maximum value Vout_max of the voltage signal generated at the terminal 210 to the maximum value Vin_max of the input voltage signal on the right vertical axis (vertical axis Y2).

  Also, on the negative side of the horizontal axis, a simulation result in the case of inputting a signal in which the polarity of Vin in FIG. 22 is reversed in the same connection as described above, that is, an input voltage signal Vin that gradually decreases the minimum value Vin_min is input. Indicated. In this case, the horizontal axis of the graph is changed to the maximum value Vin_max to be the minimum value Vin_min, and similarly, the maximum value Vout_max of the vertical axis of the graph is entered in the graph as the minimum value Vout_min. In this case, R is calculated as a ratio of the minimum value Vout_min to the minimum value Vin_min.

  In the graph of FIG. 13, when Vin_max is 10.7 V or more assumed as above, the signal waveform is distorted as a result of overvoltage protection, and Vin_max ≠ Vout_max and R ≠ 1 cannot be avoided. However, it is important that the loss is as small as possible for a signal below the voltage at which the overvoltage protection works, and it is important that the loss does not change with respect to the signal strength, that is, the linearity is good. .

  In the graph of FIG. 13, although it is a little lower than the above 10.7V, until Vin_max is about 8V, the waveform of the output signal shows a good characteristic with almost no distortion, and a voltage higher than that is input. The signal waveform has begun to be distorted due to the overvoltage prevention action.

  The circuit connecting the above circuit and the circuit of FIG. 10 does not assume that a voltage is applied in the reverse direction in normal circuit operation, and the maximum value is the forward direction between the base and emitter of the transistor 290. When a voltage signal equal to or greater than the sum of the breakdown voltage and the forward breakdown voltage between the base collector of the transistor 250 is input in the opposite direction to the above description, overvoltage protection is activated and the waveform of the output signal is distorted. When the transistors 290 and 270 are GaAs heterojunction bipolar transistors, the sum of the forward withstand voltages is approximately 1.2 + 1.2 = 2.4V.

  Further, Patent Document 2 discloses an overvoltage protection structure having a different configuration. The overvoltage protection circuit 700 forms semiconductor layers in order by epitaxial growth, arranges semiconductors having necessary conductivity and concentration composition in layers, and separates the semiconductor layers by mesa structure or ion implantation In contrast to the overvoltage protection structure formed by the method, the above Patent Document 2 targets the overvoltage protection structure formed by the manufacturing method in the process of adjusting and controlling the conductivity of the semiconductor by ion implantation.

  Further, Patent Document 3 discloses a similar protection structure against overvoltage in the case of being constituted by MOS transistors instead of bipolar transistors.

  In patent document 1 and patent document 2, since the structure restrictions resulting from the manufacturing method are different, the configurations disclosed in each other cannot be used, so it is not an advantage, both of which are the respective manufactures. It goes without saying that it has become an important technique in the method.

Further, in Patent Document 3, since it is based on an element having a MOS structure different from that of the bipolar transistor, it cannot be completely shared with Patent Documents 1 and 2.
US Patent No. 7,071,514 (Patent July 4, 2006) JP 62-181457 (released August 8, 1987) US Patent No. 5,946,177 (Patent on August 31, 1999)

  As described above, the conventional overvoltage protection circuit 700 is separated by an element isolation structure by making the semiconductor conductive layer a mesa structure (plateau structure) or by an element isolation structure by making a non-conductive region using ion implantation. A plurality of transistors or a plurality of diodes were manufactured, and an overvoltage protection circuit was constituted by these elements. For this reason, the circuit occupation area has become large.

  The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a small overvoltage protection element.

  Still another object of the present invention is to provide a small overvoltage protection element in which the waveform of an output signal is more difficult to distort.

  In order to solve the above problems, an overvoltage protection element of the present invention is formed on a first conductive first semiconductor layer, and has a first electrode having an ohmic contact with the first semiconductor layer, and the first semiconductor layer. A second semiconductor layer having a second conductivity that is opposite to the first conductivity, and an ohmic contact formed on the second semiconductor layer. A second electrode having a second semiconductor layer, separated from the second semiconductor layer, formed on the first semiconductor layer, formed on the third semiconductor layer, and formed on the third semiconductor layer; A fourth semiconductor layer having first conductivity, a fifth semiconductor layer having the first conductivity, separated from the fourth semiconductor layer and formed on the third semiconductor layer, and the fifth semiconductor layer An ohmic capacitor is formed on the fifth semiconductor layer. A fourth electrode formed on the fourth semiconductor layer and having an ohmic contact with the fourth semiconductor layer; a first wiring connecting the first electrode and the third electrode; And an overvoltage protection element including a second wiring connecting the second electrode and the fourth electrode, wherein the first wiring and the second wiring are output terminals.

  Furthermore, in order to solve the above-described problem, an overvoltage protection element of the present invention is formed on a first conductive first semiconductor layer, and has a first electrode having an ohmic contact with the first semiconductor layer, and the first electrode A second semiconductor layer formed on the semiconductor layer and having a second conductivity opposite to the first conductivity; and formed on the second semiconductor layer and ohmic on the second semiconductor layer. A second electrode having a contact, separated from the second semiconductor layer, formed on the first semiconductor layer, formed on the third semiconductor layer, and a third semiconductor layer having the second conductivity. A fourth semiconductor layer having the first conductivity, a fifth semiconductor layer having the first conductivity, separated from the fourth semiconductor layer and formed on the third semiconductor layer, and the fifth semiconductor layer. An ohmic layer is formed on the semiconductor layer and is formed on the fifth semiconductor layer. A third electrode having a contact, and a fourth electrode formed on the fourth semiconductor layer and having an ohmic contact with the fourth semiconductor layer; the second semiconductor layer; and the third semiconductor layer. A sixth semiconductor layer formed on the first semiconductor layer and having the second conductivity; a fifth electrode formed on the sixth semiconductor layer and having an ohmic contact on the sixth semiconductor layer; A seventh semiconductor layer formed on the first semiconductor layer, separated from the second semiconductor layer, the third semiconductor layer, and the sixth semiconductor layer, and having the second conductivity; and the seventh semiconductor layer. An eighth semiconductor layer formed on the first semiconductor layer; and a ninth semiconductor layer formed on the seventh semiconductor layer, separated from the eighth semiconductor layer, and having the first conductivity. Formed on the ninth semiconductor layer, A sixth electrode having an ohmic contact in the ninth semiconductor layer, a seventh electrode formed on the eighth semiconductor layer and having an ohmic contact in the eighth semiconductor layer, the second electrode, and the fourth electrode A second wiring that connects, a third wiring that connects the first electrode, the third electrode, and the sixth electrode; and a fourth wiring that connects the fifth electrode and the seventh electrode; The overvoltage protection element includes the second wiring and the fourth wiring as output terminals.

  The overvoltage protection element according to the present invention is the overvoltage protection element including an eighth electrode formed in the third semiconductor layer and having an ohmic contact in the third semiconductor layer.

  The overvoltage protection element of the present invention includes an eighth electrode formed on the third semiconductor layer, having an ohmic contact on the third semiconductor layer, and formed on the seventh semiconductor layer. The overvoltage protection element includes a ninth electrode having an ohmic contact in the semiconductor layer.

  In the overvoltage protection element of the present invention, the eighth electrode is formed along at least one long side of the fourth semiconductor layer and one long side of the fifth semiconductor layer. Further, the overvoltage protection element is used.

  In the overvoltage protection element of the present invention, the eighth electrode is formed along at least one long side of the fourth semiconductor layer and one long side of the fifth semiconductor layer. In addition, the ninth electrode includes at least the overvoltage protection element formed along both the long side of the eighth semiconductor layer and the long side of the ninth semiconductor layer. .

  The overvoltage protection element of the present invention is the overvoltage protection element in which the eighth capacitor and the second wiring are connected by a first capacitor element.

  In the overvoltage protection element of the present invention, the eighth electrode and the second wiring are connected by a first capacitive element, and the ninth electrode and the fourth wiring are connected by a second capacitor. The overvoltage protection element is connected by a capacitive element.

  In the overvoltage protection element of the present invention, the first capacitor element is formed by laminating a first insulating film made of silicon nitride or silicon oxide on the eighth electrode, and the first insulating film is formed on the first insulating film. The overvoltage protection element is a capacitive element having a structure formed by stacking the second wiring.

  In the overvoltage protection element of the present invention, the first capacitor element is formed by laminating a first insulating film made of silicon nitride or silicon oxide on the eighth electrode, and the first insulating film is formed on the first insulating film. A capacitive element having a structure in which a second wiring is laminated, wherein the second capacitive element comprises a second insulating film laminated on the ninth electrode, and the second insulating film on the second insulating film; The overvoltage protection element is a capacitive element having a structure in which four wirings are stacked.

  In the overvoltage protection element of the present invention, a third insulating film made of silicon nitride or silicon oxide is laminated on the third semiconductor layer, and the second wiring is laminated on the third insulating film. The overvoltage protection element includes the third capacitor element having the formed structure.

  In the overvoltage protection element of the present invention, a third insulating film made of silicon nitride or silicon oxide is laminated on the third semiconductor layer, and the second wiring is laminated on the third insulating film. A third capacitive element having a formed structure; a fourth insulating film made of silicon nitride or silicon oxide is stacked on the seventh semiconductor layer; and the fourth wiring is formed on the fourth insulating film. Is formed by the overvoltage protection element having the fourth capacitor element having a structure formed by laminating.

  With the configuration of the overvoltage protection element of the present invention, a small overvoltage protection element can be provided.

  In addition, according to the configuration of the overvoltage protection element of the present invention, an overvoltage protection element with less distortion can be provided by the function of the added capacitance element.

[Embodiment 1]
One embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1A is a circuit diagram of an overvoltage protection element 1 according to Embodiment 1 of the present invention, and FIG. 1B is a plan view of the overvoltage protection element 1 according to Embodiment 1 of the present invention. FIG.1 (c) is a cross-sectional view in the AA line of the overvoltage protection element 1 of FIG.1 (b).

  In the circuit diagram of FIG. 1A, the overvoltage protection element 1 includes NPN transistors Tr1 and Tr2 and a diode D1. The cathode of the diode D1, the collector of the transistor Tr1, the collector of the transistor Tr2, and the emitter of the transistor Tr2 are connected to each other and to the terminal VDD.

  The base of the transistor Tr1 is connected to the base of the transistor Tr2. The anode of the diode D1 and the emitter of the transistor Tr1 are connected to the ground terminal GND.

  In the circuit of FIG. 1A, the terminal VDD and the ground terminal GND are output terminals of a circuit intended for overvoltage protection.

  In the plan view of FIG. 1B and the cross-sectional view of FIG. 1C, the overvoltage protection element 1 includes a semiconductor substrate 2, an element isolation region (deactivation subcollector region) 14, a subcollector region 13, Tr1. Electrode 3 serving as both collector electrode of Tr2 and cathode electrode of D1, collector mesa region 12 common to Tr1 and Tr2, cathode region 11 of D1, base mesa region 5 common to Tr1 and Tr2, anode region 4 of D1, base electrode 6, D1 Anode electrode 18, Tr1 emitter mesa region 7, Tr2 emitter mesa region 8, Tr1 emitter electrode 9, Tr2 emitter electrode 10, insulating film 15, and wirings 16 and 17.

  In the above configuration, the subcollector region 13, the collector mesa region 12, and the cathode region 11 constitute a first conductive first semiconductor layer, the electrode 3 constitutes a first electrode, and the anode region 4 constitutes a first conductive layer. A second conductive second semiconductor layer having a conductivity opposite to the conductivity is formed, the anode electrode 18 forms a second electrode, and the base mesa region 5 forms a second conductive third semiconductor layer. The base electrode 6 constitutes the eighth electrode, the Tr1 emitter mesa region 7 constitutes the first conductive fourth semiconductor layer, and the Tr2 emitter mesa region 8 constitutes the first conductive fifth semiconductor layer. The emitter electrode 10 of Tr2 constitutes the third electrode, the emitter electrode 9 of Tr1 constitutes the fourth electrode, the wiring 16 constitutes the first wiring, and the wiring 17 constitutes the second wiring. Yes.

  One side L1 facing the base electrode 6 of the emitter mesa region 7 of Tr1 shown by the rectangle in FIG. 1B is one side of the long side of the fourth semiconductor layer, and is shown by the rectangle in FIG. One side L2 facing the base electrode 6 of the emitter mesa region 8 of Tr2 is one side of the long side of the fifth semiconductor layer, and the eighth electrode as the base electrode 6 is formed along both of them. The eighth electrode is configured.

  The overvoltage protection element 1 shown in the plan view of FIG. 1B and the cross-sectional view of FIG. 1C can be manufactured as follows.

  First, an N-type GaAs subcollector layer having a relatively high impurity concentration is formed on the semiconductor substrate 2 by epitaxial growth. As the semiconductor substrate 2, for example, a semi-insulating GaAs (potassium arsenide) substrate is used.

  Next, a collector / cathode layer of N-type GaAs having a relatively low impurity concentration is formed on the subcollector layer by epitaxial growth. A P-type GaAs base layer and anode layer is formed on the collector layer and cathode layer by epitaxial growth.

  An N-type AlGaAs emitter layer is formed on the base layer / anode layer by epitaxial growth. Thereafter, etching is performed as follows, and the semiconductor layer is separated to manufacture each element.

  First, the emitter layer is separated by etching to form emitter mesa regions 7 and 8.

  Next, the base layer / anode layer and the collector layer / cathode layer are separated by etching to form the base mesa region 5, the anode region 4 of D1, the collector mesa region 12, and the cathode region 11. Usually, since the base layer of the transistor used for Tr1 and Tr2 is formed thin, it is etched in the same process as the etching of the lower collector / cathode layer to form a base mesa region and a collector mesa region having substantially the same shape in plan view. In the diode element, an anode region and a cathode region having substantially the same shape in plan view are formed.

  Next, ion implantation is performed on the subcollector layer to form an element isolation region 14 with no conductivity, and the subcollector region 13 of the overvoltage protection element 1 is separated from an external circuit.

  Further, each electrode of the transistor and the diode is formed as follows.

  First, in order to make ohmic contact with the emitter mesa regions 7 and 8, emitter electrodes 9 and 10 are formed on the emitter mesa region, respectively.

  Next, a base electrode 6 is formed on the base mesa region in order to make an ohmic contact with the base mesa region 5. This step also serves to form the anode electrode 18 on the anode layer for making ohmic contact with the anode region 4 of D1.

  Next, in order to make ohmic contact with the subcollector region 13, the electrode 3 is formed on the subcollector region.

  Further, an insulating film 15 is formed on the surfaces of the semiconductor and the electrode. The insulating film 15 is silicon nitride. Usually, in order to activate the ohmic contact, heat treatment is performed after the insulating film 15 is formed. Thereafter, a part of the insulating film 15 formed on the electrode 3, the emitter electrodes 9, 10 and the anode electrode 18 is removed by etching. Thereby, a part of the electrode 3, a part of the emitter electrodes 9, 10 and a part of the anode electrode 18 are exposed.

  Then, the exposed part of the electrode 3 and the exposed part of the emitter electrode 10 are electrically connected by the wiring 16. Similarly, the exposed portion of the emitter electrode 9 and the exposed portion of the anode electrode 18 are electrically connected by the wiring 17.

  As described above, in the overvoltage protection element 1, the element connected to the subcollector region 13, that is, the diode D1 and the transistors Tr1 and Tr2 are formed in the same subcollector region 13 without separating the subcollector region 13. I can do it. Therefore, since the space | interval of elements can be narrowed, the occupation area of the overvoltage protection element 1 can be reduced and size reduction is attained.

  Further, in the overvoltage protection element 1, the collector mesa region 12 and the base mesa region 5 of the transistors Tr1 and Tr2 do not need to be separated and can be shared, which contributes to the miniaturization of the circuit.

  These features are the epitaxial growth in order from the subcollector layer, the semiconductors with the necessary conductivity and concentration composition are arranged in advance, and the semiconductor layer is separated by mesa structure or ion implantation. By taking the planar connection and the cross-sectional structure of the circuit connection of FIG. 1A and the elements of FIGS. 1B and 1C, the connection of wiring on the circuit diagram and the arrangement of the physical structure do not contradict each other. This is due to the combination.

  In particular, the above-described configuration is made possible by using a diode using a PN junction of a base layer and a collector layer forming a transistor as the diode D1.

  Further, in the step of separating the emitter mesa regions 7 and 8 in the above step, in some cases, a part of the emitter layer may remain thin on the base layer, and the emitter mesa regions 7 and 8 are connected by a part of the emitter layer. It is good also as a structure. This is a structure often used to prevent deterioration of characteristics of the transistors Tr1 and Tr2 over time.

  However, in this case, a part of the emitter layer left thin in the base layer is set to a thickness not more than “thickness that is completely depleted”, so that the emitter mesa regions 7 and 8 are electrically separated. .

  In addition, a part of the collector layer / cathode layer may be thinly left on the subcollector layer between the collector mesa region and the cathode region in the above process. Usually, it is desirable to remove the collector layer / cathode layer having a relatively low concentration as much as possible so that the electrode 3 can be connected to the subcollector region 13 with a low contact resistance, but originally the collectors of the transistors Tr1 and Tr2 and the diode D1 The cathode is connected in the subcollector region. Therefore, a part of the collector layer exists on the subcollector region between Tr1, Tr2, and D1, and even if it has conductivity, the operation of the overvoltage protection element 1 is not affected.

  Further, in the above process, a mesa separation structure by etching is used for the separation of the semiconductor layer. However, if possible, a separation structure by ion implantation can be used.

  Alternatively, in order to isolate the subcollector region 13 from the peripheral circuit, the element isolation region 14 that has lost conductivity by ion implantation is formed, but the subcollector region 13 and the peripheral circuit are separated by a mesa isolation structure by etching. You can also

  When the upper region of the emitter region has a structure often used as a “non-alloy ohmic structure” such as InGaAs, the emitter electrodes 9 and 10 are omitted and the wirings 16 and 17 are in direct contact with each other. Thus, the contact portion may function as the emitter electrodes 9 and 10.

  Further, as the position of each element in the overvoltage protection element 1, the common base mesa region 5 of Tr1 and Tr2 is arranged in the center, D1 and the electrode 3 are arranged on both sides thereof, and Tr1 is arranged on the side close to D1, With the configuration shown in FIG. 1 in which Tr2 is disposed on the side close to the electrode 3, the wiring layers in the overvoltage protection element 1 do not intersect. Therefore, each element can be connected as shown in FIG. 1A by a single metal wiring layer. With this configuration, the manufacturing process can be simplified.

  When the semiconductor substrate 2 of the overvoltage protection element 1 has a mesa isolation structure by etching with a solution like a GaAs semiconductor and the structure of the overvoltage protection element 1 is manufactured, the orientation in which the slope of the mesa structure becomes a taper structure, There is an orientation in which the slope has a reverse taper structure.

  Normally, when wiring crosses a slope with a reverse taper structure, use an air bridge structure that exceeds the step or a structure that uses an interlayer insulating film such as polyimide that fills the step and flattens the wiring so that the wiring does not break. It will be.

  Also in the present embodiment, when the wiring crosses the inclined surface having the reverse taper structure, the air bridge structure or the structure using an interlayer insulating film such as polyimide should be used in the same manner. Since the number of wirings is small (wirings 16 and 17), there is another effect that wiring can be easily performed while avoiding the inclined surface having the reverse taper structure.

  For example, in the case of the structure of FIG. 1 described above, the arrangement is selected so that the slope parallel to the cross section AA has an inversely tapered structure, and the wiring passes through the slope perpendicular to the cross section AA having the tapered structure. Thus, if the arrangement of the elements is selected, the wirings 16 and 17 can be formed without using an air bridge structure, an interlayer insulating film such as polyimide, and the like, and the overvoltage protection element 1 of FIG. 1 can be manufactured.

  For this reason, in a process in which multi-layer wiring is possible, the overvoltage protection element 1 is connected by the lowermost layer wiring, and a wiring made of another metal wiring layer can pass over the overvoltage protection element 1. Accordingly, the degree of freedom in layout is greatly improved.

  Although the overvoltage protection element 1 has the advantage of being small in size, it is arranged in the signal path from each wire bonding pad, etc., so the above configuration allows the overvoltage protection element to be arranged under the wiring, etc. This leads to a reduction in size, and is more preferable.

  The base electrode 6 can be omitted because there is no connection to the outside. However, the overvoltage protection element 1 uses a leak current (leakage current, specifically an avalanche current or a Zener effect current) flowing from the emitter of the transistor Tr2 to the base of the transistor Tr2.

  Therefore, if the overvoltage protection function is activated and the leakage current no longer flows while the leakage current is as small as possible, the transistor Tr2 that flows the leakage current itself may be deteriorated or destroyed.

  Therefore, it is preferable to dispose the base electrode 6 along the emitter region of the transistor Tr2 and extend the base electrode 6 along the emitter region of the transistor Tr1.

  With the above configuration, the resistance of the path through which the leakage current flows can be reduced, so that the overvoltage protection function works quickly and the reliability of the overvoltage protection element 1 itself can be improved.

  In the epitaxial configuration used for the overvoltage protection element 1, since the sheet resistance of the base layer may be particularly high, in order to reduce the resistance between the bases of Tr1 and Tr2, at least the longitudinal direction of the emitter regions of the transistors Tr1 and Tr2 More preferably, the base electrode 6 is arranged at a position along one side.

  FIG. 2 is a view showing a conventional protective structure (Patent Document 2). 2A is a cross-sectional view showing a conventional protective structure, FIG. 2B is a cross-sectional view showing another conventional protective structure, and FIG. 2C is a cross-sectional view of FIG. It is a circuit diagram of the protection structure of a) and the protection structure of FIG.

  The protection structure of FIG. 2 has a circuit configuration similar to that of the overvoltage protection element 1 of FIG. 1, but is manufactured by determining the conductivity of the semiconductor layer by ion implantation. It is completely different. This is because the restrictions on device fabrication derived from the manufacturing method are completely different.

  The overvoltage protection element 1 according to the first embodiment and the protection structure shown in FIG. For this reason, it is impossible to adopt the same element configuration, and technical ideas such as element miniaturization and terminal sharing are completely different.

  FIG. 3 is a graph showing a simulation result of the circuit of FIG. The simulation was performed as follows.

  A circuit is configured such that an input voltage signal Vin whose maximum value Vin_max gradually increases as shown by a solid line is input to a load circuit having a load impedance of 50Ω from a signal source having an input impedance of 50Ω, and the load circuit In parallel, the circuit of FIG. 1A is connected so that the terminal VDD is on the positive voltage side.

  The GND in FIG. 1A is connected to the ground wiring side that is relatively negative with respect to the signal wiring of the above circuit. The frequency of the input voltage signal Vin and the output voltage signal Vout was 2.5 GHz (gigahertz).

  3 shows the maximum value Vin_max of the input voltage signal Vin on the horizontal axis, the maximum value Vout_max of the output voltage signal Vout generated at the terminal VDD on the left vertical axis (vertical axis Y1), and the maximum value Vin_max of the input voltage signal Vin. Is a graph showing the ratio R of the maximum value Vout_max of the output voltage signal Vout to the right vertical axis (vertical axis Y2).

  Further, on the negative side of the horizontal axis, in the same connection as described above, a signal in which the polarity of Vin in FIG. 1A is reversed, that is, an input voltage signal Vin in which the minimum value Vin_min gradually decreases is input. The simulation results are shown. In this case, the horizontal axis of the graph is changed to the maximum value Vin_max to be the minimum value Vin_min, and similarly, the maximum value Vout_max of the vertical axis of the graph is entered in the graph as the minimum value Vout_min. In this case, R is calculated as a ratio of the minimum value Vout_min to the minimum value Vin_min.

  In the graph of FIG. 3, the maximum value Vout_max increases according to the maximum value Vin_max until 10.7 V (volts) where the overvoltage protection element 1 starts to operate (up to about 11.5 V in the simulation result), and the output voltage signal It can be seen that Vout is not distorted.

  The overvoltage protection element 1 according to the embodiment of the present invention is preferably connected to an input / output circuit of an amplification amplifier that amplifies OFDM modulation such as a wireless LAN that requires high linear amplification characteristics.

  The numerical value of 10.7 V described above indicates that the reverse breakdown voltage (maximum value of the voltage applied from the emitter to the base) of the GaAs bipolar transistor used as the transistor Tr2 in the simulation is 9.5 V, and the collector current of the transistor Tr1 is conductive. It is a numerical value when the base-emitter voltage is 1.2V.

  That is, even if the overvoltage protection element 1 is connected to the wiring through which the high-frequency signal is transmitted, the distortion is very small in the output voltage signal Vout having an assumed overvoltage protection voltage of 10.7 V or less. Note that the overvoltage protection element 1 does not assume that a normal voltage is applied in the reverse direction, that is, a positive voltage is applied relatively to the GND with respect to the terminal VDD. When a voltage signal whose value is equal to or greater than the forward withstand voltage of the diode D1 is input, the overvoltage protection function is activated and the waveform of the output signal is distorted. When the diode D1 is a GaAs diode, the forward breakdown voltage of the diode D1 is approximately 1.2V.

  Comparing FIG. 3 with FIG. 13 which is a simulation result of the configuration of the prior art, it can be seen that in the configuration of the prior art, the ratio R decreases from around 8 V and the line formation is somewhat degraded. On the other hand, such deterioration of linearity is not seen in FIG. Although it is currently unknown what causes this characteristic with good linearity, the configuration of the present embodiment can be downsized as described above, and at least equal to or more than the configuration of the prior art. It was found that the configuration was excellent in linearity.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. The configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 4A is a circuit diagram of the overvoltage protection element 21 according to Embodiment 2 of the present invention, and FIG. 2B is a plan view of the overvoltage protection element 21 according to Embodiment 2 of the present invention. FIG.4 (c) is a cross-sectional view in the AA line of the overvoltage protection element 1 of FIG.4 (b).

  In the circuit diagram of FIG. 4A, the overvoltage protection element 21 further includes NPN transistors Tr3 and Tr4 and a diode D2. The cathode of the diode D1, the collector of the transistor Tr1, the collector of the transistor Tr2, and the emitter of the transistor Tr2, and the cathode of the diode D2, the collector of the transistor Tr4, the collector of the transistor Tr3, and the emitter of the transistor Tr3 are connected to each other.

  The base of the transistor Tr3 is connected to the base of the transistor Tr4. The anode of the diode D2 and the emitter of the transistor Tr4 are connected to the terminal VDD.

  In the plan view of FIG. 4B and the cross-sectional view of FIG. 4C, the overvoltage protection element 21 includes a semiconductor substrate 2, an element isolation region (deactivation subcollector region) 14, a subcollector region 13, Tr1. Tr3, Tr3 and Tr4 collector electrode and D1 and D2 cathode electrode 3; Tr3 and Tr4 common collector mesa region 32; D2 cathode region 31; Tr3 and Tr4 common base mesa region 25; D2 anode region 24, a second base electrode 26, an anode electrode 38 of D2, an emitter mesa region 27 of Tr4, an emitter mesa region 28 of Tr3, an emitter electrode 29 of Tr4, an emitter electrode 30 of Tr3, and wirings 36 and 37.

  In the above configuration, the subcollector region 13 constitutes the first conductive first semiconductor layer, the electrode 3 constitutes the first electrode, the anode region 24 constitutes the sixth semiconductor layer, and the anode electrode 38 , The fifth mesa region 25 constitutes the seventh semiconductor layer, the second base electrode 26 constitutes the ninth electrode, the emitter mesa region 27 of Tr4 constitutes the eighth semiconductor layer, Tr3 Emitter mesa region 28 constitutes the ninth semiconductor layer, Tr3 emitter electrode 30 constitutes the sixth electrode, Tr4 emitter electrode 29 constitutes the seventh electrode, and wiring 36 constitutes the third wiring. The wiring 37 forms a fourth wiring.

  Further, one side L3 facing the second base electrode 26 of the emitter mesa region 27 of Tr4 shown by a rectangle in FIG. 4B is defined as one side of the long side of the eighth semiconductor layer, and FIG. ), The side L4 facing the base electrode 6 of the emitter mesa region 28 of Tr3 indicated by a rectangle is one side of the long side of the ninth semiconductor layer, and the ninth electrode as the second base electrode 26 is , Both are configured as a ninth electrode formed along.

  The overvoltage protection element 21 shown in the plan view of FIG. 4B and the cross-sectional view of FIG. 4C can be manufactured as follows.

  First, an N-type GaAs subcollector layer having a relatively high impurity concentration is formed on the semiconductor substrate 2 by epitaxial growth.

  Next, a collector / cathode layer of N-type GaAs having a relatively low impurity concentration is formed on the subcollector layer by epitaxial growth. A P-type GaAs base layer and anode layer is formed on the collector layer and cathode layer by epitaxial growth.

  An N-type AlGaAs emitter layer is formed on the base layer / anode layer by epitaxial growth. Thereafter, etching is performed as follows, and the semiconductor layer is separated to manufacture each element.

  First, the emitter layer is separated by etching to form emitter mesa regions 7, 8, 27, and 28.

  Next, the base layer / anode layer and the collector layer / cathode layer are separated by etching, and the base mesa regions 5, 25, the anode region 4 of D1, the anode region 24 of D2, the collector mesa regions 12, 32, and the cathode region are separated. 11 and 31 are formed. Usually, since the base layer of the transistor used for Tr1 and Tr2 is formed thin, it is etched in the same process as the etching of the lower collector / cathode layer to form a base mesa region and a collector mesa region having substantially the same shape in plan view. In the diode element, an anode region and a cathode region having substantially the same shape in plan view are formed.

  Next, ion implantation is performed on the subcollector layer to form an element isolation region 14 with no conductivity, and the subcollector region 13 of the overvoltage protection element 21 is separated from an external circuit.

  Further, each electrode of the transistor and the diode is formed as follows.

  First, emitter electrodes 9, 10, 29, and 30 are formed on the emitter mesa region in order to make ohmic contact with the emitter mesa regions 7, 8, 27, and 28, respectively.

  Next, base electrodes 6 and 26 are formed on the base mesa region in order to make ohmic contact with the base mesa regions 5 and 25. This step includes forming an anode electrode 18 on the anode layer for making ohmic contact with the anode region 4 of D1, and forming an anode electrode 38 on the anode layer for making ohmic contact with the anode region 24 of D2. Doubles as

  Next, in order to make ohmic contact with the subcollector region 13, the electrode 3 is formed on the subcollector region.

  Further, an insulating film 15 is formed on the surfaces of the semiconductor and the electrode. The insulating film 15 is silicon nitride. Usually, in order to activate the ohmic contact, heat treatment is performed after the insulating film 15 is formed. Thereafter, a part of the insulating film 15 formed on the electrode 3, the emitter electrodes 9, 10, 29, 30 and the anode electrodes 18, 38 is removed by etching. Thereby, a part of the electrode 3, a part of the emitter electrodes 9, 10, 29, 30 and a part of the anode electrodes 18, 38 are exposed.

  Then, the exposed part of the electrode 3 and the exposed part of the emitter electrodes 10 and 30 are electrically connected by the wiring 36. Similarly, the exposed portion of the emitter electrode 9 and the exposed portion of the anode electrode 18 are electrically connected by the wiring 17, and the exposed portion of the emitter electrode 29 and the exposed portion of the anode electrode 38 are connected to the wiring 37. Connect it electrically.

  The overvoltage protection element 21 has a configuration in which the two overvoltage protection circuits shown in the first embodiment are connected in series in the opposite direction in a form in which the electrode 3 and the subcollector region 13 are shared. In the configuration shown in the present embodiment, even in such a case, since the subcollector region 13 and the electrode 3 are shared by all the semiconductor elements, the element spacing can be minimized and the size can be reduced. Is possible.

  FIG. 5 is a graph showing a simulation result of the circuit of FIG. The simulation was performed as follows.

  A circuit is configured such that an input voltage signal Vin whose maximum value Vin_max gradually increases as shown by a solid line is input to a load circuit having a load impedance of 50Ω from a signal source having an input impedance of 50Ω, and the load circuit In parallel, the circuit of FIG. 4A is connected so that the terminal VDD is on the positive voltage side. The GND of FIG. 4A is connected to the ground wiring side that is relatively negative with respect to the signal wiring of the above circuit. The frequency of the input voltage signal Vin and the output voltage signal Vout was 2.5 GHz (gigahertz).

  In this case, the reverse breakdown voltage (maximum value of the voltage applied from the emitter to the base) of the transistor Tr2, the base-emitter voltage when the collector current of the transistor Tr1 is conducted, and the sum of the forward breakdown voltages of the diode D2. When a voltage equal to or higher than the first sum voltage is applied to the wiring 37, the overvoltage protection function is activated.

  Further, the reverse breakdown voltage of the transistor Tr3 (the maximum value of the voltage applied from the emitter to the base), the base-emitter voltage when the collector current of the transistor Tr4 is conducted, and the sum of the forward breakdown voltages of the diode D1. When a voltage equal to or lower than the polarity reversal voltage obtained by reversing the polarity of the second sum is applied to the wiring 37, an overvoltage protection function is activated.

  5 shows the maximum value Vin_max of the input voltage signal Vin on the horizontal axis, the maximum value Vout_max of the output voltage signal Vout generated at the terminal VDD on the left vertical axis (vertical axis Y1), and the maximum value Vin_max of the input voltage signal Vin. Is a graph showing the ratio R of the maximum value Vout_max of the output voltage signal Vout to the right vertical axis (vertical axis Y2).

  Further, on the negative side of the horizontal axis, in the same connection as described above, a signal in which the polarity of Vin in FIG. 4A is reversed, that is, an input voltage signal Vin in which the minimum value Vin_min gradually decreases is input. The simulation results are shown. In this case, the horizontal axis of the graph is changed to the maximum value Vin_max to be the minimum value Vin_min, and similarly, the maximum value Vout_max of the vertical axis of the graph is entered in the graph as the minimum value Vout_min. In this case, R is calculated as a ratio of the minimum value Vout_min to the minimum value Vin_min.

  Unlike FIGS. 3 and 13, it can be seen that the signal is not distorted up to around −11.5 V in the reverse direction, that is, even in the minimum value Vin_min <0.

  That is, when a voltage not lower than the second sum voltage and not higher than the first sum voltage is input to the wiring 37, the output voltage signal of the system is hardly distorted.

  As described above, the overvoltage protection element 21 is an overvoltage protection element having a high withstand voltage in both the forward and reverse directions of the input voltage signal Vin, despite being formed very small in the single sub-collector region 13.

  In the case of an amplifier circuit composed of NPN transistors, when a voltage signal is directly output from the collector terminal of the amplifier transistor, the output signal is basically a positive voltage signal, but is output via an output matching circuit. In some cases, a negative voltage signal may be output. Since the overvoltage protection element 21 has a high breakdown voltage in both the forward and reverse directions of the input voltage signal Vin, the overvoltage protection element 21 is particularly suitable as an overvoltage protection element connected to the output matching circuit of the amplifier circuit as described above.

  Further, in the configuration shown in the first embodiment, the two lines of wirings 16 and 17 are used. In the second embodiment, the three lines of wirings 17, 36 and 37 are used. Is simple, and the characteristics that can be arranged so that the wirings 17, 36, and 37 do not intersect as shown in FIG. 4B are the same. For this reason, the feature that the wiring layer can be formed by one layer is the same. Further, wiring can be performed while avoiding a reversely tapered element step slope. For example, in the configuration of FIG. 4B, as in the first embodiment, the arrangement is selected so that the slope parallel to the cross section AA has an inverse taper, and the cross section AA having the tapered structure is orthogonal. The arrangement of the elements may be selected so that the wiring passes through the slope.

  In particular, in order to avoid the attenuation of the high-frequency signal by the matching circuit itself, the matching circuit is often wired with an upper layer wiring of which the normal wiring thickness is set thick among the multilayer wiring. For this reason, the structure shown in this embodiment can be formed of only a single lower layer wiring and has a feature that it can be easily formed below the wiring of the output matching circuit. By forming it below the wiring of the output matching circuit, the entire circuit can be further reduced in size.

[Embodiment 3]
The following will describe another embodiment of the present invention with reference to FIG. 1, FIG. 6, FIG. 8, and FIG. The configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and descriptions thereof are omitted.

  The overvoltage protection element of the present embodiment further includes a capacitor C1 indicated by a broken line in the overvoltage protection element 1 of FIG. The base of the transistor Tr1 is connected to the base of the transistor Tr2 and one end of the capacitor C1, and the anode of the diode D1, the emitter of the transistor Tr1 and the other end of the capacitor C1 are connected to the ground terminal GND.

  Here, the capacitor C1 of FIG. 1A constitutes a first capacitor element.

  FIG. 6 is a graph showing a simulation result of the circuit of FIG. 1A including the capacitor C1. The capacitance of the capacitor C1 was 0.5 pF (picofarad).

The simulation was performed in the same manner as in the first embodiment except that the capacitor C1 was present, and was similarly graphed. However, since the overvoltage protection element 1 of the first embodiment has a relatively small distortion even when the capacitor C1 is not provided, the difference in characteristics is difficult to understand. For this reason, in FIG. 6, the ratio R is shown in decibels and is assumed to be a power passing loss. Since the ratio R is a voltage ratio, a common logarithm with 10 as the base is taken as log ₁₀ R and multiplied by 20 to give 20 log ₁₀ R [dB].

  In FIG. 6, the characteristic when the capacitor is excluded (Embodiment 2) is indicated by a broken line, and the characteristic when the capacitor is added is indicated by a solid line.

  In FIG. 6, the characteristic when the capacitor is added is that the power passing loss is reduced by about 0.05 dB to 0.1 dB than the characteristic when the capacitor is removed, and the power passing due to the increase of Vin_max. Less change in loss. In a linearity amplifier such as a WLAN (Wireless Local Area Network), characteristic deterioration starts to occur when the distortion of the entire circuit changes by about 0.2 dB to 0.3 dB. For this reason, the distortion of 0.1 dB that the overvoltage protection element that originally does not amplify cannot be ignored.

  Therefore, the overvoltage protection element according to the third embodiment including the capacitor C1 can be used as an overvoltage protection element more suitable for the linearity amplifier as described above.

  Hereinafter, the reason why the linearity is improved when the capacitor C1 is added will be described.

  In the case of the circuit of FIG. 1A, the terminal VDD and the base terminal of the transistor Tr1 are connected by the collector-base capacitance of the transistor Tr1, the collector-base capacitance of the transistor Tr2, and the emitter-base capacitance of the transistor Tr2. There is a parasitic capacitance between them.

  When the voltage is applied to the terminal VDD, the parasitic capacitance supplies a transient current to the base terminal of the transistor Tr1 before the voltage between the base and the emitter of the transistor Tr2 reaches the reverse leakage voltage. It has the effect of raising the base potential of the transistor Tr1. For this reason, the collector-emitter of the transistor Tr1 is slightly conducted. It is considered that a loss is caused by this conduction.

  By adding the capacitor C1, it becomes possible to flow a current due to the parasitic capacitance to the terminal GND. For this reason, it is preferable to set the capacitance value of the capacitor C1 to a value equal to or larger than the parasitic capacitance, preferably about twice the parasitic capacitance. In the first and second embodiments, since the parasitic capacitance is about 0.25 pF, the capacitance value of the capacitor C1 is set to 0.5 pF.

  Note that if the capacitance value of the capacitor C1 is too large, the response to the overvoltage pulse is delayed, but the assumed width of the overvoltage pulse is about several tens of nsec (nanoseconds) in time. For this reason, if the frequency of the input / output signal is several GHz or more, the overvoltage protection element 1 can be used without any problem.

  The capacitor C1 in FIG. 1A can be manufactured in a region outside a transistor or a region outside a diode, as shown by the overvoltage protection element 41 in FIG.

  The overvoltage protection element 41 changes the wiring 17 from the overvoltage protection element 1 in FIG. 1 to the wiring 47, and the wiring 47 electrically connects the exposed part of the emitter electrode 9 and the exposed part of the anode electrode 18. At the same time, an insulating film 51 is provided between the capacitor electrode 50 and the capacitor electrode 50 connected to the base electrode 6, and the capacitor C 1 is formed by the wiring 47, the capacitor electrode 50 and the insulating film 51. It is assumed that a portion where the wiring 47 and the capacitor electrode 50 overlap at a portion other than the insulating film 51 is insulated and separated by an insulating structure (not shown) (for example, an air bridge structure).

  Alternatively, the capacitor C1 in FIG. 1A can be manufactured as an inter-wiring capacitance in the transistor region, as shown by the overvoltage protection element 61 in FIG.

  The overvoltage protection element 61 changes the wiring 17 to the wiring 67 from the overvoltage protection element 1 of FIG. 1, and the wiring 67 electrically connects the exposed part of the emitter electrode 9 and the exposed part of the anode electrode 18. In addition, the insulating film 15 is sandwiched in the region 71 between the base electrode 6 and the wiring 67 and the base electrode 6, the insulating film 15, and the wiring 67 are arranged in this order so as to produce an interwiring capacitance. Yes. Similarly, the insulating film 15 is sandwiched in the region 72 between the base mesa region 5 and the wiring 67, and the base mesa region 5, the insulating film 15, and the wiring 67 are arranged in this order so as to produce an interwiring capacitance. Yes.

  That is, the external capacitance formed by the wiring 47, the capacitor electrode 50, and the insulating film 51 in FIG. 8 constitutes the first capacitive element, and the insulating film in the portion sandwiched between the base electrode 6 and the wiring 67 in FIG. 15 constitutes a first insulating film made of silicon nitride or silicon oxide, and a portion of the insulating film 15 sandwiched between the base mesa region 5 and the wiring 67 in FIG. 9 is a third insulating film made of silicon nitride or silicon oxide. It constitutes a membrane.

  In the epitaxial layer according to each embodiment of the present invention, the base mesa regions 5 and 25 generally have a relatively high sheet resistance. For this reason, the configuration in which the wiring capacitance is produced between the base electrode 6 and the wiring 17 is connected in series to the constructed wiring capacitance, rather than the production of the wiring capacitance between the base mesa region 5 and the wiring 17. The parasitic resistance contained in the form is reduced. Therefore, linearity can be improved with a smaller capacitance value.

  In addition, each capacitance mentioned above, that is, the external capacitance formed by the wiring 47, the capacitor electrode 50, and the insulating film 51 in FIG. 8, the inter-wiring capacitance formed by the base electrode 6, the insulating film 15, and the wiring 67 in FIG. The inter-wiring capacitance formed by the base mesa region 5, the insulating film 15, and the wiring 67 in FIG. 9 may be used alone or in combination. In order to reduce the occupied area of the entire overvoltage protection element, it is preferable to use the inter-wiring capacity as much as possible and to make up for the shortage with an external capacity.

  In the above description, it has been described that the insulating film 15 is made of silicon nitride or silicon oxide, but the insulating film 51 may similarly be made of silicon nitride or silicon oxide. In particular, by using silicon nitride or silicon oxide as the insulating film 51, the insulating film 51 functions as a protective film for each element and is formed relatively thin. The value can be increased.

[Embodiment 4]
The following will describe another embodiment of the present invention with reference to FIGS. The configurations other than those described in the present embodiment are the same as those in the second embodiment and the third embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment, the second embodiment, and the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. Omitted.

  The overvoltage protection element of the present embodiment further includes capacitors C1 and C2 indicated by broken lines in the overvoltage protection element 21 of FIG. The base of the transistor Tr3 is connected to the base of the transistor Tr4 and one end of the capacitor C2. The anode of the diode D2, the emitter of the transistor Tr4, and the other end of the capacitor C2 are connected to the terminal VDD.

  Here, the capacitor C1 in FIG. 4A constitutes a first capacitive element, and the capacitor C2 in FIG. 4A constitutes a second capacitive element.

  Capacitors C1 and C2 in FIG. 4A can be fabricated in a region outside the transistor or a region outside the diode, similarly to the overvoltage protection element 41 shown in FIG. Although not shown, for example, the overvoltage protection element 41 of FIG. 8 is formed by sharing the subcollector region 13 and the electrode 3 and connecting the two overvoltage protection elements in series in the opposite direction. To do.

  Alternatively, the capacitors C1 and C2 in FIG. 4A can be manufactured as inter-wiring capacitances in the transistor region, similarly to the overvoltage protection element 61 shown in FIG. Similarly, two overvoltage protection elements 61 shown in FIG. 9 may be formed by sharing the subcollector region 13 and the electrode 3 and connecting the two overvoltage protection elements in series in the opposite direction. it can.

  At this time, the external capacitance formed by the wiring 47, the capacitor electrode 50, and the insulating film 51 of FIG. 8 constitutes the first capacitive element, and in the other overvoltage protection element connected in series in the reverse direction, As in the case of the capacitor element, the external capacitor formed by the wiring 47, the capacitor electrode 50, and the insulating film 51 constitutes the second capacitor element.

  The portion of the insulating film 15 sandwiched between the base electrode 6 and the wiring 67 in FIG. 9 constitutes a first insulating film made of silicon nitride or silicon oxide. The base electrode 6, the wiring 67 and the first insulating film constitute the first insulating film. A first capacitive element is configured. In addition, a portion of the insulating film sandwiched between the base electrode 6 and the wiring 67 in another overvoltage protection element connected in series in the reverse direction constitutes a second insulating film made of silicon nitride or silicon oxide, Similarly, a third capacitor element is formed.

  Alternatively, the portion of the insulating film 15 sandwiched between the base mesa region 5 and the wiring 67 in FIG. 9 constitutes a third insulating film made of silicon nitride or silicon oxide, and the base mesa region 5, the wiring 67 and the third insulating film 15. The insulating film forms a second capacitor element. In addition, the base mesa region 5 in another overvoltage protection element connected in series in the opposite direction and the portion of the insulating film 15 sandwiched between the wirings 67 constitute a fourth insulating film made of silicon nitride or silicon oxide. Similarly, the fourth capacitor element is formed.

  FIG. 7 is a graph showing a simulation result of the circuit of FIG. 4A including the capacitors C1 and C2. Capacitors C1 and C2 each had a capacitance of 0.5 pF (picofarad).

The simulation was performed in the same manner as in the second embodiment except that the capacitors C1 and C2 were present, and was similarly graphed. However, as in the case of the third embodiment, the ratio R is expressed in decibels (20 log ₁₀ R [dB]) to make the difference in characteristics easy to understand, and is assumed as a power passing loss.

  In FIG. 7, the characteristic when the capacitor is excluded (Embodiment 2) is indicated by a broken line, and the characteristic when the capacitor is added is indicated by a solid line.

  In FIG. 7, the characteristic when the capacitor is added is that the power passing loss is reduced by about 0.05 dB to 0.1 dB than the characteristic when the capacitor is removed, and the power passing loss accompanying the increase of Vin_Max. The overvoltage protection element of the fourth embodiment including the capacitors C1 and C2 can be used as an overvoltage protection element more suitable for a linearity amplifier.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  Since the overvoltage protection element of the present invention is small and has little distortion of high-frequency signals, it is preferable to connect it to an input / output circuit of an amplification amplifier that amplifies OFDM modulation such as a wireless LAN.

(A) is a circuit diagram of the overvoltage protection element according to the embodiment of the present invention, (b) is a plan view of the overvoltage protection element according to the embodiment of the present invention, and (c) is an overvoltage protection of (b). It is a cross-sectional view of an element. (A) is a cross-sectional view showing a conventional protective structure, (b) is a cross-sectional view showing another conventional protective structure, (c) is a protective structure of (a) and ( It is a circuit diagram of the protection structure of b). It is a graph which shows the simulation result of the circuit of Fig.1 (a) except a capacitor. (A) is a circuit diagram of the overvoltage protection element which concerns on other embodiment of this invention, (b) is a top view of the overvoltage protection element which concerns on other embodiment of this invention, (c) is (b) 2) is a cross-sectional view of the overvoltage protection element of FIG. It is a graph which shows the simulation result of the circuit of Fig.4 (a) except a capacitor. It is a graph which shows the simulation result of the circuit of Fig.1 (a) provided with the capacitor. It is a graph which shows the simulation result of the circuit of Fig.4 (a) provided with the capacitor. It is a top view of the overvoltage protection element provided with the capacitor based on another embodiment of the present invention. It is a top view of the overvoltage protection element provided with the capacitor based on another embodiment of the present invention. It is a top view of the conventional overvoltage protection circuit. It is a circuit diagram of the other conventional overvoltage protection circuit. It is the graph which showed the simulation result of the circuit which inputs the input voltage signal from which the maximum value becomes high gradually from the signal source which has 50 Ω input impedance to the load circuit whose load impedance is 50 Ω. The horizontal axis represents the maximum value of the input voltage signal, the vertical axis on the left represents the voltage generated at the output terminal of the circuit in FIG. 10, and the ratio between the maximum value of the input voltage signal and the voltage generated at the output terminal of the circuit in FIG. Is a graph showing the right vertical axis.

Explanation of symbols

1, 21, 41, 61 Overvoltage protection element 2 Semiconductor substrate 3 Electrode (first electrode)
4 Anode region (second semiconductor layer)
5 Base mesa region (third semiconductor layer)
6 Base electrode (8th electrode)
7 Emitter mesa region (fourth semiconductor layer)
8 Emitter mesa region (fifth semiconductor layer)
9 Emitter electrode (4th electrode)
10 Emitter electrode (third electrode)
11 Cathode region 12 Collector mesa region 13 Subcollector region (first semiconductor layer)
14 Element isolation region 15, 51 Insulating film (first insulating film to sixth insulating film)
16 wiring (first wiring, output terminal)
17 Wiring (second wiring, output terminal)
18 Anode electrode (second electrode)
24 Anode region (sixth semiconductor layer)
25 Base mesa region (seventh semiconductor layer)
26 Second base electrode (ninth electrode)
27 Emitter mesa region (eighth semiconductor layer)
28 Emitter mesa region (9th semiconductor layer)
29 Emitter electrode (seventh electrode)
30 Emitter electrode (sixth electrode)
31 Cathode region 32 Collector mesa region 36 Wiring (third wiring)
37 Wiring (4th wiring, output terminal)
38 Anode electrode (5th electrode)
47, 67 Wiring 50 Capacitor electrode (first capacitor electrode, second capacitor electrode)
71, 72 region C1, C2 capacitor D1 diode (first diode)
D2 Diode L1, L2, L3, L4 Long side of emitter layer GND, VDD terminal Tr1 NPN transistor (first transistor)
Tr2 NPN transistor (second transistor)
Tr3, Tr4 NPN transistor Vin Input voltage signal Vout Output voltage signal

Claims (12)

A first electrode formed on the first conductive first semiconductor layer and having an ohmic contact with the first semiconductor layer;
A second semiconductor layer formed on the first semiconductor layer and having a second conductivity that is opposite to the first conductivity;
A second electrode formed on the second semiconductor layer and having an ohmic contact with the second semiconductor layer;
A third semiconductor layer separated from the second semiconductor layer and formed on the first semiconductor layer and having the second conductivity;
A fourth semiconductor layer formed on the third semiconductor layer and having the first conductivity;
A fifth semiconductor layer separated from the fourth semiconductor layer and formed on the third semiconductor layer and having the first conductivity;
A third electrode formed on the fifth semiconductor layer and having an ohmic contact with the fifth semiconductor layer;
A fourth electrode formed on the fourth semiconductor layer and having an ohmic contact with the fourth semiconductor layer;
A first wiring connecting the first electrode and the third electrode;
A second wiring connecting the second electrode and the fourth electrode;
An overvoltage protection element, wherein the first wiring and the second wiring are output terminals. A first electrode formed on the first conductive first semiconductor layer and having an ohmic contact with the first semiconductor layer;
A second semiconductor layer formed on the first semiconductor layer and having a second conductivity that is opposite to the first conductivity;
A second electrode formed on the second semiconductor layer and having an ohmic contact with the second semiconductor layer;
A third semiconductor layer separated from the second semiconductor layer and formed on the first semiconductor layer and having the second conductivity;
A fourth semiconductor layer formed on the third semiconductor layer and having the first conductivity;
A fifth semiconductor layer separated from the fourth semiconductor layer and formed on the third semiconductor layer and having the first conductivity;
A third electrode formed on the fifth semiconductor layer and having an ohmic contact with the fifth semiconductor layer;
A fourth electrode formed on the fourth semiconductor layer and having an ohmic contact with the fourth semiconductor layer;
A sixth semiconductor layer formed on the first semiconductor layer separately from the second semiconductor layer and the third semiconductor layer and having the second conductivity;
A fifth electrode formed on the sixth semiconductor layer and having an ohmic contact with the sixth semiconductor layer;
A seventh semiconductor layer formed on the first semiconductor layer, separated from the second semiconductor layer, the third semiconductor layer, and the sixth semiconductor layer, and having the second conductivity;
An eighth semiconductor layer formed on the seventh semiconductor layer and having the first conductivity;
A ninth semiconductor layer formed on the seventh semiconductor layer, separated from the eighth semiconductor layer and having the first conductivity;
A sixth electrode formed on the ninth semiconductor layer and having an ohmic contact with the ninth semiconductor layer;
A seventh electrode formed on the eighth semiconductor layer and having an ohmic contact with the eighth semiconductor layer;
A second wiring connecting the second electrode and the fourth electrode;
A third wiring connecting the first electrode, the third electrode, and the sixth electrode;
A fourth wiring connecting the fifth electrode and the seventh electrode;
The overvoltage protection element, wherein the second wiring and the fourth wiring are output terminals.   The overvoltage protection element according to claim 1, further comprising an eighth electrode formed in the third semiconductor layer and having an ohmic contact on the third semiconductor layer.   An eighth electrode formed on the third semiconductor layer and having an ohmic contact on the third semiconductor layer; and a ninth electrode formed on the seventh semiconductor layer and having an ohmic contact on the seventh semiconductor layer. The overvoltage protection element according to claim 2, wherein the overvoltage protection element is provided.   The eighth electrode is formed along at least one long side of the fourth semiconductor layer and one long side of the fifth semiconductor layer. The overvoltage protection element according to 1.   The eighth electrode is formed along at least one long side of the fourth semiconductor layer and one long side of the fifth semiconductor layer, and the ninth electrode includes at least the long side The overvoltage protection element according to claim 4, wherein the overvoltage protection element is formed along both one long side of the eighth semiconductor layer and one long side of the ninth semiconductor layer.   6. The overvoltage protection element according to claim 5, wherein the eighth capacitor and the second wiring are connected by a first capacitor element.   The eighth capacitor and the second wiring are connected by a first capacitive element, and the ninth electrode and the fourth wiring are connected by a second capacitive element. 6. The overvoltage protection element according to 6.   The first capacitive element is formed by laminating a first insulating film made of silicon nitride or silicon oxide on the eighth electrode, and laminating the second wiring on the first insulating film. The overvoltage protection element according to claim 7, wherein the overvoltage protection element is a capacitive element having a structure. The first capacitive element is formed by laminating a first insulating film made of silicon nitride or silicon oxide on the eighth electrode, and laminating the second wiring on the first insulating film. A capacitive element having a structure;
The second capacitive element is a capacitive element having a structure in which a second insulating film is laminated on the ninth electrode and the fourth wiring is laminated on the second insulating film. The overvoltage protection element according to claim 8, wherein   A third capacitive element having a structure in which a third insulating film made of silicon nitride or silicon oxide is laminated on the third semiconductor layer, and the second wiring is laminated on the third insulating film. The overvoltage protection element according to claim 9, comprising: A third capacitive element having a structure in which a third insulating film made of silicon nitride or silicon oxide is laminated on the third semiconductor layer, and the second wiring is laminated on the third insulating film. Have
A fourth capacitive element having a structure in which a fourth insulating film made of silicon nitride or silicon oxide is laminated on the seventh semiconductor layer, and the fourth wiring is laminated on the fourth insulating film. The overvoltage protection element according to claim 10, comprising:

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