JP2010135589A - Method of manufacturing field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an FET capable of attaining high positioning precision and a high degree of integration. <P>SOLUTION: The method of manufacturing the FET includes: forming a first n-type semiconductor layer 21 on the surface of a p-type semiconductor substrate 10 and then forming a first p-type semiconductor layer 31 thereupon by an epitaxial growing method; implanting ions of a p-type impurity in a portion of the first n-type semiconductor layer 21 to form a second p-type semiconductor layer 32; implanting ions of an n-type impurity in a portion of the first p-type semiconductor layer 31 to obtain an N-type well 61 comprising the first n-type semiconductor layer 21 and a second n-type semiconductor layer 22; and then forming an N channel type FET at a P-type well 62 comprising the region of the first p-type semiconductor layer 31 enclosed with the N-type well 61. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a field effect transistor, and more particularly, to a method for manufacturing a field effect transistor for obtaining a medium and high breakdown voltage field effect transistor having a so-called triple well structure.

  In a high voltage integrated circuit such as an LCD driver used in a television receiver or the like equipped with a liquid crystal display device, there are a high voltage MOSFET circuit that handles a voltage of several tens of volts and a low voltage CMOS logic circuit that operates at several volts. Integrated on the same semiconductor substrate. In such an integrated circuit, it is necessary to insulate a high breakdown voltage N-channel field effect transistor (hereinafter sometimes abbreviated as FET) from a p-type semiconductor substrate depending on the application. For this purpose, a P-type well in which a high breakdown voltage N-channel FET is to be formed is formed in an N-type well formed deep from the surface of the p-type semiconductor substrate, and the p-type semiconductor substrate and the high breakdown voltage N-channel are formed. The P-type well of the type FET is insulated by a pn junction. Such an N-channel FET may be referred to herein as a “triple well N-channel FET”.

  An example of the cross-sectional structure of such an integrated circuit is shown in the conceptual diagram of FIG. The substrate 210 is made of a p-type semiconductor substrate, and a high-resistance p-type semiconductor layer 211 is provided on the substrate 210. The p-type semiconductor layer 211 is formed with a triple well / N-channel FET 201, a high-medium-breakdown-voltage or low-breakdown-voltage N-channel FET 203 and a P-channel FET 204. In FIG. 9, the element isolation region is not shown.

  A manufacturing method of an N-channel FET and a P-channel FET having such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-193442. The outline of the manufacturing method disclosed in this patent publication will be described below.

[Step-10]
First, an n-type semiconductor layer 211 is formed at a deep position of the p-type semiconductor substrate 210 based on an ion implantation method. The n-type semiconductor layer 211 is formed on the entire surface of the p-type semiconductor substrate 210 or in a desired region. A region of the p-type semiconductor substrate 210 located on the n-type semiconductor layer 211 is referred to as a p-type semiconductor layer 212.

[Step-20]
Next, the p-type semiconductor layer 213 is epitaxially grown on the p-type semiconductor layer 212 (see FIG. 10A).

[Step-30]
Thereafter, an n-type semiconductor region 214 reaching the n-type semiconductor layer 211 is formed in a predetermined region of the p-type semiconductor layers 212 and 213 above the n-type semiconductor layer 211 based on an ion implantation method (FIG. 10B). reference).

[Step-40]
Next, a p-type semiconductor region 215 is formed in part of the n-type semiconductor region 214 based on an ion implantation method. As a result, a first N-type well 216 made of an n-type semiconductor region 214 and a first P-type well 217 made of a p-type semiconductor region 215 can be obtained (see FIG. 10C).

[Step-50]
Thereafter, the second N-type well 218 for the low-voltage P-channel FET is ionized in the p-type semiconductor layer 213 except for the n-type semiconductor region 214, the first N-type well 216, and the first P-type well 217. It forms based on the injection method. Thus, the second P-type well 219 and the second N-type well 218 made of the p-type semiconductor layer 213 can be obtained (see FIG. 10D).

[Step-60]
Next, in each well 216, 217, 218, 219, a high-voltage P-channel FET 202, a high-breakdown-voltage N-channel FET 201, a low-voltage P-channel FET 204, and a low-voltage N-channel FET 203 are formed.

JP2004193345

  However, the technique disclosed in this patent publication has the following problems.

  That is, in [Step-10], an alignment mark is formed on the surface of the p-type semiconductor substrate 210 before the n-type semiconductor layer 211 is formed in the deep position of the p-type semiconductor substrate 210 based on the ion implantation method. However, since the thick p-type semiconductor layer 213 is epitaxially grown on the p-type semiconductor substrate 210 in [Step-20], the alignment mark provided on the surface of the p-type semiconductor substrate 210 is subjected to dimensional change or deformation. End up. Therefore, it is necessary to form a special alignment mark corresponding to the epitaxial growth of the p-type semiconductor layer 213. Alternatively, there is no allowance for alignment in a later process, and it becomes difficult to arrange the FETs in the closest density.

  When the n-type semiconductor layer 211 is formed in a desired region, the n-type semiconductor region 214 is formed from the n-type semiconductor layer 211 when the n-type semiconductor region 214 is formed based on the ion implantation method in [Step-30]. It must be prevented from protruding. In other words, the n-type semiconductor layer 211 must be formed larger as much as possible for misalignment. Accordingly, the occupation area of the high-breakdown-voltage N-channel FET 201 is increased by the amount of misalignment, and a high integration degree cannot be obtained in the high-voltage MOSFET circuit, and the chip area increases.

  Further, the second P-type well 219 made of the p-type semiconductor layer 213 is located above the n-type semiconductor layer 211. Therefore, the sheet resistance of the P-type well is increased as compared with the case where the n-type semiconductor layer 211 is not provided. As a result, the well potential is easily raised and latch-up is likely to occur. In addition, since the n-type semiconductor layer 211 exists, a ground electrode for the second P-type well 219 cannot be provided on the back surface of the p-type semiconductor substrate 210, and a wire is formed on the surface side of the p-type semiconductor substrate 210. It is necessary to secure a sufficient number of bonds and bump wiring. As a result, there is a possibility that the chip area increases due to an increase in the number of contact pads.

  Therefore, an object of the present invention is to provide a method of manufacturing a field effect transistor having a structure in which high alignment accuracy and high integration degree can be obtained, and a ground electrode can be provided on the back surface of a semiconductor substrate and latch-up is unlikely to occur. It is to provide.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the first aspect of the present invention includes:
(A) forming a first n-type semiconductor layer on the surface of a p-type semiconductor substrate;
(B) forming a first p-type semiconductor layer on the first n-type semiconductor layer based on an epitaxial growth method;
(C) P-type impurities are ion-implanted into a region of the first n-type semiconductor layer that does not form an N-type well, and this region is used as a second p-type semiconductor layer.
(D) An n-type impurity is ion-implanted into a portion of the first p-type semiconductor layer located above the outer periphery of the region of the first n-type semiconductor layer in which the N-type well is to be formed. After obtaining an N-type well composed of an n-type semiconductor layer and a second n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer,
(E) forming an N-channel field effect transistor (abbreviated as N-channel FET) in a P-type well composed of a region of the first p-type semiconductor layer surrounded by the N-type well;
It consists of each process.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the second aspect of the present invention includes:
(A) After ion-implanting n-type impurities into the p-type semiconductor substrate, a p-type semiconductor layer is formed on the p-type semiconductor substrate, whereby the p-type semiconductor substrate, the first n-type semiconductor layer, the first After obtaining the laminated structure of 1 p-type semiconductor layer,
(B) P-type impurities are ion-implanted into a region of the first n-type semiconductor layer where the N-type well is not formed, and the region is used as a second p-type semiconductor layer.
(C) An n-type impurity is ion-implanted into a portion of the first p-type semiconductor layer located above the outer periphery of the region of the first n-type semiconductor layer in which the N-type well is to be formed. After obtaining an N-type well composed of an n-type semiconductor layer and a second n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer,
(D) forming an N-channel FET in a P-type well composed of a region of the first p-type semiconductor layer surrounded by the N-type well;
It consists of each process.

  In the method of manufacturing a field effect transistor according to the first aspect of the present invention, in step (B), a first p-type semiconductor layer is formed on the first n-type semiconductor layer based on an epitaxial growth method, In step (C), p-type impurities are ion-implanted into a region of the first n-type semiconductor layer in which the N-type well is not formed, and this region is used as a second p-type semiconductor layer. And what is necessary is just to form an alignment mark between a process (B) and a process (C). In the field effect transistor manufacturing method according to the second aspect of the present invention, in step (A), an n-type impurity is ion-implanted into the p-type semiconductor substrate, and then the p-type semiconductor substrate is formed. A p-type semiconductor layer is formed, and in step (B), p-type impurities are ion-implanted into a region of the first n-type semiconductor layer where an N-type well is not formed, and this region is used as a second p-type semiconductor layer. To do. And what is necessary is just to form an alignment mark between a process (A) and a process (B).

  That is, in the method for manufacturing the field effect transistor according to the first aspect or the second aspect of the present invention, an alignment mark is formed on the first p-type semiconductor layer, and various subsequent processes are performed based on the alignment mark. Alignment in the process may be performed. Accordingly, it is possible to minimize the margin for alignment between the N-channel FET (triple well / N-channel FET) formed in the P-type well and the other FETs. Therefore, the close-packed arrangement of each FET is possible, and a high degree of integration can be obtained. Further, since the alignment mark is provided after the formation of the thick first p-type semiconductor layer, it is difficult to undergo a dimensional change or deformation of the alignment mark in a subsequent process. Therefore, it is not necessary to form a special alignment mark corresponding to the epitaxial growth of the semiconductor layer.

  The first p-type semiconductor layer is connected to the p-type semiconductor substrate through the second p-type semiconductor layer. Therefore, if a second N-channel FET is formed by using the first p-type semiconductor layer as a second P-type well, the back surface of the p-type semiconductor substrate is grounded for the second P-type well. An electrode can be provided, and the chip area does not increase. Furthermore, the sheet resistance of the second P-type well does not increase and latch-up is unlikely to occur.

Hereinafter, the present invention will be described based on examples with reference to the drawings. However, the present invention is not limited to the examples, and various numerical values and materials in the examples are examples. The description will be given in the following order.
1. 1. General Description of Field Effect Transistor Manufacturing Method of the Present Invention Example 1 (Specific Description of Manufacturing Method of Field Effect Transistor according to First Aspect of Present Invention)
3. Example 2 (Modification of the Field Effect Transistor Manufacturing Method of Example 1)
4). Example 3 (Specific Description of Field Effect Transistor Manufacturing Method According to First Aspect of the Present Invention)
5). Example 4 (Modification of the Field Effect Transistor Manufacturing Method of Example 3)

[Description of General Method for Manufacturing Field Effect Transistor of the Present Invention]
In the manufacturing method of the field effect transistor according to the first aspect of the present invention, in the step (D), and in the manufacturing method of the field effect transistor according to the second aspect of the present invention, In step (C), an n-type impurity is ion-implanted into a region of the first p-type semiconductor layer where a P-channel field effect transistor (abbreviated as P-channel FET) is to be formed to form an N-type well. ,
In the method of manufacturing a field effect transistor according to the first aspect of the present invention, between the steps (D) and (E) or after the step (E), the method of the present invention is also applied. In the method for producing a field effect transistor according to the second aspect, a P-channel FET is provided between the steps (C) and (D) or after the step (D). It can be set as the form including the process to form.

  Moreover, in the manufacturing method of the field effect transistor according to the first aspect of the present invention including the above preferable mode, between the steps (D) and (E), or in the step (E) Later, in the method of manufacturing a field effect transistor according to the second aspect of the present invention including the above-described preferable mode, between the steps (C) and (D) or the step (D ) And a step of forming a second N-channel FET using the region of the first p-type semiconductor layer located above the second p-type semiconductor layer as a second P-type well. Can do.

  Furthermore, in the manufacturing method of the field effect transistor according to the first aspect of the present invention including the above-described preferable modes and configurations, the above-described preferable modes are provided between the steps (D) and (E). In the method of manufacturing the field effect transistor according to the second aspect of the present invention including the form and configuration, the third p-type semiconductor layer is formed on the entire surface between the steps (C) and (D). Then, an n-type impurity is ion-implanted into a portion of the third p-type semiconductor layer located above the second n-type semiconductor layer, so that a third extending upward from the second n-type semiconductor layer is formed. The step of obtaining the n-type semiconductor layer is executed (this step may be repeated twice or more), and the method of manufacturing the field effect transistor according to the first aspect of the present invention includes the step In (E), the field effect transistor according to the second aspect of the present invention In the manufacturing method, in the step (D), the first n-type semiconductor layer, the second n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer, and the third n-type semiconductor layer. An N-channel FET (triple well / N-channel FET) is formed in the regions of the first p-type semiconductor layer and the third p-type semiconductor layer surrounded by the N-type well made of the semiconductor layer. it can.

  In the method of manufacturing a field effect transistor according to the first aspect of the present invention including the above-described preferred form and configuration, the first n-type semiconductor is formed on the surface of the p-type semiconductor substrate in the step (A). The layer can be formed by an epitaxial growth method (epitaxial growth method that performs in-situ doping).

In the method for manufacturing the field effect transistor according to the first aspect or the second aspect of the present invention including the preferred embodiment and configuration described above, the concentration of the type impurity in each semiconductor layer is, for example, secondary ion mass spectrometry ( SIMS analysis). Here, when the concentration of the n-type impurity in the first n-type semiconductor layer is “1.00”, the concentration of the n-type impurity in the second n-type semiconductor layer and the third n-type semiconductor layer is as follows. Examples include 1 × 10 ^{−3 to} 5 × 10 ² and 1 × 10 ^{−3 to} 5 × 10 ² . Further, the concentration of the p-type impurity in the first p-type semiconductor layer, the second p-type semiconductor layer, and the third p-type semiconductor layer is 1 × 10 ^{−4 to} 1 × 10, 1 × 10 respectively. ^{-4 to} 1x10 and ^{1x10 -4 to} 1x10. Since the second p-type semiconductor layer is formed by ion-implanting p-type impurities into the first n-type semiconductor layer, the concentration of the n-type impurities contained in the second p-type semiconductor layer is Basically, it is “1.00”. Examples of the p-type impurity to be ion-implanted into the first n-type semiconductor layer include boron (B) and indium (In).

  Example 1 relates to a method of manufacturing a field effect transistor according to the first aspect of the present invention. 1A to 1C and FIG. 2A to FIG. 2C are schematic partial cross-sectional views of the semiconductor substrate and the like. Will be explained.

[Step-100]
First, a buffer layer 11 containing a low-concentration p-type impurity having an appropriate thickness is epitaxially grown on a p-type semiconductor substrate 10 composed of a low-resistance p-type silicon semiconductor substrate having a plane orientation (100) (FIG. 1). (See (A)). Note that the p-type semiconductor substrate 10 contains, for example, boron as a p-type impurity, and the electrical resistivity is, for example, 0.01 Ω · cm.

[Step-110]
Thereafter, the first n-type semiconductor layer 21 is formed on the surface of the p-type semiconductor substrate, and then the first p-type semiconductor layer 31 is epitaxially grown on the first n-type semiconductor layer 21 (in-situ introduction). (Epitaxial growth method performing in-situ doping)) (see FIG. 1B). Thereafter, alignment marks (not shown) are provided on the first p-type semiconductor layer 31. The impurity concentrations of the first n-type semiconductor layer 21 and the first p-type semiconductor layer 31 are illustrated in Table 1 below. The thickness of the first n-type semiconductor layer 21 is such that a desired breakdown voltage can be obtained between the first n-type semiconductor layer 21 and the p-type semiconductor substrate 10 or between the P-type well 62 formed in a later step. do it. In addition, the thickness of the first p-type semiconductor layer 31 is such that the breakdown voltage between the first p-type semiconductor layer 31 and the N-channel type formed in the first p-type semiconductor layer 31 in a later step is determined. It may be determined based on the punch-through breakdown voltage between the FET (triple well / N-channel FET) and the first p-type semiconductor layer 31.

[Table 1]
First n-type semiconductor layer 21: impurity: phosphorus
Concentration: 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³
Thickness: 0.5 μm to 2 μm
First p-type semiconductor layer 31: Impurity: Boron
^{Concentration: 1 × 10 15 ~5 × 10} 16 / cm 3
Thickness: 4μm

[Step-120]
Next, a p-type impurity is ion-implanted into a region of the first n-type semiconductor layer 21 where the N-type well 61 is not formed, and this region of the first n-type semiconductor layer 21 where the N-type well 61 is not formed is second. P-type semiconductor layer 32 (see FIG. 1C). Specifically, using the alignment mark provided in the first p-type semiconductor layer 31 as a reference, a resist layer 41 is provided on the first p-type semiconductor layer 31 based on a lithography technique, and an N-type well 61 is formed. A region of the first n-type semiconductor layer to be covered is covered with a resist layer 41. Thereafter, using the resist layer 41 as a mask, p-type impurities are ionized into the portion of the first n-type semiconductor layer 21 that is not located below the resist layer 41 through the exposed first p-type semiconductor layer 31. inject. Then, after ion implantation, the resist layer 41 is removed. The concentration of the p-type impurity may be selected so that the n-type impurity in the first n-type semiconductor layer 21 is compensated. The implantation energy may be determined so that the peak of the implanted p-type impurity concentration is located in or near the first n-type semiconductor layer 21. The conditions for ion implantation are illustrated in Table 2 below. With the alignment mark provided on the first p-type semiconductor layer 31 as a reference, the second n-type semiconductor layer 21 located below the first p-type semiconductor layer 31 is aligned with the second p with high alignment accuracy. A type semiconductor layer 32 can be provided. Further, since the so-called light boron having a small atomic weight is ion-implanted, even if the first p-type semiconductor layer 31 is thick, the first n-type semiconductor layer 21 can be reliably ion-implanted.

[Table 2]
Formation of second p-type semiconductor layer 32 Impurity: Boron dose: 1 × 10 ¹² to 1 × 10 ¹⁵ / cm ²
Injection energy: 2 MeV

[Step-130]
Next, an n-type impurity is ion-implanted into a portion of the first p-type semiconductor layer 31 located above the outer periphery of the region of the first n-type semiconductor layer 21 where the N-type well 61 is to be formed. An N-type well 61 including the first n-type semiconductor layer 21 and the second n-type semiconductor layer 22 extending upward from the outer periphery of the first n-type semiconductor layer 21 is obtained (see FIG. 2A). . At the same time, an n-type well 63 is formed by ion-implanting n-type impurities into the region of the first p-type semiconductor layer 31 where a P-channel FET is to be formed. Note that the second n-type semiconductor layer 22 also functions as an electrode extraction portion of the N-type well 61. Specifically, a resist layer 42 is provided on the first p-type semiconductor layer 31 based on the lithography technique with reference to the alignment mark provided on the first p-type semiconductor layer 31, and the second n-type semiconductor. The region of the first p-type semiconductor layer 31 where the layer 22 and the N-type well 63 are to be formed is exposed. Thereafter, n-type impurities are ion-implanted into the exposed portion of the first p-type semiconductor layer 31 using the resist layer 42 as a mask. Then, after ion implantation, the resist layer 42 is removed. The conditions for ion implantation are illustrated in Table 3 below. The dose amount and implantation energy may be determined from the electrical characteristics of the high-voltage P-channel FET.

[Table 3]
Formation of second n-type semiconductor layer 22 and N-type well 63 Impurity: phosphorus dose: 1 × 10 ¹² to 1 × 10 ¹³ / cm ²
Injection energy: 2 × 10 ² to 2 × 10 ³ KeV
.

[Step-140]
Thereafter, activation annealing is performed to activate the p-type impurity introduced in [Step-120] and [Step-130]. Thereafter, an element isolation region 51 having a LOCOS structure is formed by a known method. Then, after removing the oxide film formed on the surface of the active region surrounded by the element isolation region 51, the p-type semiconductor substrate 10 is thermally oxidized to form a sacrificial oxide film (not shown). Thus, the structure shown in FIG. 2B can be obtained.

[Step-150]
Thereafter, an N-channel FET (hereinafter sometimes referred to as a triple well / N-channel FET) is formed in the P-type well 62 formed of the region of the first p-type semiconductor layer 31 surrounded by the N-type well 61. . Further, the region of the first p-type semiconductor layer 31 located above the second p-type semiconductor layer 32 is defined as a second P-type well 64, and the second P-type well 64 has a second N-channel type. An FET is formed. Further, a P-channel FET is formed in the N-type well 63.

  Specifically, after removing the sacrificial oxide film, the surface of the P-type well 62 composed of the first p-type semiconductor layer 31, the N-type well 63, and the P-type well 64 composed of the first p-type semiconductor layer 31 is formed. Then, the gate insulating layers 71A, 71B, 71C are formed by a known method. Thereafter, gate electrodes 72A, 72B, 72C are formed by a well-known method to form an LDD structure (not shown). Next, source / drain regions 73A, 73B, and 73C are formed in the P-type well 62, the N-type well 63, and the P-type well 64, respectively. In this way, as shown in FIG. 2C, a triple well / N-channel FET can be obtained in the P-type well 62 composed of the first p-type semiconductor layer 31. In addition, a second N-channel FET can be obtained in the P-type well 64 composed of the first p-type semiconductor layer 31, and a P-channel FET can be obtained in the N-type well 63.

  In the method of manufacturing the field effect transistor according to the first embodiment, an alignment mark for lithography is formed on the surface of the first p-type semiconductor layer 31. Then, formation of the second p-type semiconductor layer 32 in [Step-120], formation of the second n-type semiconductor layer 22 in [Step-130], formation of the N-type well 63, and element in [Step-140] This alignment mark is used in the formation of the separation region 51. Thereby, alignment of these area | regions can be performed with high precision. Therefore, the margin for alignment between the triple well N-channel FET and other FETs is minimized. Therefore, the close-packed arrangement of each FET is possible, and a high degree of integration can be obtained. In addition, since the alignment mark is provided in the thick first p-type semiconductor layer 31, it is difficult to undergo a dimensional change or deformation of the alignment mark in a later process. Therefore, it is not necessary to form a special alignment mark corresponding to the epitaxial growth of the semiconductor layer, and the lithography positioning accuracy does not deteriorate.

  Further, the P-type well 64 of the high breakdown voltage N-channel FET or the low-voltage N-channel FET that is not a triple well FET does not go through the first n-type semiconductor layer 21 but goes through the second p-type semiconductor layer 32. It is connected to a p-type semiconductor substrate 10 made of a low-resistance p-type silicon semiconductor substrate. Therefore, not only can the ground electrode be provided on the back surface of the p-type semiconductor substrate 10, but also the well resistance that causes latch-up is reduced, and latch-up is unlikely to occur. In [Step-120], the p-type impurity for compensating the first n-type semiconductor layer 21 is ion-implanted at a high concentration, whereby the resistance of the P-type well 64 can be further reduced and latch-up is performed. Can be made more difficult to occur.

  Moreover, only the region of the first n-type semiconductor layer 21 where the N-type well 61 is not formed is ion-implanted with a p-type impurity such as boron that has a projection range larger than phosphorus and can be implanted deeper than phosphorus with the same acceleration voltage. Then, the second p-type semiconductor layer 32 is formed by carrier compensation. As a result, the second ion is selectively applied only to a necessary region from the first n-type semiconductor layer 21 located deeper than the conventional technique using a conventional ion implantation apparatus without relying on drive-in diffusion. The p-type semiconductor layer 32 can be formed.

  In addition, the P-type well 64 can be formed deeply, and a low sheet resistance of the P-type well 64 can be obtained. Thereby, the occurrence of latch-up is more effectively suppressed. Furthermore, by using a low-resistance p-type semiconductor substrate, the low-resistance p-type semiconductor substrate becomes a current path parallel to the P-type well 64, and a lower sheet resistance of the P-type well 64 is obtained. Thereby, the occurrence of latch-up is further suppressed.

  Furthermore, [Step-110] and [Step-120] and subsequent steps can be executed in another production line and another production factory, and the production cost of the FET can be reduced.

  In the method of manufacturing the field effect transistor according to the first embodiment, the first n-type semiconductor layer 21 is located at a deep position, and the n-type impurity concentration is higher or thicker. The type semiconductor layer 21 can be obtained. As a result, for example, a triple well N-channel FET having a breakdown voltage of 32 volts can be manufactured.

  The contents described above are basically the same in the second to fourth embodiments described below.

  In addition, since the first n-type semiconductor layer 21 is formed based on an epitaxial growth method that introduces in situ, the concentration and distribution shape of the first n-type semiconductor layer 21 can be freely set according to the impurity source gas flow rate, and It can be controlled independently. As a result, the thin first n-type semiconductor layer 21 can be formed at a high concentration which is difficult to obtain by ion implantation, and the first n-type semiconductor layer 21 having the optimum impurity distribution can be obtained at a low manufacturing cost. it can.

  The second embodiment is a modification of the first embodiment. Hereinafter, with reference to schematic partial sectional views of the semiconductor substrate and the like in FIGS. 3A and 3B and FIGS. 4A and 4B, a method for manufacturing the field effect transistor of Example 2 will be described below. Will be explained.

[Step-200]
First, the same steps as [Step-100] to [Step-120] of Example 1 are performed.

[Step-210]
Thereafter, the same step as [Step-130] of the first embodiment is performed, and the first p-type located above the outer peripheral portion of the region of the first n-type semiconductor layer 21 where the N-type well 61 is to be formed. An n-type impurity is ion-implanted into the semiconductor layer 31, and thus the first n-type semiconductor layer 21 and the second n-type semiconductor layer 22 extending upward from the outer periphery of the first n-type semiconductor layer 21. An N-type well 61 is obtained. At the same time, an n-type well 63 is formed by ion-implanting n-type impurities into the region of the first p-type semiconductor layer 31 where a P-channel FET is to be formed. Thus, the structure shown in FIG. 3A can be obtained.

[Step-220]
Next, a third p-type semiconductor layer 33 is formed on the entire surface, and then an n-type impurity is ion-implanted into a portion of the third p-type semiconductor layer 33 located above the second n-type semiconductor layer 22. Thus, the third n-type semiconductor layer 23 extending upward from the second n-type semiconductor layer 22 is obtained. Specifically, the third p-type semiconductor layer 33 is formed on the entire surface based on the epitaxial growth method in the same manner as in [Step-110] in Example 1 (see FIG. 3B). Next, a resist layer (not shown) is provided on the third p-type semiconductor layer 33 based on the lithography technique using the alignment mark provided on the first p-type semiconductor layer 31 as a reference, and a third n-type semiconductor layer 33 is formed. The region of the third p-type semiconductor layer 33 where the semiconductor layer 23 and the N-type well 63 are to be formed is exposed. Then, using the resist layer as a mask, the third n-type impurity is ion-implanted into the exposed portion of the third p-type semiconductor layer 33 in the same manner as in [Step-130] of the first embodiment. After obtaining the semiconductor layer 23 and the fourth n-type semiconductor layer 24, the resist layer is removed (see FIG. 4A). Note that this process may be repeated two or more times. Then, after performing activation annealing, an element isolation region 51 having a LOCOS structure is formed. Thereafter, the oxide film formed on the surface of the active region surrounded by the element isolation region 51 is removed, and the p-type semiconductor substrate is thermally oxidized to form a sacrificial oxide film (not shown). In this way, the structure shown in FIG. 4B can be obtained. If the thickness of the third p-type semiconductor layer 33 is reduced, the deformation of the alignment mark provided in the first p-type semiconductor layer 31 is slight and no problem occurs.

[Step-230]
Thereafter, in the same manner as in [Step-150] of the first embodiment, the first n-type semiconductor layer 21 and the second n extending upward from the outer peripheral portion of the first n-type semiconductor layer 21 by a well-known method. Triple-well N-channel FET in the region of the first p-type semiconductor layer 31 and the third p-type semiconductor layer 33 surrounded by the N-type well 61 composed of the n-type semiconductor layer 22 and the third n-type semiconductor layer 23 Form. In addition, the second p-type well 64 is used as a region of the first p-type semiconductor layer 31 and the third p-type semiconductor layer 33 located above the second p-type semiconductor layer 32, and the second n-channel FET is formed. Form. Further, a P-channel FET is formed in the N-type well 63 including the fourth n-type semiconductor layer 24.

  Example 3 relates to a method of manufacturing a field effect transistor according to the second aspect of the present invention. Hereinafter, with reference to schematic partial sectional views of the semiconductor substrate and the like of FIGS. 5A to 5C and FIGS. 6A to 6C, a method for manufacturing the field effect transistor of Example 3 will be described below. Will be explained.

[Step-300]
First, an n-type impurity is ion-implanted into a p-type semiconductor substrate 10 composed of a low-resistance p-type silicon semiconductor substrate (electric resistivity is, for example, 0.01 Ω · cm) having a plane orientation (100), and then a p-type semiconductor substrate. A p-type semiconductor layer (electric resistivity: 10 Ω · cm) is formed thereon. Thus, a stacked structure of the p-type semiconductor substrate 10, the first n-type semiconductor layer 121, and the first p-type semiconductor layer can be obtained. Thereafter, an alignment mark (not shown) is provided on the first p-type semiconductor layer 131. FIG. 5A shows a schematic partial cross-sectional view of a p-type semiconductor substrate and the like in a state where n-type impurities are ion-implanted inside the p-type semiconductor substrate 10. Here, the portion of the p-type semiconductor substrate on the first n-type semiconductor layer 121 is indicated by a p-type semiconductor layer 10A. FIG. 5B shows a schematic partial cross-sectional view of the p-type semiconductor substrate and the like after the p-type semiconductor layer is formed on the p-type semiconductor substrate. Here, the p-type semiconductor layer 10A and the p-type semiconductor layer formed by the epitaxial growth method on the p-type semiconductor substrate in the same manner as in [Step-110] in Example 1 are combined to form the first p-type semiconductor layer. It is represented as 131. The conditions for ion implantation are illustrated in Table 4 below.

[Table 4]
Formation of first n-type semiconductor layer 121 Impurity: Phosphorous dose: 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ²
Injection energy: 2 MeV

  Alternatively, after a p-type semiconductor layer (electric resistivity: 10 Ω · cm) is formed on the p-type semiconductor substrate 10 by an epitaxial growth method, an n-type impurity is ion-implanted into the p-type semiconductor layer. Then, a first n-type semiconductor layer may be formed, and a p-type semiconductor layer (electric resistivity: 10 Ω · cm) may be formed on the p-type semiconductor layer by an epitaxial growth method. According to such a method, a stacked structure of the p-type semiconductor substrate 10, the p-type semiconductor layer, the first n-type semiconductor layer, the p-type semiconductor layer, and the p-type semiconductor layer is obtained. Note that the two p-type semiconductor layers on the first n-type semiconductor layer may be regarded as the first p-type semiconductor layer.

[Step-310]
Thereafter, in the same manner as in [Step-120] in Example 1, p-type impurities are ion-implanted into the region of the first n-type semiconductor layer 121 where the N-type well 61 is not formed, and the N-type well 61 is not formed. This region of the first n-type semiconductor layer 121 is referred to as a second p-type semiconductor layer 132 (see FIG. 5C).

[Step-320]
Next, in the same manner as in [Step-130] in Example 1, the first p-type semiconductor layer located above the outer periphery of the region of the first n-type semiconductor layer 121 where the N-type well 61 is to be formed. An n-type impurity is ion-implanted into a portion 131, and thus includes a first n-type semiconductor layer 121 and a second n-type semiconductor layer 122 extending upward from the outer periphery of the first n-type semiconductor layer 121. An N-type well 61 is obtained (see FIG. 6A). At the same time, an n-type well 63 is formed by ion-implanting an n-type impurity in the region of the first p-type semiconductor layer 131 where a P-channel FET is to be formed. Note that the second n-type semiconductor layer 122 also functions as an electrode extraction portion of the N-type well 61.

[Step-330]
Thereafter, activation annealing is performed to activate the p-type impurity introduced in [Step-310] and [Step-320]. Thereafter, an element isolation region 51 having a LOCOS structure is formed by a known method. Then, after removing the oxide film formed on the surface of the active region surrounded by the element isolation region 51, the p-type semiconductor substrate is thermally oxidized to form a sacrificial oxide film (not shown). Thus, the structure shown in FIG. 6B can be obtained.

[Step-340]
Thereafter, in the same manner as in [Step-150] in the first embodiment, a triple well / N-channel FET is formed in the P-type well 62 including the region of the first p-type semiconductor layer 131 surrounded by the N-type well 61. To do. Further, the region of the first p-type semiconductor layer 131 located above the second p-type semiconductor layer 132 is defined as a second P-type well 64, and the second P-type well 64 has a second N-channel type. An FET is formed. Further, a P-channel FET is formed in the N-type well 63. Thus, the structure shown in FIG. 6C can be obtained.

  In Example 3, the first n-type semiconductor layer 121 may be formed in a shallow region from the surface of the p-type semiconductor substrate 10 in [Step-300]. The density and distribution shape can be controlled with a relatively high degree of freedom. As a result, the first n-type semiconductor layer 121 having an optimum impurity distribution can be obtained. Further, the first n-type semiconductor layer 121 is once formed inside the p-type semiconductor substrate 10 and then a p-type semiconductor layer formed by an epitaxial growth method is formed. Here, it is not necessary to form alignment marks before epitaxial growth. Therefore, the alignment mark is not deformed by epitaxial growth, and deterioration of alignment accuracy in the subsequent process can be avoided, so that the degree of integration can be increased. Alternatively, it is possible to eliminate measures for deformation / disappearance of the alignment mark (such as forming the alignment mark with a very deep and enormous size, or re-forming the alignment mark after epitaxial growth), so that the manufacturing cost can be reduced. The first n-type semiconductor layer 121 may be formed in a relatively deep region from the surface of the p-type semiconductor substrate 10. As a result, the first p-type semiconductor layer 131 having the same thickness can be obtained by the epitaxial growth method of the p-type semiconductor layer having a smaller thickness, so that the time required for the epitaxial growth can be shortened and the manufacturing cost can be reduced. Can do. Further, when forming the alignment mark before the epitaxial growth, the p-type semiconductor layer having a smaller thickness may be formed by the epitaxial growth method, so that the deformation of the alignment mark can be reduced. As a result, it is possible to reduce the deterioration of alignment accuracy in the subsequent process due to the deformation of the alignment mark by epitaxial growth, and to reduce the degree of integration. Alternatively, since it is possible to omit measures for deformation / disappearance of the alignment mark, the manufacturing cost can be reduced.

  Furthermore, even in the third embodiment, [Step-300] and [Step-310] can be executed in different manufacturing lines and different manufacturing plants, thereby reducing the manufacturing cost of the FET. Can do.

  The fourth embodiment is a modification of the third embodiment. Hereinafter, with reference to schematic partial cross-sectional views of the semiconductor substrate and the like of FIGS. 7A and 7B and FIGS. 8A and 8B, a method of manufacturing a field effect transistor of Example 4 will be described below. Will be explained.

[Step-400]
First, the same steps as [Step-300] to [Step-310] of Example 3 are performed.

[Step-410]
Thereafter, the same step as [Step-320] in Example 3 is performed, and the first p-type located above the outer periphery of the region of the first n-type semiconductor layer 121 where the N-type well 61 is to be formed. An n-type impurity is ion-implanted into the semiconductor layer 131, whereby the first n-type semiconductor layer 121 and the second n-type semiconductor layer 122 extending upward from the outer periphery of the first n-type semiconductor layer 121. An N-type well 61 is obtained. At the same time, an n-type well 63 is formed by ion-implanting an n-type impurity in the region of the first p-type semiconductor layer 131 where a P-channel FET is to be formed. In this way, the structure shown in FIG. 7A can be obtained.

[Step-420]
Next, in the same manner as in [Step-220] in Example 2, a third p-type semiconductor layer 133 is formed on the entire surface, and then a third p-type layer located above the second n-type semiconductor layer 122 is formed. An n-type impurity is ion-implanted into the type semiconductor layer 133, thereby obtaining a third n-type semiconductor layer 123 extending upward from the second n-type semiconductor layer 122. Specifically, the third p-type semiconductor layer 133 is formed on the entire surface based on the epitaxial growth method in the same manner as in [Step-110] of Example 1 (see FIG. 7B). Next, using the alignment mark provided in the first p-type semiconductor layer 131 as a reference, a resist layer (not shown) is provided on the third p-type semiconductor layer 133 based on the lithography technique, and the third n-type semiconductor layer 131 is provided. The region of the third p-type semiconductor layer 133 where the semiconductor layer 123 and the N-type well 63 are to be formed is exposed. Then, using the resist layer as a mask, the third n-type impurity is ion-implanted into the exposed portion of the third p-type semiconductor layer 133 in the same manner as in [Step-140] of the first embodiment. After obtaining the semiconductor layer 123 and the fourth n-type semiconductor layer 124, the resist layer is removed (see FIG. 8A). Note that this process may be repeated two or more times. Then, after performing activation annealing, an element isolation region 51 having a LOCOS structure is formed. Thereafter, the oxide film formed on the surface of the active region surrounded by the element isolation region 51 is removed, and the p-type semiconductor substrate is thermally oxidized to form a sacrificial oxide film (not shown). Thus, the structure shown in FIG. 8B can be obtained. If the thickness of the third p-type semiconductor layer 133 is reduced, deformation of the alignment mark provided in the first p-type semiconductor layer 131 is slight and no problem occurs.

[Step-430]
Thereafter, in the same manner as in [Step-230] of the second embodiment, the first n-type semiconductor layer 121 and the second n extending upward from the outer peripheral portion of the first n-type semiconductor layer 121 by a well-known method. Triple well N-channel FET in the region of the first p-type semiconductor layer 131 and the third p-type semiconductor layer 133 surrounded by the N-type well 61 composed of the n-type semiconductor layer 122 and the third n-type semiconductor layer 123 Form. Further, the second p-type well 64 is used as the first p-type semiconductor layer 131 and the third p-type semiconductor layer 133 located above the second p-type semiconductor layer 132. Form. Further, a P-channel FET is formed in the N-type well 63 including the fourth n-type semiconductor layer 124.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. Various manufacturing conditions, materials used, and the like in the method for manufacturing a field effect transistor described in the examples are examples, and can be appropriately changed. The configuration and structure of the field effect transistor are also examples, and can be changed as appropriate.

1A to 1C are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field-effect transistor of Example 1. FIG. 2A to 2C are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 1 following FIG. 1C. 3A and 3B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 2. FIG. 4A and 4B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field-effect transistor of Example 2 following FIG. 3B. 5A to 5C are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 3. FIG. 6A to 6C are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 3 following FIG. 5C. 7A and 7B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 4. FIG. 8A and 8B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the method for manufacturing the field effect transistor of Example 4 following FIG. 7B. FIG. 9 is a conceptual diagram showing an example of a cross-sectional structure of a conventional integrated circuit. FIGS. 10A to 10D are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the outline of the manufacturing method disclosed in JP-A-2004-193452.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Buffer layer, 21, 121 ... 1st n-type semiconductor layer, 22, 122 ... 2nd n-type semiconductor layer, 23, 123 ... 3rd N-type semiconductor layer, 24, 124 ... fourth n-type semiconductor layer, 31, 131 ... first p-type semiconductor layer, 32, 132 ... second p-type semiconductor layer, 33, 133 ... third p-type semiconductor layer, 41 ... resist layer, 42 ... resist layer, 51 ... element isolation region, 61, 63 ... N-type well, 62, 64 ... P-type well, 71A, 71B, 71C ... gate insulating layer, 72A, 72B, 72C ... gate electrode, 73A, 73B, 73C ... source / drain region

Claims (9)

(A) forming a first n-type semiconductor layer on the surface of a p-type semiconductor substrate;
(B) forming a first p-type semiconductor layer on the first n-type semiconductor layer based on an epitaxial growth method;
(C) P-type impurities are ion-implanted into a region of the first n-type semiconductor layer that does not form an N-type well, and this region is used as a second p-type semiconductor layer.
(D) An n-type impurity is ion-implanted into a portion of the first p-type semiconductor layer located above the outer periphery of the region of the first n-type semiconductor layer in which the N-type well is to be formed. After obtaining an N-type well composed of an n-type semiconductor layer and a second n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer,
(E) forming an N-channel field effect transistor in a P-type well composed of a region of the first p-type semiconductor layer surrounded by the N-type well;
A manufacturing method of a field effect transistor comprising each step. In the step (D), an n-type impurity is ion-implanted into a region of the first p-type semiconductor layer where a P-channel field effect transistor is to be formed, thereby forming an N-type well.
The field effect transistor according to claim 1, further comprising a step of forming a P-channel field effect transistor in the N-type well between the steps (D) and (E) or after the step (E). Manufacturing method.   A region of the first p-type semiconductor layer located above the second p-type semiconductor layer between the steps (D) and (E) or after the step (E) is defined as a second P. 2. The method of manufacturing a field effect transistor according to claim 1, comprising a step of forming a second N-channel field effect transistor as a type well. Between the steps (D) and (E), a third p-type semiconductor layer is formed on the entire surface, and then a portion of the third p-type semiconductor layer located above the second n-type semiconductor layer An n-type impurity is ion-implanted into the first n-type semiconductor layer, thereby performing a step of obtaining a third n-type semiconductor layer extending upward from the second n-type semiconductor layer;
In the step (E), the first n-type semiconductor layer and the N-type composed of the second n-type semiconductor layer and the third n-type semiconductor layer extending upward from the outer peripheral portion of the first n-type semiconductor layer. 2. The method of manufacturing a field effect transistor according to claim 1, wherein an N-channel field effect transistor is formed in a region of the first p-type semiconductor layer and the third p-type semiconductor layer surrounded by the well.   The method of manufacturing a field effect transistor according to claim 1, wherein in the step (A), a first n-type semiconductor layer is formed on the surface of the p-type semiconductor substrate by an epitaxial growth method. (A) After ion-implanting n-type impurities into the p-type semiconductor substrate, a p-type semiconductor layer is formed on the p-type semiconductor substrate, whereby the p-type semiconductor substrate, the first n-type semiconductor layer, the first After obtaining the laminated structure of 1 p-type semiconductor layer,
(B) P-type impurities are ion-implanted into a region of the first n-type semiconductor layer where the N-type well is not formed, and the region is used as a second p-type semiconductor layer.
(C) An n-type impurity is ion-implanted into a portion of the first p-type semiconductor layer located above the outer periphery of the region of the first n-type semiconductor layer in which the N-type well is to be formed. After obtaining an N-type well composed of an n-type semiconductor layer and a second n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer,
(D) forming an N-channel field effect transistor in a P-type well composed of a region of the first p-type semiconductor layer surrounded by the N-type well;
A manufacturing method of a field effect transistor comprising each step. In the step (C), an n-type impurity is ion-implanted into a region of the first p-type semiconductor layer where a P-channel field effect transistor is to be formed, thereby forming an N-type well.
The field effect transistor according to claim 6, further comprising a step of forming a P-channel field effect transistor in the N-type well between the steps (C) and (D) or after the step (D). Manufacturing method.   A region of the first p-type semiconductor layer located above the second p-type semiconductor layer is formed between the steps (C) and (D) or after the step (D). The method of manufacturing a field effect transistor according to claim 6, further comprising forming a second N-channel field effect transistor as a type well. Between the steps (C) and (D), a third p-type semiconductor layer is formed on the entire surface, and then a portion of the third p-type semiconductor layer located above the second n-type semiconductor layer An n-type impurity is ion-implanted into the first n-type semiconductor layer, thereby performing a step of obtaining a third n-type semiconductor layer extending upward from the second n-type semiconductor layer;
In the step (D), the first n-type semiconductor layer and the N-type composed of the second n-type semiconductor layer and the third n-type semiconductor layer extending upward from the outer periphery of the first n-type semiconductor layer. 7. The method of manufacturing a field effect transistor according to claim 6, wherein an N channel field effect transistor is formed in a region of the first p-type semiconductor layer and the third p-type semiconductor layer surrounded by the well.

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