JP2010134592A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate the operation of a programmable controller. <P>SOLUTION: The programmable controller includes a ladder program storage memory 5 for storing program instructions configuring a ladder program; and a program execution CPU 3 for sequence-controlling a control object according to the program instructions. This programmable controller is provided with a hardware CPU 8a for generating hardware program instructions from the program instructions on software, and the program execution CPU 3 transfers data to be controlled to the hardware CPU 8a. The hardware CPU 8a performs the logical arithmetic operation of the data according to the hardware program instructions, and transfers the arithmetic results to the program execution CPU 3. The programmable execution CPU 3 controls the control object according to the arithmetic results. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a programmable controller (PLC) used for control of a machine tool or the like, and particularly relates to speeding up the control operation.

  A programmable controller is used as a control device for factory automation (FA) installed in a production factory or the like. This programmable controller is composed of a plurality of units. Examples of the plurality of units include a power supply unit, a CPU unit, an input unit, an output unit, a communication unit, and other high-functional units. The CPU unit includes a CPU, an I / O memory, a program memory, and the like. The CPU performs an IN refresh process for fetching a signal input from the input unit into the I / O memory, and performs sequence control in the program memory. Executes an operation based on the ladder program, writes the result of the operation to the I / O memory and sends it to the output unit, then performs an OUT refresh process, and then transmits and receives data to and from other PLCs on the communication network Or a series of processing for performing peripheral processing such as data transmission / reception with an external personal computer or the like via a communication port provided in the CPU unit is repeated. A sensor or the like is connected to the input unit, and an actuator or the like is connected to the output unit. The sensor or the like senses the state of the machine or equipment in the factory, and inputs the information to the input unit, and the actuator or the like drives the machine or equipment in the factory in response to the output from the output unit.

  Such a programmable controller sequentially reads and analyzes a list of instructions (program instructions) of a ladder program, which is a user program in the programmable controller, and executes an operation based on the result. The program instructions are roughly classified into basic instructions such as contact instructions and application instructions such as numerical operations. In the ladder program, the appearance ratio of basic instructions is high, and processing this operation at high speed leads to the realization of the overall high-speed operation. This is because the basic instruction is simple in arithmetic processing but has a high appearance ratio, and the application instruction is more complicated in arithmetic processing than the basic instruction but has a low appearance ratio, so it has excellent cost performance. The allocation of basic instructions and application instructions is closely related to the price of the product and is determined by the degree of integration of the sequence CPU. If a higher-integration LSI for sequence calculation is used, the price will increase, but many instructions can be processed by the sequence CPU, and the calculation performance can be improved.

By the way, in the above, in the execution of the ladder program, the speed is increased at the basic instruction, and the speed is decreased at the applied instruction, but in recent years, the demand for higher speed of the entire operation has increased in the programmable controller. It is coming. However, since the existing programmable controller depends on the processing capability of the built-in CPU, there is a limit to increasing the speed of the programmable controller when the processing capability of the CPU is low. Prior patent documents of the programmable controller will be described below.
JP 2004-334429 A

  In the present invention, a program instruction is handled without distinguishing between a basic instruction and an application instruction, so that the processing speed of the entire program is increased and the operation speed of the programmable controller is increased.

  A programmable controller according to the present invention is a programmable controller comprising a program memory in which a plurality of program instructions constituting a ladder program are stored, and a program execution CPU that performs sequence control on a controlled object in accordance with the program instructions. It has a hardware-ized CPU for hardwareizing program instructions constituting the program and a hardware-based program instruction storage unit for storing the hardwareized program instructions, and the program execution CPU is controlled by the hardware-based CPU. The target data is passed, and the hardware CPU performs a logical operation on the data by the hardware program instruction, and passes the operation result to the program execution CPU. The program execution CPU performs control according to the passed operation result. It is characterized in that to control the elephants.

  According to the present invention, since the ladder program is operated and executed not by software but by hardware program instructions, the speed of the programmable controller can be increased.

  Hereinafter, a programmable controller according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  Referring to FIG. 1, this programmable controller includes a CPU module 1 and a plurality of I / O modules 2. The CPU module 1 executes a sequence program, and controls a program execution CPU 3, a system program storage memory 4, a ladder program storage memory 5, a data memory 6, a bus interface 7, and a ladder processor 8. With. 9 indicates a bus and 10 indicates an I / O device. The system program storage memory 4 stores a system program necessary for system control. The ladder program storage memory 5 stores a ladder program. The data memory 6 has a work area used by the program execution CPU 3 for work, an I / O storage area for storing an input / output status for the I / O device 10 when a program command is executed, and other areas. The bus interface 7 interfaces the CPU module 1 and the I / O module 2.

  The ladder processor 8 includes a hardware CPU 8a for hardwareizing program instructions constituting the ladder program, and hardware software for storing software for making the ladder program in the ladder program storage memory 5 hardware. It has a storage memory 8b and a hardware program instruction storage unit 8c for storing program instructions that are hardwareized by the hardware CPU 8a.

  In the programmable controller of the embodiment having the above-described configuration, the following operation is performed.

  First, the program execution CPU 3 inputs a ladder program to the hardware CPU 8 a in the ladder processor 8. The ladder program sent from the program execution CPU 3 is composed of a large number of program instructions. The program instructions include basic instructions (sequence instructions), OUT instructions, application instructions, END instructions, and application instructions include OR instructions, AND instructions, MOVE instructions, and the like. As shown in FIG. 2, in step 1, contact instruction X0 (LD instruction), contact instruction X1 (OR instruction), contact instruction X2 (AND instruction), output instruction Y0 (OUT instruction) connected to the bus line of the ladder program After processing, in step 2, the next contact command X3 (LD command), contact command X4 (AND command), contact command Y1 (OUT command) connected to the bus is executed, and in step n, contact command Xn (LD command) and contact command Yn (OUT command) are executed, the END command (not shown) at the end of the ladder program is executed, and the process returns to the contact command X0 (LD command) again. Repeatedly (scan process).

  The hardware CPU 8a in the ladder processor 8 converts the ladder program shown in FIG. 2 inputted from the program execution CPU 3 by the software in the hardware software storage memory 8b, for example, steps n1 and n2 as shown in FIG. ,... Are converted into hardware logical block groups H1, H2,..., Hn. In this way, a hardware-programmed program instruction 8c is generated by hardwareizing each step of the ladder program. This hardware-implemented program instruction 8c is a hardware-implemented program instruction of each step constituting the ladder program.

  Next, the program execution CPU 3 passes the data from the I / O device 10 to be controlled received via the I / O module 2 to the ladder processor 8. The ladder processor 8 causes the internal hardware CPU 8a to execute the data in accordance with the corresponding hardware program instruction in the storage unit 8c, and then passes the operation result to the program execution CPU 3. In this manner, in the embodiment, the ladder program is operated and executed by the hardware program instruction instead of software, so that the speed of the programmable controller can be increased.

FIG. 1 is a diagram showing a configuration of a programmable controller according to an embodiment of the present invention. FIG. 2 is a ladder diagram. FIG. 3 is a diagram showing the hardwareized program instructions of the programmable controller related to the method according to the embodiment of the present invention.

Explanation of symbols

1 CPU module 2 I / O module 3 Program execution CPU
4 System program storage memory 5 Ladder program storage memory 6 Data memory 7 Bus interface 8 Ladder processor 8a Hardware CPU
8b Hardware software storage memory 8c Hardware program instruction storage

Claims (1)

A programmable controller comprising a program memory in which a plurality of program instructions constituting a ladder program are stored, and a program execution CPU that performs sequence control of a controlled object in accordance with the program instructions,
A hardwareized CPU for hardwareizing program instructions constituting a ladder program;
A hardwareized program instruction storage unit for storing hardwareized program instructions;
And having
The program execution CPU passes data to be controlled to the hardware CPU,
The hardware CPU performs a logical operation on the data according to the hardware program instruction in the storage unit, and passes the operation result to the program execution CPU.
A programmable controller, wherein the program execution CPU controls a control target in accordance with a passed calculation result.

Images