JP2010133830A - Method of evaluating solder junction state, and chip component for evaluating solder junction state - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of evaluating a solder junction state and to provide chip components for evaluating a solder junction state capable of three-dimensionally recognizing a crack shape, or the like of a solder junction section by accurately grasping and determining the amount of polishing of a specimen and parallelism of a polishing section, improving reliability in observation of the section, and performing observation by setting a plurality of target sections to one observation target. <P>SOLUTION: When observing a junction state of a solder junction section 12, the chip components 11 for evaluation a solder junction state and the solder junction section 12 are polished on a plane A nearly vertical to a first reference line 21. By measuring interval widths b1, b2 between the first reference line 21 and first lines 22, 23 for adjusting the amount of polishing and interval widths b3, b4 between a second reference line 31 and second lines 32, 33 for adjusting the amount of polishing on a section of the chip components 11 for evaluating a solder junction state, parallelism of the section of the chip components 11 for evaluating a solder junction state is confirmed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solder joint state evaluation method and a chip component for solder joint state evaluation, and more particularly to a technique for improving reliability in joint state evaluation by solder joint.

  Conventionally, in a test for evaluating the reliability of a solder joint portion with respect to a printed circuit board such as an electronic control component, for example, a test product including the solder joint portion is subjected to cross-section cutting after a thermal reliability test and polished, and the presence or absence of cracks and the shape A method of evaluating the solder joint state by observing the degree of deterioration such as the above is used (for example, Patent Document 1).

Below, the evaluation method of the soldering state which concerns on a prior art is demonstrated using FIGS. 4-6.
FIG. 4A is a perspective view showing a substrate according to the prior art, and FIG. 4B is a perspective view showing a test product including a solder joint portion according to the prior art. FIG. 5A is a perspective view showing a state in which a test product according to the prior art is sealed in a resin, and FIG. 5B is a perspective view showing a state in which the test product according to the prior art is similarly polished with a polishing disc. FIG. 6A is a plan view showing a chip part for evaluating the solder joint state according to the prior art, and FIG. 6B is a cross-sectional view of the chip part for evaluating the solder joint state in the polished cross section of FIG.

In the test for evaluating the soldered state, first, as shown in FIGS. 4A and 4B, various chip components are soldered to lands on the substrate. Specifically, for example, when the parts to be joined are rectangular parallelepiped chip parts as shown in FIG. 4B, the planes exposed on the surface of the rectangular parallelepiped chip parts are positioned parallel to each other and perpendicular to the substrate. Each of the two planes is soldered to the substrate as a solder joint surface.
Then, after performing the cooling reliability test, as shown in FIG. 4B, the rectangular parallelepiped chip component to be subjected to reliability evaluation is cut out as a test product including a solder joint portion with the substrate.

  And as shown to Fig.5 (a), the said test article is enclosed so that the said solder joint surface may become perpendicular to the bottom face of the said cylindrical resin with respect to transparent resin formed in a cylindrical shape, Fix it so that polishing and cross-sectional observation are easy. Further, the cylindrical resin in which the test product is sealed is pressed against the polishing machine rotating in the direction of arrow γ in FIG. 5B while applying a predetermined pressure in the direction of arrow δ. Thus, the test product is polished. That is, the solder joint portion that joins the rectangular parallelepiped chip component and the substrate and the rectangular parallelepiped chip component are simultaneously polished to observe the joining state of the solder joint portion.

When polishing as described above, as shown in FIG. 6 (a), a target cross section to be observed is set at a substantially central portion in the pressurizing direction δ of the test article, and the target cross section is polished. In this solder joint portion, the presence or absence of cracks as shown in FIG.
JP 2003-240770 A

However, in the prior art, since the polishing operation is performed manually, a large part relies on the operator's intuition and knack, and the operator accurately grasps the polishing amount and the parallelism of the polishing section during the polishing operation. It was difficult to do. For this reason, as shown by the dotted line in FIG. 6A, the actual polished cross section may deviate from the target cross section, and the reliability in observation of the cross section may be lowered.
In addition, this makes it difficult to three-dimensionally recognize the shape of a crack in a solder joint portion by performing observation by setting a plurality of target cross sections for one observation target.

  Therefore, in the present invention, in view of the above situation, when polishing a test article including a solder joint portion, an operator can accurately grasp and judge the polishing amount and the parallelism of the polishing section during the polishing operation. In addition, the reliability of cross-section observation can be improved, and by setting multiple target cross-sections for one observation target, the shape of cracks in solder joints can be recognized in three dimensions. A solder joint state evaluation method and a chip part for solder joint state evaluation that can be provided are provided.

  The problems to be solved by the present invention are as described above. Next, means for solving the problems will be described.

  That is, in claim 1, among the planes exposed on the surface of the rectangular parallelepiped chip component, each of the two planes positioned parallel to each other and perpendicular to the substrate is soldered to the substrate as a solder bonding surface. Solder joint evaluation method for observing the joint state of the solder joint part by simultaneously polishing the solder joint part joining the rectangular chip part and the substrate and the rectangular chip part in the joint state And among the planes exposed on the surface of the rectangular parallelepiped chip component, the midpoints of the two sides perpendicular to the solder joint surfaces are connected to the first plane orthogonal to the two solder joint surfaces. The first reference line is formed in advance, and the one side in the first plane from the midpoint of one side perpendicular to the solder joint surface of the first plane Two first polishing amount adjustment lines are formed in advance so as to be symmetrical with each other about the first reference line as a symmetry axis toward the other side facing each other, and the surface of the rectangular chip component Among the planes exposed to the second plane located parallel to the first plane, so that the first reference line and the two first polishing amount adjustment lines are parallel, When the second reference line and the two second polishing amount adjustment lines are formed in advance and the joining state of the solder joint portion is observed, the rectangular parallelepiped chip component, the solder joint portion, Between the first reference line and the first polishing amount adjustment line in the cross section of the rectangular parallelepiped chip component. And the second The quasi-line with the second polishing amount adjusting line spacing of the respective end points, by measuring, confirms the parallelism of the cross-section of the rectangular parallelepiped chip component.

  According to a second aspect of the present invention, the first plane is a plane located on the opposite side of the rectangular chip component from the substrate side.

  According to a third aspect of the present invention, the first reference line, the two first polishing amount adjustment lines, the second reference line, and the two second polishing amount adjustment lines are formed by silk printing or a laser marker. It is formed by processing by.

  According to a fourth aspect of the present invention, each of the two planes positioned parallel to each other and perpendicular to the substrate is soldered to the substrate as a solder joint surface and polished simultaneously with the solder joint portion to be joined to the substrate. A solder joint state evaluation chip component having a rectangular parallelepiped shape in which the joint state of the solder joint portion is observed, and the two solder joint surfaces among the planes exposed on the surface of the solder joint state evaluation chip component A first reference line parallel to the solder joint surface is formed, connecting the midpoints of the two sides perpendicular to the solder joint surface to the first plane perpendicular to the solder joint surface. From the midpoint of one side perpendicular to the solder joint surface of the first plane to the other side opposite to the one side in the first plane, the first reference line as the symmetry axis is used as a symmetry axis. Of the planes exposed to the surface of the rectangular parallelepiped chip component, two second planes that are positioned in parallel with the first plane are formed so as to be line symmetric. The second reference line and the two second polishing amount adjustment lines are respectively parallel to the first reference line and the two first polishing amount adjustment lines. The first reference line and the first polishing amount adjustment in the cross-section of the chip part for evaluating the solder joint state are formed and polished together with the solder joint portion and in a plane substantially perpendicular to the first reference line. For measuring the solder joint state by measuring the distance between the respective end points with the work line and the distance between the respective end points between the second reference line and the second polishing amount adjusting line. The parallelism of the cross-section of the chip component It is intended to be sure.

  According to a fifth aspect of the present invention, the first plane is a plane located on the opposite side of the rectangular chip component from the substrate side.

  7. The first reference line, the two first polishing amount adjustment lines, the second reference line, and the two second polishing amount adjustment lines are silk-printed or laser markers. It is formed by processing by.

  As effects of the present invention, the following effects can be obtained.

  According to the present invention, when polishing a specimen including a solder joint portion, an operator can accurately grasp and judge the amount of polishing and the parallelism of a polished cross section during the polishing operation, and the reliability in observation of the cross section can be determined. Can be improved. In addition, by setting a plurality of target cross sections for one observation target and performing observation, it is possible to three-dimensionally recognize the shape of a crack in the solder joint portion.

Next, embodiments of the invention will be described.
FIG. 1A is a plan view showing a chip part for evaluating the solder joint state according to the present invention, and FIG. 1B is an AA line (FIG. 1C) of FIG. (A′-A ′ line) cross-sectional view, (c) is a bottom view showing the solder joint state evaluation chip component.
FIG. 2 is a plan view showing a solder joint state evaluation chip component according to the present invention and a cross-sectional view in each cross section.
FIG. 3A is a front view showing a chip part for evaluating the solder joint state according to another embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line HH in FIG. FIG.
FIG. 4A is a perspective view showing a substrate according to the prior art, and FIG. 4B is a perspective view showing a test product including a solder joint portion according to the prior art.
FIG. 5A is a perspective view showing a state in which a test product according to the prior art is sealed in a resin, and FIG. 5B is a perspective view showing a state in which the test product according to the prior art is similarly polished with a polishing disc.
FIG. 6A is a plan view showing a chip part for evaluating the solder joint state according to the prior art, and FIG. 6B is a cross-sectional view of the chip part for evaluating the solder joint state in the polished cross section of FIG.
It should be noted that the technical scope of the present invention is not limited to the following embodiments, and is widely applied to the entire scope of technical ideas that the present invention truly intends, as will be apparent from the matters described in the present specification and drawings. It extends.

  The solder joint state evaluation method and the solder joint state evaluation chip component according to the present invention will be described below.

  First, a method for evaluating a solder joint state according to the present invention will be described with reference to FIGS. In this specification, for convenience of explanation, the lower side in FIG. 1A is the front side, the upper side is the rear side, and the right side is the right side and the left side is the left side. Similarly, the front side of the sheet of FIG. 1A will be described as the upper side and the back side of the sheet will be described as the lower side.

  The solder joint state evaluation method according to the present invention has the same basic configuration as the conventional evaluation method shown in FIGS. That is, as shown in FIGS. 1A, 1B and 1C, among the planes exposed on the surface of the solder joint state evaluation chip component 11 which is a rectangular parallelepiped chip component, the substrates are parallel to each other and not shown. Each of the two planes positioned perpendicular to each other is solder-bonded to the lands 13 and 13 disposed on the surface of the substrate as the solder-bonding surfaces 11c and 11d. The target solder joint state evaluation chip component 11 is cut out as a test product including solder joint portions 12 and 12 with the substrate.

Then, the test product is sealed in a transparent resin formed in a cylindrical shape so that the solder joint surface is perpendicular to the bottom surface of the cylindrical resin, and is fixed so that polishing and cross-sectional observation are easy. Turn into. Thereafter, the cylindrical specimen resin in which the specimen is sealed is pressed against the rotating polishing disc while manually applying a predetermined pressure to polish the specimen.
Specifically, the solder joint state evaluation chip part 11 and the solder joint state parts 12 and 12 for joining the solder joint state evaluation chip part 11 and the substrate are simultaneously polished to obtain the solder joint part 12. 12 bonding states are observed to observe the presence or absence of cracks and the degree of deterioration such as shape.

Furthermore, in the solder joint state evaluation method according to the present embodiment, among the planes exposed on the surface of the solder joint state evaluation chip component 11, the board surface is orthogonal to the two solder joint surfaces 11c and 11d. Is parallel to the upper surface 11a, which is the surface opposite to the substrate side of the chip component 11 for evaluating the solder joint state, and is perpendicular to the solder joint surfaces 11c and 11d on the upper surface 11a. A first reference line 21 connecting the midpoints 20 and 20 of the sides is formed in advance.
Further, the first reference line is formed on the upper surface 11a from a midpoint 20 on one side of the upper surface 11a perpendicular to the solder joint surfaces 11c and 11d toward the other side of the upper surface 11a facing the one side. Two first polishing amount adjusting lines 22 and 23 are formed in advance so as to be symmetrical with respect to each other about the axis of symmetry 21. The first polishing amount adjusting lines 22 and 23 are inclined with respect to the first reference line 21 in opposite directions and by the same angle.
Further, among the planes exposed on the surface of the chip component 11 for evaluating the solder joint state, the first reference is applied to the bottom surface 11b which is a second plane parallel to the top surface 11a and positioned on the substrate side from the top surface 11a. The second reference line 31 and the two second polishing amount adjustment lines 32 and 33 are arranged so as to be parallel to the line 21 and the two first polishing amount adjustment lines 22 and 23. Each is formed in advance.
The second reference line 31 and the two second polishing amount adjustment lines 32 and 33 are the first reference line 21 formed on the upper surface 11a and the two second polishing amount adjusting lines 32 and 33 on the bottom surface 11b. It is formed at a position corresponding to the position where one polishing amount adjusting line 22, 23 is formed. That is, when the chip component 11 for solder joint state evaluation is viewed in a plan view, the first reference line 21, the two first polishing amount adjustment lines 22 and 23, and the second reference line 31 and the two second polishing amount adjustment lines 32 and 33 overlap each other.
At this time, as shown in FIG. 1A, the width in the front-rear direction of the first polishing amount adjustment lines 22 and 23 and the second polishing amount adjustment lines 32 and 33 is a0, and the width in the left-right direction. Is b0.
In the present embodiment, the first reference line 21, the two first polishing amount adjustment lines 22, 23, the second reference line 31, and the two second polishing amount adjustment lines. 32 and 33 are formed as silk lines by silk printing.

When observing the joint state of the solder joint portions 12 and 12, the solder joint state evaluation chip component 11 and the solder joint portions 12 and 12 are soldered substantially perpendicular to the first reference line 21. Since the flat surface (cross section AA in FIG. 1A, cross section A′-A ′ in FIG. 1C) separated from the front surface of the chip component 11 for bonding state evaluation by the width a1 is polished as a target plane. is there.
Thereafter, the end points 21a of the first reference line 21 and the first polishing amount adjustment lines 22 and 23 in the target cross section of the solder joint state evaluation chip component 11 shown in FIG. Widths b1 and b2 between 22a and 23a, and Widths b3 and b4 between the end points 31a and 32a and 33a of the second reference line 31 and the second polishing amount adjusting lines 32 and 33, respectively. Is measured.

Here, as described above, the first reference line 21, the two first polishing amount adjustment lines 22, 23, the second reference line 31, and the two second polishing amount adjustment lines 32. Since 33 is formed by silk printing with a three-dimensional thickness, as shown in FIG. 1B, the end points 21a, 22a, 23a, 31a, 32a, This makes it possible to recognize 33a visually or with a measuring instrument.
The first reference line 21, the two first polishing amount adjustment lines 22 and 23, the second reference line 31, and the two second polishing amount adjustment lines 32 and 33 are: The surface of the chip part 11 for evaluating the solder joint state is processed with a laser marker or the like, and is formed by carving a line-shaped groove so that it can be recognized in the cross section.

  In the interval widths b1, b2, b3, and b4 measured as described above, the polished cross section is parallel to a plane perpendicular to the straight line in the front-rear direction when the relationship of the following expression (1) is satisfied. In other words, it can be confirmed that the polishing is performed in a cross section perpendicular to the first reference line 21.

For example, when polishing is performed with a cross section tilted by rotating around a vertical axis from the plane where the parallelism is 0, that is, the target cross section, b2 with respect to b1 and b4 with respect to b3 have different sizes. It will be. In addition, when polishing is performed with a cross section that is rotated about the axis in the left-right direction and tilted, the sizes of b3 with respect to b1 and b4 with respect to b2 are different.
That is, if it is confirmed that the relationship of the above formula (1) is established in the measured interval widths b1, b2, b3, and b4, the polished cross section does not rotate about the axis in the vertical direction or the horizontal direction. In other words, it can be confirmed that the parallelism of the polished cross section is zero.

  Further, when the relationship of the following expression (2) is established for the widths a0, a1, b0, and b1, the polished cross section of the solder joint state evaluation chip component 11 is actually on the target plane separated from the front surface by the width a1. It can be confirmed that they match.

  That is, since the slope of the first polishing amount adjustment line 22 is constant, the ratio of a0 to b0 geometrically always coincides with the ratio of a1 to (b0-b1). Is established. That is, if the relationship between the measured interval width b1 and a0 · a1 · b0 is expressed by the above equation (2), the distance from the front surface is exactly a1 apart, in other words, a predetermined cross section. It can be confirmed that the material is polished.

  In the solder joint state evaluation method according to the present invention, the solder joint state evaluation chip component 11 is configured as described above, so that when the test product including the solder joint portions 12 and 12 is polished, the solder joint state evaluation chip component 11 is accurately specified. This makes it possible to observe the cross section of the film and to adjust the parallelism. That is, since the worker can accurately grasp and judge the polishing amount and the parallelism of the polished cross section without relying on intuition and tips in the polishing work, the actual polished cross section does not deviate from the target cross section, This can improve the reliability of cross-sectional observation.

For this reason, in the solder joint state evaluation method according to the present invention, as shown in FIG. 2, a plurality of target cross sections A1 to A5 are set for the solder joint state evaluation chip component 11 and observed. It can also be done.
That is, as shown in the plan view of FIG. 2, target cross sections are set in order from A1 to A5 from the front to the rear (direction of arrow α) of the solder joint state evaluation chip component 11, and the first cross section is set in each cross section. The distance between the end points of one reference line 21 and the first polishing amount adjustment lines 22 and 23, and the second reference line 31 and the second polishing amount adjustment lines 32 and 33. The interval width of each end point is measured. For example, the end points of the first polishing amount adjustment line 22 are end points 22a to 22a located at locations B1 to B5 from the right side toward the center direction (the direction of arrow β) in the target cross sections A1 to A5, respectively. 22e, the distance between the end points of the first polishing amount adjustment lines 22 and 23, and the second reference line 31 and the second polishing amount adjustment lines 32 and 33, respectively. It is measured in the same manner as above.

  In this way, by setting and observing a plurality of target cross sections on one solder joint state evaluation chip component 11, it becomes possible to three-dimensionally recognize the shape of cracks in the solder joint portions 12 and 12. . Specifically, according to the present embodiment, the first reference line 21 is formed on the upper surface 11a, and a plurality of planes substantially perpendicular to the first reference line 21 are set as target cross sections. In addition to the spread of cracks in the left-right direction, the length and shape of the cracks can also be grasped in the front-rear direction. As a result, it is possible to observe the spread of cracks in the front-rear direction, etc., which could not be determined by the conventional technology that had been observed with a single target cross section, so that the observation accuracy could be improved. It becomes possible. In the present embodiment, the target cross section is set to five of A1 to A5. However, the target cross section can be adjusted according to the size of the observation target, and the number is limited to the present embodiment. It is not a thing.

Next, a solder joint evaluation method according to another embodiment of the present invention will be described with reference to FIG.
Since the basic configuration of the solder joint state evaluation method according to this embodiment is the same as that of the above-described embodiment shown in FIG. 1, portions common to the above-described embodiment are denoted by the same reference numerals. The description is omitted.

In the solder joint state evaluation method according to this embodiment, of the planes exposed on the surface of the solder joint state evaluation chip component 11, the two solder joint surfaces 11c and 11d are orthogonal to each other and perpendicular to the substrate surface. The first front surface 11e, which is the first flat surface, is connected to the middle points 40, 40 of the two sides perpendicular to the solder joint surfaces 11c, 11d on the front surface 11e. The reference line 41 is formed in advance.
Further, the first reference line extends from the midpoint 40 of one side perpendicular to the solder joint surfaces 11c and 11d of the front surface 11e toward the other side of the front surface 11e opposite to the one side. Two first polishing amount adjusting lines 42 and 43 are formed in advance so as to be line-symmetric with respect to 41 as an axis of symmetry. The first polishing amount adjusting lines 42 and 43 are inclined with respect to the first reference line 41 in opposite directions and by the same angle.
Further, of the planes exposed on the surface of the chip component 11 for evaluating the solder joint state, the first reference is applied to the rear surface 11f, which is a second plane parallel to the front surface 11e and positioned behind the front surface 11e. The second reference line 51 and the two second polishing amount adjustment lines 52 and 53 are arranged so as to be parallel to the line 41 and the two first polishing amount adjustment lines 42 and 43. Each is formed in advance.
The second reference line 51 and the two second polishing amount adjustment lines 52 and 53 are the first reference line 41 formed on the front surface 11e and the two second polishing amount adjusting lines 52 and 53 on the rear surface 11f. It is formed at a position corresponding to the position where one polishing amount adjusting line 42/43 is formed. That is, when the chip component 11 for solder joint state evaluation is viewed from the front, the first reference line 41, the two first polishing amount adjustment lines 42 and 43, and the second reference line 51 and the two second polishing amount adjustment lines 52 and 53 overlap each other.
At this time, as shown in FIG. 3A, the vertical width of the first polishing amount adjusting lines 42 and 43 is h0, and the horizontal width is b0.

  When observing the joining state of the solder joint portions 12 and 12, the solder joint state evaluation chip component 11 and the solder joint portions 12 and 12 are soldered substantially perpendicular to the first reference line 41. Polishing is performed using a plane (HH cross section in FIG. 3A) separated from the bottom surface of the chip state 11 for bonding state evaluation by the width h1 as a target plane. Further, the end points 41a and 42a of the first reference line 41 and the first polishing amount adjusting lines 42 and 43 in the cross section of the solder joint state evaluation chip component 11 shown in FIG. The interval widths b1 and b2 of 43a and the interval widths b3 and b4 of the respective end points 51a and 52a and 53a of the second reference line and the second polishing amount adjusting line are measured.

  Also in the interval widths b1, b2, b3, and b4 measured as described above, when the relationship of the above equation (1) is established, the polished cross section is parallel to a plane perpendicular to the straight line in the vertical direction. It can be confirmed that there is some (the parallelism of the cross section is 0), in other words, that the polishing is performed in a cross section perpendicular to the first reference line 41.

  When the relationship of the following expression (3) is established for the widths h0, h1, b0, and b1, the polished cross section of the solder joint state evaluation chip component 11 is actually on the target plane that is separated from the front surface by the width h1. It can be confirmed that they match.

  That is, since the slope of the first polishing amount adjustment line 42 is constant, the ratio of h0 to b0 is geometrically consistent with the ratio of h1 to b1, so the above equation (3) is satisfied. is there. In other words, if the relationship of the above equation (3) is established for the measured interval width b1 and h0 · h1 · b0, the distance from the bottom surface is accurately separated by h1, in other words, exactly the predetermined distance It can be confirmed that the cross section is polished.

  Also in the solder joint state evaluation method according to the present embodiment, by configuring the solder joint state evaluation chip component 11 as described above, when the test product including the solder joint portions 12 and 12 is polished accurately A predetermined cross section can be observed, and the parallelism can be adjusted. That is, since the worker can accurately grasp and judge the polishing amount and the parallelism of the polished cross section without relying on intuition and tips in the polishing work, the actual polished cross section does not deviate from the target cross section, This can improve the reliability of cross-sectional observation. In addition, according to the present embodiment, the first reference line 41 is formed on the front surface 11e, and a plurality of planes substantially perpendicular to the first reference line 41 are set as target cross sections. Not only the spread of cracks but also the length and shape of the cracks can be grasped in the vertical direction.

(A) is a top view which shows the chip component for soldering state evaluation which concerns on this invention, (b) is the AA line in FIG. 1 (a) of the chip component for soldering state evaluation similarly (in FIG.1 (c)) (A'-A 'line) sectional drawing, (c) is a bottom view which similarly shows the chip component for soldering state evaluation. The top view which shows the chip component for solder joint state evaluation which concerns on this invention, and sectional drawing in each cross section. (A) is a front view which shows the chip component for solder joint state evaluation which concerns on another embodiment of this invention, (b) is the HH sectional view taken on the line of FIG. 3 (a) of the chip component for solder joint state evaluation similarly. (A) is a perspective view which shows the board | substrate which concerns on a prior art, (b) is a perspective view which shows the test article similarly containing the solder joint part which concerns on a prior art. (A) is a perspective view which shows the state which enclosed the test article which concerns on a prior art in resin, (b) is a perspective view which shows a mode that the test article based on a prior art is grind | polished with a grinder similarly. (A) is a top view which shows the chip component for soldering state evaluation which concerns on a prior art, (b) is sectional drawing in the grinding | polishing cross section of Fig.6 (a) of the chip component for soldering state evaluation similarly.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Chip component for solder joint state evaluation 12 Solder joint part 21 First reference line 22 First polishing amount adjustment line 23 First polishing amount adjustment line 31 Second reference line 32 For second polishing amount adjustment Line 33 Second polishing amount adjustment line

Claims (6)

Of the flat surfaces exposed on the surface of the rectangular parallelepiped chip component, each of the two flat surfaces positioned parallel to each other and perpendicular to the substrate is solder-bonded to the substrate as a solder bonding surface. A solder joint state evaluation method for simultaneously polishing a solder joint portion for joining a component and the substrate and the rectangular parallelepiped chip component and observing a joint state of the solder joint portion,
Of the planes exposed on the surface of the rectangular parallelepiped chip component, a first plane perpendicular to the two solder joint surfaces is connected to the midpoints of the two sides perpendicular to the solder joint surfaces. Create a reference line in advance,
In the first plane, from the midpoint of one side perpendicular to the solder joint surface of the first plane to the other side opposite to the one side in the first plane, the first reference line in the previous period Two first polishing amount adjustment lines are formed in advance so that they are symmetrical with respect to each other about the axis of symmetry,
Among the planes exposed on the surface of the rectangular parallelepiped chip component, the first reference line and the two first polishing amount adjustment lines are arranged on a second plane positioned parallel to the first plane. Each of the second reference line and the two second polishing amount adjustment lines in advance so as to be parallel to each other,
When observing the joining state of the solder joint portion, the rectangular chip component and the solder joint portion are polished by a plane substantially perpendicular to the first reference line, and the cross section of the rectangular chip component is , The distance between the end points of the first reference line and the first polishing amount adjustment line, and the end points of the second reference line and the second polishing amount adjustment line By confirming the parallelism of the cross-section of the rectangular parallelepiped chip component by measuring the interval of,
A method for evaluating a solder joint state. The first plane is a plane located on the side opposite to the substrate side of the rectangular parallelepiped chip component.
The method for evaluating a solder joint state according to claim 1, wherein: The first reference line, the two first polishing amount adjustment lines, the second reference line, and the two second polishing amount adjustment lines are formed by processing by silk printing or a laser marker.
The method for evaluating a solder joint state according to claim 1 or 2, wherein: Each of the two planes positioned parallel to each other and perpendicular to the substrate is soldered to the substrate as a solder bonding surface, and polished simultaneously with the solder bonding portion to be bonded to the substrate. It is a rectangular parallelepiped solder joint state evaluation chip component in which the joint state is observed,
Of the planes exposed on the surface of the solder joint state evaluation chip component, the first plane perpendicular to the two solder joint surfaces is connected to the midpoints of the two sides perpendicular to the solder joint surfaces, A first reference line parallel to the solder joint surface is formed;
In the first plane, from the midpoint of one side perpendicular to the solder joint surface of the first plane to the other side opposite to the one side in the first plane, the first reference line in the previous period Two first polishing amount adjustment lines are formed so as to be symmetrical with respect to each other about the axis of symmetry,
Among the planes exposed on the surface of the rectangular parallelepiped chip component, the first reference line and the two first polishing amount adjustment lines are arranged on a second plane positioned parallel to the first plane. The second reference line and two second polishing amount adjustment lines are formed so as to be parallel to each other,
Polishing in a plane substantially perpendicular to the first reference line together with the solder joint portion, and the first reference line and the first polishing amount adjustment line in the cross section of the chip component for solder joint state evaluation Measuring the distance between the respective end points, and the distance between the respective end points between the second reference line and the second polishing amount adjusting line. The parallelism of the cross section is confirmed,
A chip component for evaluating a solder joint state. The first plane is a plane located on the side opposite to the substrate side of the rectangular parallelepiped chip component.
The chip part for solder joint state evaluation according to claim 4, characterized in that: The first reference line, the two first polishing amount adjustment lines, the second reference line, and the two second polishing amount adjustment lines are formed by silk printing or laser marker processing. ,
The chip component for evaluating a solder joint state according to claim 4 or 5, characterized in that:

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