JP2010130526A - Offset detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in circuit threshold voltage with respect to a temperature change. <P>SOLUTION: An offset detection circuit 50 is provided with current sources 1 to 3, a Pch MOS transistor PT1, a Pch MOS transistor PT2, Nch MOS transistors NT1 to NT4, and a resistor R1. The Nch MOS transistors NT1 and NT2 and a differential couple of Pch MOS transistors PT1 and PT2 are set to the same β ratio, respectively. The current sources 1 and 2 cause a reference current Iref to flow to a side of a low-potential side power source VSS on the basis of a reference voltage supplied from a band gap reference circuit 4. A relation of a potential difference V(p-n) between an input voltage Vinp and an input voltage Vinn, a gate-source voltage Vgs1 of the Nch MOS transistor NT1, a gate-source voltage Vgs2 of the Nch MOS transistor NT2, a resistance value r1 of the resistor R1 and the reference current Iref is set to V(p-n)=(Vgs1-Vgs2)+(r1×Iref). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an offset detection circuit.

  In an amplifier such as a voltage amplifier circuit, a power amplifier, and an operational amplifier (op amp), an offset voltage is generated in an output signal. A semiconductor integrated circuit and various devices provided with an amplifier are provided with an offset detection circuit for determining whether or not the offset voltage exceeds a predetermined standard. When it is determined that the offset voltage exceeds a predetermined standard (circuit threshold voltage (Vth)), an alarm signal is output from the offset detection circuit (see, for example, Patent Document 1).

  When an unbalanced differential pair of MOS transistors is used in the offset detection circuit described in Patent Document 1 and the like, the temperature dependence of the circuit threshold voltage (Vth) is large, so whether or not the offset value satisfies a predetermined value. There is a problem that it is not possible to accurately judge. This is particularly noticeable in the industrial equipment field where the temperature guarantee range is wide.

In addition, when an unbalanced differential pair of MOS transistors is used, there is a problem that it is difficult to achieve matching at the layout design stage.
JP 2008-67046 A

  An object of the present invention is to provide an offset detection circuit capable of suppressing a fluctuation of a circuit threshold voltage with respect to a temperature change.

  An offset detection circuit according to one embodiment of the present invention includes a first Nch insulated gate type in which a first input voltage is input to a gate, a drain is connected to a high-potential side power supply side, and the first input voltage is level-shifted. A field effect transistor, a resistor having one end connected to the source of the first Nch insulated gate field effect transistor, a second input voltage input to the gate, and a drain connected to the high potential side power supply side; A second Nch insulated gate field effect transistor for level shifting the second input voltage; a first Pch insulated gate field effect transistor whose gate is connected to the other end of the resistor; and a gate for the second The second Pch isolation is connected to the source of the Nch insulated gate field effect transistor and forms a differential pair with the first Pch insulated gate field effect transistor. Characterized by comprising a gate-type field effect transistor.

  Furthermore, in the offset detection circuit according to another aspect of the present invention, the first input voltage is input to the gate, the drain is connected to the low-potential side power supply side, and the first Pch insulation for level-shifting the first input voltage is provided. A gate type field effect transistor, and a second Pch insulated gate field effect transistor in which a second input voltage is input to the gate, a drain is connected to the low potential power supply side, and the second input voltage is level-shifted A resistor having one end connected to the source of the second Pch insulated gate field effect transistor, and a first Nch insulated gate type having a gate connected to the source of the first Pch insulated gate field effect transistor. A field effect transistor and a second N having a gate connected to the other end of the resistor and forming a differential pair with the first Nch insulated gate field effect transistor Characterized by comprising an h insulated gate field effect transistor.

  ADVANTAGE OF THE INVENTION According to this invention, the offset detection circuit which can suppress the fluctuation | variation of a circuit threshold voltage with respect to a temperature change can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, an offset detection circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an offset detection circuit, and FIG. 2 is a circuit diagram showing an offset detection circuit of a comparative example. In this embodiment, correction means for suppressing the temperature of the offset value and the process variation is provided in the preceding stage of the transistors forming the differential pair.

  As shown in FIG. 1, the offset detection circuit 50 is provided with current sources 1 to 3, Pch MOS transistors PT1, Pch MOS transistors PT2, Nch MOS transistors NT1 to NT4, and a resistor R1. The offset detection circuit 50 is provided in a semiconductor integrated circuit or various devices. For example, whether the offset voltage of a signal output from an amplifier such as a voltage amplifier circuit, a power amplifier, or an operational amplifier (op amp) exceeds a predetermined standard. Make a decision. When the offset voltage of the signal output from the amplifier exceeds a predetermined standard, an alarm signal, for example, a high level signal is output from the offset detection circuit 50. The offset detection circuit 50 is an offset detection circuit suitable when the input voltage Vinp and the input voltage Vinn are relatively high potentials.

  Here, the MOS transistor is also referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The MIS transistor is also referred to as a MIS (Metal Insulator Semiconductor) transistor. The MOS transistor and MIS transistor are called insulated gate field effect transistors.

  The Nch MOS transistor NT1 has a drain connected to the high-potential-side power supply VCC, and an input voltage Vinp that is an input differential voltage is input to the gate, and the input voltage Vinp is level-shifted. Resistor R1 has one end connected to the source of Nch MOS transistor NT1 and the other end connected to node N1. Here, the resistor R1 is preferably made of a material having a small voltage coefficient and temperature coefficient, such as a polycrystalline polysilicon film, a metal cermet film, or a metal thin film doped with impurities formed on the field at a high concentration. .

  The Nch MOS transistor NT2 has a drain connected to the high potential side power supply VCC, a gate to which an input voltage Vinn as an input differential voltage is input, a source connected to the node N2, and a level shift of the input voltage Vinn.

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT1 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT2 are set to be the same. Is done. With this setting, complicated processing at the layout design stage can be reduced.

  One end of the current source 1 is connected to the other end (node N1) of the resistor R1, and the other end is connected to the low-potential-side power source VSS that is a ground voltage. The current source 1 causes the reference current Iref to flow to the low potential side power source VSS side based on the reference voltage supplied from the band gap reference circuit 4.

  One end of the current source 2 is connected to the source (node N2) of the Nch MOS transistor NT2, and the other end is connected to the low potential side power source VSS which is the ground voltage. The current source 2 causes the reference current Iref to flow to the low potential side power source VSS side based on the reference voltage supplied from the band gap reference circuit 4. Here, the reference current Iref generated by the current source 2 is at the same level as the reference current Iref generated by the current source 1.

  One end of the current source 3 is connected to the high potential side power supply VCC, the other end is connected to the node N3, and the bias current Ib flows to the node N3 side.

  In the Pch MOS transistor PT1, the source is connected to the node N3, the drain is connected to the node N4, and the gate is connected to the other end (node N1) of the resistor R1.

  Pch MOS transistor PT2 has a source connected to node N3, a drain connected to node N5, and a gate connected to the source (node N2) of Nch MOS transistor NT2.

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT1 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT2 are set to be the same. Make a balanced differential pair. With this setting, complicated processing at the layout design stage can be reduced.

  The Nch MOS transistor NT3 has a drain connected to the node N4, a gate connected to the drain, and a source connected to the low potential side power source VSS. The Nch MOS transistor NT4 has a drain connected to the node N5, a gate connected to the gate of the Nch MOS transistor NT3, and a source connected to the low potential power source VSS. Nch MOS transistor NT3 and Nch MOS transistor NT4 constitute a current mirror circuit.

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT3 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT4 are set to be the same. The With this setting, complicated processing at the layout design stage can be reduced.

  The output signal Sout of the offset detection circuit 50 is output from the node N5. When the potential difference between the input voltage Vinp and the input voltage Vinn exceeds a circuit threshold voltage (Vth) that is a predetermined standard value, the output signal Sout becomes an alarm signal that is at a high level (“1”). When the potential difference between the input voltage Vinp and the input voltage Vinn is equal to or lower than a circuit threshold voltage (Vth) that is a predetermined standard value, the output signal Sout is at a low level (“0”).

Here, the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, the gate-source voltage Vgs1 of the Nch MOS transistor NT1, the gate-source voltage Vgs2 of the Nch MOS transistor NT2, and the resistance value of the resistor R1 The relationship between r1 and the reference current Iref is
V (p−n) = (Vgs1−Vgs2) + (r1 × Iref) ・ ・ ・ ・ ・ ・ ・ ・ Formula (1)
It can be expressed as.

  (Vgs1-Vgs2) is equal to the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT1 and Nch MOS transistor NT2, and the respective drain currents are equal. The dependency is very small. Since the reference current Iref is inversely proportional to the resistance value of a resistor (not shown) provided in the bandgap reference circuit 4, (r1 × Iref) has very little process dependency and temperature dependency. For this reason, the offset voltage, which is the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, has very small process dependency and temperature dependency. Further, the circuit threshold voltage (Vth), which is a predetermined standard value, has very small process dependency and temperature dependency.

  As shown in FIG. 2, the offset detection circuit 60 of the comparative example is provided with a current source 5, a Pch MOS transistor PT11, a Pch MOS transistor PT12, an Nch MOS transistor NT11, and an Nch MOS transistor NT12. The offset detection circuit 60 of the comparative example determines whether the potential difference (offset voltage) between the input voltage Vinp and the input voltage Vinn exceeds a circuit threshold voltage (Vth) that is a predetermined standard.

  The Pch MOS transistor PT11 has a source connected to the high potential side power supply VCC, a gate connected to the drain, and a drain connected to the node N11. Pch MOS transistor PT12 has a source connected to high potential side power supply VCC, a gate connected to the gate of Pch MOS transistor PT11, and a drain connected to node N12.

  N-channel MOS transistor NT11 has a drain connected to node N11, a gate to which input voltage Vinp is input, and a source connected to node N13. N-channel MOS transistor NT12 has a drain connected to node N12, a gate to which input voltage Vinn is input, and a source connected to node N13.

  Nch MOS transistor NT11 and Nch MOS transistor NT12 form an unbalanced differential pair. Β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of Nch MOS transistor NT12 is m times larger than β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of Nch MOS transistor NT11. (Where m is 1 or more).

  One end of the current source 5 is connected to the node N13, the other end is connected to the low potential side power source VSS, and the bias current Ib flows to the low potential side power source VSS side.

  The output signal Sout of the offset detection circuit 60 is output from the node N12. In the offset detection circuit 60, since the potential difference (Vp−n) for switching the current value flowing through the Nch MOS transistor NT11 and the Nch MOS transistor NT12 forming the unbalanced differential pair has temperature dependence, the offset value can be accurately defined. Can not. That is, the offset voltage, which is the potential difference V (p−n) between the input voltage Vinp and the input voltage Vinn, has a large process dependency and temperature dependency, and the circuit threshold voltage (Vth), which is a predetermined standard value, is a process voltage. The dependence and temperature dependence are very large. Furthermore, the offset detection circuit 60 having an unbalanced differential pair requires complicated processing at the layout design stage.

  Next, temperature characteristics of the offset detection circuit will be described with reference to FIGS. FIG. 3 is a diagram showing the temperature dependence of the circuit threshold voltage of the offset detection circuit of this embodiment, and FIG. 4 is a diagram showing the temperature dependence of the circuit threshold voltage of the offset detection circuit of the comparative example. Here, the temperature dependence of the circuit threshold voltage of the offset detection circuit is calculated using simulation. The temperature is in the range of −40 ° C. to + 125 ° C. required for industrial equipment, and the circuit threshold voltage (Vth), which is a predetermined standard value required, is 100 ± 10 mV.

  As shown in FIG. 3, in the offset detection circuit 50 of the present embodiment, the circuit threshold voltage (Vth) is 96 to 104 mV in all the required temperature range (−40 ° C. to + 125 ° C.) and all satisfy the required standard value. The difference between the upper limit and the lower limit is as small as about 8 mV.

  On the other hand, as shown in FIG. 4, in the offset detection circuit 60 of the comparative example, the circuit threshold voltage (Vth) does not satisfy the required standard value of 77 to 126 mV in the entire required temperature range (−40 ° C. to + 125 ° C.). (At + 125 ° C., all do not satisfy the required standard value, and at −40 ° C., most do not satisfy the required standard value). In addition, the difference between the upper limit and the lower limit is about 49 mV, which is about 6 times larger than the present embodiment.

  As described above, in the offset detection circuit of this embodiment, the current sources 1 to 3, the Pch MOS transistor PT1, the Pch MOS transistor PT2, the Nch MOS transistors NT1 to NT4, and the resistor R1 are provided. The Nch MOS transistor NT1 receives the input voltage Vinp at its gate and shifts the level of the input voltage Vinp. The resistor R1 has one end connected to the source of the Nch MOS transistor NT1 and the other end connected to the gate of the Pch MOS transistor PT1 and one end of the current source 1. In the Nch MOS transistor NT2, the input voltage Vinn is input to the gate, the source is connected to the gate of the Pch MOS transistor PT2 and one end of the current source 2, and the input voltage Vinn is level-shifted. The current sources 1 and 2 flow the reference current Iref to the low potential side power source VSS side based on the reference voltage supplied from the band gap reference circuit 4. Nch MOS transistor NT1 and Nch MOS transistor NT2, and Pch MOS transistor PT1 and Pch MOS transistor PT2 forming a differential pair are set to the same β ratio. Potential difference V (pn) between input voltage Vinp and input voltage Vinn, gate-source voltage Vgs1 of Nch MOS transistor NT1, gate-source voltage Vgs2 of Nch MOS transistor NT2, resistance value r1 of resistor R1, reference The relationship of the current Iref is set to V (p−n) = (Vgs1−Vgs2) + (r1 × Iref).

  For this reason, the offset voltage, which is the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, has very small process dependency and temperature dependency. Further, the circuit threshold voltage (Vth), which is a predetermined standard value, has very small process dependency and temperature dependency. Therefore, the circuit threshold voltage (Vth) can be accurately defined over a wide temperature range, and the offset value can be accurately determined over a wide temperature range. Further, the Nch MOS transistor NT1 and the Nch MOS transistor NT2, the Nch MOS transistor NT3 and the Nch MOS transistor NT4, and the Pch MOS transistor PT1 and the Pch MOS transistor PT2 forming the differential pair constituting the offset detection circuit 50 have the same β ratio. Therefore, complicated processing at the layout design stage is not required.

  In the present embodiment, the offset detection circuit 50 is configured by a MOS transistor, but a MIS transistor may be used instead.

  Next, an offset detection circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing the offset detection circuit. In this embodiment, an Nch MOS transistor is used as a transistor forming a differential pair.

  As shown in FIG. 5, the offset detection circuit 51 includes current sources 1 to 3, Pch MOS transistors PT21 to PT24, Nch MOS transistor NT21, Nch MOS transistor NT22, and resistor R11. The offset detection circuit 51 is provided in a semiconductor integrated circuit or various devices. For example, whether the offset voltage of a signal output from an amplifier such as a voltage amplification circuit, a power amplifier, or an operational amplifier (op amp) exceeds a predetermined standard. Make a decision. When the offset voltage of the signal output from the amplifier exceeds a predetermined standard, an alarm signal, for example, a high level signal is output from the offset detection circuit 51. The offset detection circuit 51 is an offset detection circuit suitable when the input voltage Vinp and the input voltage Vinn are relatively low potentials.

  The current source 1 has one end connected to the high potential side power supply VCC and the other end connected to the node N21. The current source 1 causes the reference current Iref to flow to the node N21 side based on the reference voltage supplied from the band gap reference circuit 4.

  The current source 2 has one end connected to the high potential side power supply VCC and the other end connected to the node N22. The current source 2 causes the reference current Iref to flow to the node N22 side based on the reference voltage supplied from the band gap reference circuit 4. Here, the reference current Iref generated by the current source 2 is at the same level as the reference current Iref generated by the current source 1.

  In the Pch MOS transistor PT21, the source is connected to the other end (node N21) of the current source 1, the gate is supplied with the input voltage Vinp, the drain is connected to the low potential side power source VSS, and the input voltage Vinp is level-shifted.

  One end of the resistor R11 is connected to the other end (node N22) of the current source 2. In the Pch MOS transistor PT22, the source is connected to the other end of the resistor R11, the input voltage Vinn is input to the gate, the drain is connected to the low potential side power source VSS, and the input voltage Vinn is level-shifted. Here, the resistor R11 is preferably made of a material having a small voltage coefficient and temperature coefficient, such as a polycrystalline polysilicon film, a metal cermet film, or a metal thin film doped with impurities formed on the field at a high concentration. .

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT21 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT22 are set to be the same. The With this setting, complicated processing at the layout design stage can be reduced.

  The Pch MOS transistor PT23 has a source connected to the high potential side power supply VCC, a gate connected to the drain, and a drain connected to the node N23. The Pch MOS transistor PT24 has a source connected to the high potential side power supply VCC, a gate connected to the gate of the Pch MOS transistor PT23, and a drain connected to the node N24.

  Pch MOS transistor PT23 and Pch MOS transistor PT24 form a current mirror circuit. The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT23 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT24 are set to be the same. The With this setting, complicated processing at the layout design stage can be reduced.

  N-channel MOS transistor NT21 has a drain connected to node N23, a gate connected to node N21, and a source connected to node N25. N-channel MOS transistor NT22 has a drain connected to node N24, a gate connected to node N22, and a source connected to node N25.

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT21 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT22 are set to be the same. Make a balanced differential pair. With this setting, complicated processing at the layout design stage can be reduced.

  One end of the current source 3 is connected to the node N25, the other end is connected to the low potential side power source VSS, and the bias current Ib flows to the low potential side power source VSS side.

  An output signal Sout of the offset detection circuit 51 is output from the node N24. When the potential difference between the input voltage Vinp and the input voltage Vinn exceeds a circuit threshold voltage (Vth) that is a predetermined standard value, the output signal Sout becomes an alarm signal that is at a high level (“1”). When the potential difference between the input voltage Vinp and the input voltage Vinn is equal to or lower than a circuit threshold voltage (Vth) that is a predetermined standard value, the output signal Sout is at a low level (“0”).

Here, the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, the gate-source voltage Vgs21 of the Pch MOS transistor PT21, the gate-source voltage Vgs22 of the Pch MOS transistor PT22, and the resistance value of the resistor R11. The relationship between r11 and the reference current Iref is
V (p−n) = (| Vgs22 | − | Vgs21 |) + (r11 × Iref) Expression (2)
It can be expressed as.

  (| Vgs22 | − | Vgs21 |) is equal to the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Pch MOS transistor PT21 and the Pch MOS transistor PT22, and the respective drain currents are equal. Process dependence and temperature dependence are very small. Since the reference current Iref is inversely proportional to the resistance value of a resistor (not shown) provided in the band gap reference circuit 4, (r11 × Iref) has very little process dependency and temperature dependency. For this reason, the offset voltage, which is the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, has very small process dependency and temperature dependency. Further, the circuit threshold voltage (Vth), which is a predetermined standard value, has very small process dependency and temperature dependency.

  As described above, in the offset detection circuit of the present embodiment, the current sources 1 to 3, the Pch MOS transistors PT21 to PT24, the Nch MOS transistor NT21, the Nch MOS transistor NT22, and the resistor R11 are provided. The input voltage Vinp is input to the gate of the Pch MOS transistor PT21, and the level of the input voltage Vinp is shifted. In the Pch MOS transistor PT22, the input voltage Vinn is input to the gate, and the input voltage Vinn is level-shifted. Resistor R11 has one end connected to the source of Pch MOS transistor PT22 and the other end connected to node N22. The current sources 1 and 2 flow the reference current Iref to the low potential side power source VSS side based on the reference voltage supplied from the band gap reference circuit 4. Pch MOS transistor PT21 and Pch MOS transistor PT22, and Nch MOS transistor NT21 and Nch MOS transistor NT22 forming a differential pair are set to the same β ratio. The potential difference V (p−n) between the input voltage Vinp and the input voltage Vinn, the gate-source voltage Vgs21 of the Pch MOS transistor PT21, the gate-source voltage Vgs22 of the Pch MOS transistor PT22, the resistance value r11 of the resistor R11, the reference The relationship of the current Iref is set to V (p−n) = (| Vgs22 | − | Vgs21 |) + (r11 × Iref).

  For this reason, the offset voltage, which is the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, has very small process dependency and temperature dependency. Further, the circuit threshold voltage (Vth), which is a predetermined standard value, has very small process dependency and temperature dependency. Therefore, the circuit threshold voltage (Vth) can be accurately defined over a wide temperature range, and the offset value can be accurately determined over a wide temperature range. Further, the Pch MOS transistor PT21 and the Pch MOS transistor PT22, the Pch MOS transistor PT23 and the Pch MOS transistor PT24, and the Nch MOS transistor NT21 and the Nch MOS transistor NT22 forming the differential pair, which constitute the offset detection circuit 51, have the same β ratio. Therefore, complicated processing at the layout design stage is not required.

  Next, an offset detection circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing the offset detection circuit. In this embodiment, a current mirror circuit is provided on the high potential side power supply side.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the offset detection circuit 52 includes a current source 1, a current source 2, Pch MOS transistors PT1 to PT4, Nch MOS transistors NT1 to NT4, and a resistor R1. The offset detection circuit 52 is provided in a semiconductor integrated circuit or various devices. For example, whether the offset voltage of a signal output from an amplifier such as a voltage amplifier circuit, a power amplifier, or an operational amplifier (op amp) exceeds a predetermined standard. Make a decision. When the offset voltage of the signal output from the amplifier exceeds a predetermined standard, an alarm signal, for example, a high level signal is output from the offset detection circuit 52.

  The Pch MOS transistor PT3 has a source connected to the high potential side power supply VCC, a gate connected to the drain, and a drain connected to the node N6, the drain of the Nch MOS transistor NT1, and the drain of the Nch MOS transistor NT2. The Pch MOS transistor PT4 has a source connected to the high potential side power supply VCC, a gate connected to the gate of the Pch MOS transistor PT3, and a drain connected to the node N3, the source of the Pch MOS transistor PT1, and the source of the Pch MOS transistor PT2. Is done. Pch MOS transistor PT3 and Pch MOS transistor PT4 form a current mirror circuit.

  The offset detection circuit 52 operates in the same manner as in the first embodiment when the input voltage Vinp and the input voltage Vinn are relatively high potentials. In the offset detection circuit 52, when the input voltage Vinp and the input voltage Vinn are relatively low potentials, the current flowing in the Pch MOS transistor PT3 is suppressed, so that the offset detection circuit 52 flows in the Pch MOS transistors PT1 and PT2 of the balanced differential pair in the next stage. The current is reduced, and the malfunction of the circuit is suppressed.

  As described above, in the offset detection circuit of this embodiment, the current source 1, the current source 2, the Pch MOS transistors PT1 to PT4, the Nch MOS transistors NT1 to NT4, and the resistor R1 are provided. Pch MOS transistor PT3 and Pch MOS transistor PT4 constitute a current mirror circuit. When the input voltage Vinp and the input voltage Vinn are relatively low potentials, this current mirror circuit restricts the current flowing through the Pch MOS transistors PT1 and PT2 of the balanced differential pair at the next stage.

  For this reason, in addition to the effects of the first embodiment, when the input voltage Vinp and the input voltage Vinn are relatively low potentials, malfunction of the offset detection circuit 52 can be suppressed.

  Next, an offset detection circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram showing the offset detection circuit. In this embodiment, a current mirror circuit is provided on the low potential side power supply side.

  In the following, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the offset detection circuit 53 includes a current source 1, a current source 2, Pch MOS transistors PT21 to PT24, Nch MOS transistors NT21 to NT24, and a resistor R11. The offset detection circuit 53 is provided in a semiconductor integrated circuit or various devices. For example, whether the offset voltage of a signal output from an amplifier such as a voltage amplifier circuit, a power amplifier, or an operational amplifier (op amp) exceeds a predetermined standard. Make a decision. When the offset voltage of the signal output from the amplifier exceeds a predetermined standard, the offset detection circuit 53 outputs an alarm signal, for example, a high level signal.

  The Nch MOS transistor NT23 has a drain connected to the drain of the Pch MOS transistor PT21 and a drain (node N26) of the Pch MOS transistor PT22, a gate connected to the drain, and a source connected to the low potential power source VSS. The Nch MOS transistor NT24 has a drain connected to the source of the Nch MOS transistor NT21, a source of the Nch MOS transistor NT22, and a node N25, a gate connected to the gate of the Nch MOS transistor NT23, and a source connected to the low potential side power supply VSS. Is done. Nch MOS transistor NT23 and Nch MOS transistor NT24 constitute a current mirror circuit.

  The offset detection circuit 53 operates in the same manner as in the second embodiment when the input voltage Vinp and the input voltage Vinn are relatively low potentials. In the offset detection circuit 53, when the input voltage Vinp and the input voltage Vinn are relatively high potentials, the current flowing through the Nch MOS transistor NT23 is suppressed, so that the current flows through the balanced differential pair Nch MOS transistors NT21 and NT22 in the next stage. The current is reduced, and the malfunction of the circuit is suppressed.

  Note that the combination of the offset detection circuit 53 of the present embodiment and the offset detection circuit 52 of the third embodiment makes it possible to achieve a Rail to Rail configuration of the offset detection circuit.

  As described above, the offset detection circuit of this embodiment includes the current source 1, the current source 2, the Pch MOS transistors PT21 to PT24, the Nch MOS transistors NT21 to NT24, and the resistor R11. Nch MOS transistor NT23 and Nch MOS transistor NT24 constitute a current mirror circuit. With this current mirror circuit, when the input voltage Vinp and the input voltage Vinn are relatively high, the current flowing through the Nch MOS transistors NT21 and NT22 of the balanced differential pair at the next stage is reduced.

  For this reason, in addition to the effect of the second embodiment, when the input voltage Vinp and the input voltage Vinn are relatively high potentials, malfunction of the offset detection circuit 53 can be suppressed.

  Next, an offset detection circuit according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing the offset detection circuit. The configuration of the correction means for suppressing the temperature of the offset value and the process variation is changed.

  In the following, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the offset detection circuit 54 includes current sources 1 to 3, current source 6, current source 7, Pch MOS transistors PT21 to PT24, Nch MOS transistor NT21, Nch MOS transistor NT22, Nch MOS transistor NT25, An Nch MOS transistor NT26, a resistor R21, and a resistor R22 are provided. The offset detection circuit 54 is provided in a semiconductor integrated circuit or various devices. For example, whether the offset voltage of a signal output from an amplifier such as a voltage amplifier circuit, a power amplifier, or an operational amplifier (op amp) exceeds a predetermined standard. Make a decision. When the offset voltage of the signal output from the amplifier exceeds a predetermined standard, an alarm signal, for example, a high level signal is output from the offset detection circuit 54.

  The Nch MOS transistor NT25 has a drain connected to the high potential side power supply VCC, an input voltage Vinp input to the gate, and a level shift of the input voltage Vinp. One end of resistor R21 is connected to the source of Nch MOS transistor NT25, and the other end is connected to node N27 and the gate of Pch MOS transistor PT21.

  N-channel MOS transistor NT26 has a drain connected to high potential side power supply VCC, a gate supplied with input voltage Vinn, a source connected to node N28, and level shift of input voltage Vinn. The resistor R22 has one end connected to the other end of the current source 2 and the node N22, and the other end connected to the source of the Pch MOS transistor PT22. Here, the resistors R21 and R22 are made of a material having a small voltage coefficient and temperature coefficient, for example, a polycrystalline polysilicon film, a metal cermet film, or a metal thin film doped with impurities formed on the field at a high concentration. Is preferred.

  The β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT25 and the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of the Nch MOS transistor NT26 are set to be the same. The With this setting, complicated processing at the layout design stage can be reduced.

  The current source 6 has one end connected to the node N27 and the other end connected to the low potential side power source VSS. The current source 6 allows the reference current Iref to flow to the low potential side power supply VSS side based on the reference voltage supplied from the band gap reference circuit 4. One end of the current source 7 is connected to the node N28, and the other end is connected to the low potential side power source VSS. The current source 7 causes the reference current Iref to flow to the low potential side power supply VSS side based on the reference voltage supplied from the band gap reference circuit 4.

  The reference current Iref generated by the current source 6 and the reference current Iref generated by the current source 7 are at the same level as the reference current Iref generated by the current source 1.

Here, the relationship between the resistance value r21 of the resistor R21, the resistance value r22 of the resistor R22, and the resistance value r11 of the resistor R11 of Example 2 is as follows:
r21 = (1−X) × r11 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Formula (3)
r22 = (X) x r11 ... Formula (4)
Set to Note that the value of X is a real number of 1 or less.

Potential difference V (pn) between input voltage Vinp and input voltage Vinn, gate-source voltage Vgs25 of Nch MOS transistor NT25, gate-source voltage Vgs26 of Nch MOS transistor NT26, gate-source of Pch MOS transistor PT21 The relationship between the inter-voltage Vgs21, the gate-source voltage Vgs22 of the Pch MOS transistor PT22, the resistance value r11 of the resistor R11 in the second embodiment, and the reference current Iref is as follows:
V (p−n) = (Vgs25−Vgs26) + (| Vgs22 | − | Vgs21 |) + (r11 × Iref) (5)
It can be expressed as.

  (Vgs25−Vgs26) + (| Vgs22 | − | Vgs21 |) has the same β ratio (Wg (gate width dimension) / Lg (gate length dimension)) between the Pch MOS transistor PT21 and the Pch MOS transistor PT22, and the Nch MOS transistor. Since the β ratio (Wg (gate width dimension) / Lg (gate length dimension)) of NT25 and Nch MOS transistor NT26 is equal and the respective drain currents are equal, the process dependency and temperature dependency are very small. Since the reference current Iref is inversely proportional to the resistance value of a resistor (not shown) provided in the band gap reference circuit 4, (r11 × Iref) has very little process dependency and temperature dependency. For this reason, the offset voltage, which is the potential difference V (pn) between the input voltage Vinp and the input voltage Vinn, has very small process dependency and temperature dependency. Further, the circuit threshold voltage (Vth), which is a predetermined standard value, has very small process dependency and temperature dependency.

  As described above, in the offset detection circuit of this embodiment, the current sources 1 to 3, the current source 6, the current source 7, the Pch MOS transistors PT21 to PT24, the Nch MOS transistor NT21, the Nch MOS transistor NT22, the Nch MOS transistor NT25, An Nch MOS transistor NT26, a resistor R21, and a resistor R22 are provided. Potential difference V (pn) between input voltage Vinp and input voltage Vinn, gate-source voltage Vgs25 of Nch MOS transistor NT25, gate-source voltage Vgs26 of Nch MOS transistor NT26, gate-source of Pch MOS transistor PT21 The relationship between the voltage Vgs21, the gate-source voltage Vgs22 of the Pch MOS transistor PT22, the resistance value r11 of the resistor R11 and the reference current Iref in the second embodiment is V (p−n) = (Vgs25−Vgs26) + (| Vgs22 | − | Vgs21 |) + (r11 × Iref).

  Therefore, in addition to the effect of the first embodiment, the process dependency and the temperature dependency of the gate-source voltage are implemented by adjusting the shape ratio of the Nch MOS transistor and the Pch MOS transistor constituting the offset detection circuit 54. It can be made smaller than Example 1.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the first embodiment, a current mirror circuit is provided between the drain side of the Pch MOS transistors PT1 and PT2 forming a differential pair and the low potential side power source VSS, but the drain side of the Pch MOS transistors PT1 and PT2 is output. You may connect to the step side. In the second embodiment, a current mirror circuit is provided between the drain side of the Nch MOS transistor that forms a differential pair with the high potential side power supply VCC. However, the drain side of the Nch MOS transistor is connected to the output stage side. Also good.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A first Pch insulated gate field effect transistor having a source connected to a high potential power source and a gate connected to a drain, a source connected to the high potential power source, and a gate connected to the first power source A second Pch insulated gate field effect transistor connected to the gate of the Pch insulated gate field effect transistor, a first input voltage input to the gate, and a drain of the first Pch insulated gate field effect transistor. A first Nch insulated gate field effect transistor connected to the drain and level-shifting the first input voltage; a resistor having one end connected to the source of the first Nch insulated gate field effect transistor; and a gate Is connected to the drain of the first Pch insulated gate field effect transistor. A second Nch insulated gate field effect transistor level-shifting the second input voltage, a gate connected to the other end of the resistor, and a source drain of the second Pch insulated gate field effect transistor A third Pch insulated gate field effect transistor connected to the gate, a gate connected to a source of the second Nch insulated gate field effect transistor, and a source connected to the drain of the second Pch insulated gate field effect transistor A fourth Pch insulated gate field effect transistor which is connected to the third Pch insulated gate field effect transistor and forms a differential pair with the third Pch insulated gate field effect transistor, wherein the first input voltage and the second input voltage are The comparison is made to determine whether the potential difference between the first input voltage and the second input voltage exceeds a circuit threshold voltage. Set detection circuit.

(Supplementary Note 2) A first reference current is provided between the other end of the resistor and a low-potential side power supply, and causes a first reference current to flow to the low-potential side power supply side based on a reference voltage output from a bandgap reference circuit. Current source, a source of the second Nch insulated gate field effect transistor, and the low potential side power source, and a second reference current having the same level as the first reference current based on the reference voltage The offset detection circuit according to appendix 1, further comprising: a second current source that supplies a current to the low-potential-side power supply side.

(Supplementary Note 3) A first input voltage is input to the gate, the first Pch insulated gate field effect transistor level-shifts the first input voltage, and the second input voltage is input to the gate. 2, a second Pch insulated gate field effect transistor for level shifting the input voltage, a resistor having one end connected to the source of the second Pch insulated gate field effect transistor, and a drain connected to the first and second A first Nch insulated gate field effect transistor having a gate connected to the drain and a source connected to the low-potential side power supply; and a gate connected to the first Nch. A second Nch insulated gate electric field connected to the gate of the insulated gate field effect transistor and having a source connected to the low potential side power source And a third Nch insulated gate electric field whose gate is connected to the source of the first Pch insulated gate field effect transistor and whose source is connected to the drain of the second Nch insulated gate field effect transistor. An effect transistor, a gate connected to the other end of the resistor, a source connected to a drain of the second Nch insulated gate field effect transistor, and a differential pair with the first Nch insulated gate field effect transistor. And a potential difference between the first input voltage and the second input voltage by comparing the first input voltage with the second input voltage. An offset detection circuit that determines whether or not the circuit threshold voltage is exceeded.

(Supplementary Note 4) A first reference current is provided based on a reference voltage provided between a high-potential-side power supply and a source of the first Pch insulated gate field effect transistor and output from a band gap reference circuit. A first current source that flows to the low-potential-side power supply side through one Pch insulated gate field effect transistor, and provided between the high-potential-side power supply and the other end of the resistor, based on the reference voltage Appendix 3 comprising: a second current source for supplying a second reference current having the same level as that of the first reference current to the low-potential-side power supply side through the second Pch insulated gate field effect transistor The offset detection circuit described.

(Supplementary Note 5) A first Nch insulated gate field effect transistor in which a first input voltage is input to a gate and a drain is connected to a high-potential side power supply, and one end of the first Nch insulated gate field effect transistor is connected to the first potential A first resistor connected to the source of the transistor, a first Pch insulated gate field effect transistor having a gate connected to the other end of the resistor and a drain connected to the low-potential side power source, and a second connected to the gate An input voltage is input, a drain is connected to the high-potential side power supply, a second Nch insulated gate field effect transistor, a gate is connected to a source of the second Nch insulated gate field effect transistor, and a drain is A second Pch insulated gate field effect transistor connected to the low potential side power source, and one end of the second Pch insulated gate field effect transistor A second resistor connected to the source of the first Pch insulated gate field effect transistor, a third Nch insulated gate field effect transistor whose gate is connected to the source of the first Pch insulated gate field effect transistor, and a gate connected to the second resistor. A fourth Nch insulated gate field effect transistor which is connected to the other end of the first and forms a differential pair with the third Nch insulated gate field effect transistor, and the first input voltage and the second An offset detection circuit that compares input voltages and determines whether a potential difference between the first input voltage and the second input voltage exceeds a circuit threshold voltage.

(Supplementary Note 6) A first reference current is provided between the one end of the first resistor and the low-potential-side power supply, and the first reference current is supplied to the low-potential-side power supply side based on a reference voltage output from a band gap reference circuit. A first current source that flows, a high-potential side power source, and a source of the first Pch insulated gate field effect transistor, and a first current source having the same level as the first reference current based on the reference voltage. 2 reference currents to the low-potential-side power supply side through the first Pch insulated gate field effect transistor, the source of the second Nch insulated gate field effect transistor, and the low current source A third current source provided between the potential-side power sources and configured to flow a third reference current of the same level as the first reference current to the low-potential-side power source side based on the reference voltage; Power supply and said A fourth reference current having the same level as the first reference current based on the reference voltage, and the second resistor and the second Pch insulated gate field effect transistor. The offset detection circuit according to appendix 5, further comprising: a fourth current source that flows to the low-potential-side power supply side through

(Supplementary note 7) Any one of Supplementary notes 1 to 6, wherein the β ratios of the transistors for level shifting the input voltage are set to be the same, and the β ratios of the transistors forming the differential pair are also set to be the same. An offset detection circuit according to claim 1.

1 is a circuit diagram showing an offset detection circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing an offset detection circuit of a comparative example according to Embodiment 1 of the present invention. The figure which shows the temperature dependence of the circuit threshold voltage of the offset detection circuit of the present Example which concerns on Example 1 of this invention. The figure which shows the temperature dependence of the circuit threshold voltage of the offset detection circuit of the comparative example which concerns on Example 1 of this invention. FIG. 6 is a circuit diagram illustrating an offset detection circuit according to a second embodiment of the invention. FIG. 6 is a circuit diagram illustrating an offset detection circuit according to a third embodiment of the invention. FIG. 6 is a circuit diagram illustrating an offset detection circuit according to a fourth embodiment of the invention. FIG. 9 is a circuit diagram illustrating an offset detection circuit according to a fifth embodiment of the invention.

Explanation of symbols

1, 2, 3, 5-7 Current source 4 Band gap reference circuits 50-54, 60 Offset detection circuit Ib Bias current Iref Reference currents PT1-PT4, PT11, PT12, PT21-PT24 Pch MOS transistors N1-N6, N11- N13, N21 to N28 Nodes NT1 to NT4, NT11, NT12, NT21 to NT26 Nch MOS transistors R1, R11, R21, R22 Resistor Sout Output signal VCC High potential side power supply Vinn, Vinp Input voltage VSS Low potential side power supply

Claims (5)

A first Nch insulated gate field effect transistor having a first input voltage input to the gate, a drain connected to the high potential side power supply side, and level shifting the first input voltage;
A resistor having one end connected to the source of the first Nch insulated gate field effect transistor;
A second Nch insulated gate field effect transistor having a second input voltage input to the gate, a drain connected to the high-potential-side power supply side, and level-shifting the second input voltage;
A first Pch insulated gate field effect transistor having a gate connected to the other end of the resistor;
A second Pch insulated gate field effect transistor having a gate connected to a source of the second Nch insulated gate field effect transistor and forming a differential pair with the first Pch insulated gate field effect transistor;
An offset detection circuit comprising: A first current source provided between the other end of the resistor and a low-potential side power supply and configured to flow a first reference current to the low-potential side power supply side based on a reference voltage output from a band gap reference circuit; ,
Provided between the source of the second Nch insulated gate field effect transistor and the low-potential side power supply, and based on the reference voltage, the second reference current having the same level as the first reference current is supplied to the low-potential side A second current source flowing to the power supply side;
The offset detection circuit according to claim 1, further comprising: A first Pch insulated gate field effect transistor having a first input voltage input to the gate and a drain connected to the low-potential side power supply side, and level-shifting the first input voltage;
A second Pch insulated gate field effect transistor having a second input voltage input to the gate, a drain connected to the low-potential-side power supply side, and level-shifting the second input voltage;
A resistor having one end connected to the source of the second Pch insulated gate field effect transistor;
A first Nch insulated gate field effect transistor having a gate connected to a source of the first Pch insulated gate field effect transistor;
A second Nch insulated gate field effect transistor having a gate connected to the other end of the resistor and forming a differential pair with the first Nch insulated gate field effect transistor;
An offset detection circuit comprising:   Comparing the first input voltage with the second input voltage and determining whether a potential difference between the first input voltage and the second input voltage exceeds a circuit threshold voltage; The offset detection circuit according to any one of claims 1 to 3.   5. The β ratio of transistors that level shift the input voltage is set to be the same, and the β ratio of transistors that form a differential pair is also set to be the same. The offset detection circuit described in 1.

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