JP2010128612A - Sequence control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sequence control system easily increasing the speed of arithmetic processing of a programmable controller. <P>SOLUTION: When a compiler 8 of a programming tool 2 compiles a program created by a user into instruction codes compatible with a processor 3 of a PLC 1, the compiler 8 classifies devices included in the instruction codes into devices to be frequently used and devices not to be frequently used based on use frequency when executing the instruction codes. Device data representing the states of the devices to be frequently used are stored in a built-in memory 6 of the processor 3, and device data representing the states of the devices not to be frequently used are stored in a data memory 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a sequence control system including a programmable controller that performs sequence control according to an instruction code, and a programming tool that sets the instruction code in the programmable controller.

  Conventionally, a processor that executes an instruction code including a plurality of devices (contacts, etc.), an instruction memory that stores the instruction code, and device data that represents a device state (contact opening / closing, etc.) are stored in the processor. There is provided a programmable controller (hereinafter referred to as “PLC”) including a data memory used as a work area when executing the above. This PLC is used for controlling various devices because of its convenience that the control content can be arbitrarily set by a program.

  By the way, in recent years, the configuration of devices to be controlled by the PLC has become complicated, and high-speed operation has been required. Therefore, high-speed arithmetic processing is also demanded in PLCs (for example, patents). Reference 1).

  Therefore, in this type of PLC, in order to realize high-speed arithmetic processing of the processor, a high-speed SRAM capable of high-speed memory access is used as a data memory for storing device data used for arithmetic processing. It has been proposed that memory access be directly performed between the two.

  However, in this configuration, since the path between the processor and the high-speed SRAM goes through the circuit board or the like, speeding up of the memory access is hindered by an inductive component or a capacitance component of the circuit board. Therefore, a time lag of about 10 ns occurs when a general high-speed SRAM is used due to a memory access time between the processor and the high-speed SRAM and a time delay that occurs during signal transmission.

  Therefore, in order to realize higher-speed arithmetic processing, it is considered to provide a built-in memory in the processor and store device data in the built-in memory only for a predetermined device (hereinafter referred to as a fixed selection method). As a result, when device data stored in the built-in memory is used, access between the processor and the data memory becomes unnecessary, which leads to an increase in the processing speed.

In addition, using the built-in memory as a cache memory, the device data within the range that can be stored from the beginning of the instruction code is stored in the built-in memory, and the device data in the built-in memory is stored in the data memory device during the execution of the instruction code. It is also considered to replace it with data at any time (hereinafter referred to as a cache method). In this method, the processor reads the device data when access to the device data in the data memory becomes necessary, and the device data with the least number of accesses among the device data stored in the built-in memory. Replace.
JP 2008-226276 A

  However, the above-described fixed selection method and cache method have the following problems.

  In other words, the built-in memory has a smaller memory capacity than the data memory, and the fixed selection method speeds up the arithmetic processing only when using some devices stored in the built-in memory. Unless a program is created by intentionally limiting the devices to be mainly used to the part of the devices, it is not possible to expect an increase in the processing speed.

  On the other hand, in the cache method, when a cache miss occurs (that is, when device data does not exist in the built-in memory), data is exchanged between the data memory and the built-in memory. In such cases, it is difficult to speed up the arithmetic processing.

  The present invention has been made in view of the above-described reasons, and an object thereof is to provide a sequence control system that can easily increase the speed of arithmetic processing of a programmable controller.

  According to the first aspect of the present invention, a programmable controller that performs sequence control according to an instruction code including a plurality of devices, and a programming tool that sets the instruction code in the programmable controller, the programmable controller includes a built-in memory and includes an instruction code. A programming tool having a processor to be executed, an instruction memory for storing an instruction code, and a data memory for storing device data representing a device state and used as a work area when the processor executes the instruction code Classifying means for classifying the device into a device having a high usage frequency and a device having a low usage frequency based on the frequency of use in executing the instruction code when compiling a user-created program into an instruction code; Frequent device status Distribution means for allocating the storage location of the device data so that the storage location of the device data representing the device is a built-in memory of the processor and the storage location of the device data representing the state of the infrequently used device is the data memory It is characterized by having.

  According to this configuration, device data indicating the state of a frequently used device is stored in the built-in memory of the processor, so that the processor accesses the built-in memory when the device is used during execution of the instruction code. By doing so, it is possible to perform arithmetic processing, and it is possible to increase the speed of the arithmetic processing as compared with the case of accessing the data memory. In addition, when compiling with a programming tool, a device that is frequently used for executing instruction codes is automatically selected, and device data of the device is stored in the built-in memory. Even if the device to be used is not intentionally restricted, it can be expected that the processing speed is increased. In addition, since device data is not exchanged between the data memory and the built-in memory during execution of the instruction code, it is possible to avoid a decrease in the speed of arithmetic processing due to data exchange between the data memory and the built-in memory. . In the case where there is no problem even if the operation processing of a device that is not frequently used is slow, a cheaper memory than a high-speed SRAM can be used as a data memory.

  According to a second aspect of the present invention, in the first aspect of the invention, the programming tool includes a changing unit that changes the device in which the device data is stored in the built-in memory according to a user operation. .

  According to this configuration, the user can change the device in which the device data is stored in the built-in memory. There is an advantage that arithmetic processing can be realized.

  According to a third aspect of the present invention, in the first aspect of the invention, the programming tool has an automatic mode in which the device in which the device data is stored in the built-in memory is used as the frequently used device, and device data in the built-in memory. A manual mode that allows a user to select a device in which the device is stored, a fixed selection mode in which a device in which device data is stored in the internal memory is a predetermined device, and a predetermined range of device data are stored in the internal memory, If access to device data in the data memory occurs during execution of the instruction code in the processor, the device data is the device data with the least number of accesses among the device data stored in the internal memory. There is a mode switching means that can switch the cache mode to be replaced. And wherein the Rukoto.

  According to this configuration, there is an advantage that the degree of freedom of program creation is improved by switching between the automatic mode, the manual mode, the fixed selection mode, and the cache mode.

  According to the present invention, device data representing the state of a frequently used device is stored in the built-in memory of the processor. Therefore, there is an advantage that the operation speed of the programmable controller can be easily increased.

(Embodiment 1)
As shown in FIG. 1, the sequence control system of the present embodiment includes a programmable controller (hereinafter referred to as PLC) 1 that performs sequence control according to an instruction code, and a programming tool 2 that sets the instruction code in the PLC 1. Although illustration is omitted here, switches and various sensors are connected to the input of the PLC1, and devices such as motors and various actuators to be controlled are connected to the output of the PLC1, and the PLC1 is connected to the switches and various sensors. The device to be controlled is controlled according to the input from.

  The PLC 1 includes a processor 3 that executes an instruction code, an instruction memory 4 that stores the instruction code, and a data memory 5 that is used as a work area when the processor 3 executes the instruction code. The instruction code includes a plurality of devices (contacts and the like) and constitutes an instruction for reading and writing the state (opening and closing of the contacts) of each device. Device data representing the state of each device is stored in the data memory 5 and used when the processor 3 executes an instruction code.

  Furthermore, in this embodiment, as shown in FIG. 1, the processor 3 is provided with a built-in memory 6. The built-in memory 6 has a smaller memory capacity than the instruction memory 4 and the data memory 5 provided separately from the processor 3, but the memory access from the processor 3 is faster than the instruction memory 4 and the data memory 5. It is. As will be described in detail later, the built-in memory 6 stores device data representing the state of some devices.

  The programming tool 2 includes a program creation unit 7 that creates a program (for example, a ladder program as shown in FIG. 2) that is a source of an instruction code in accordance with a user operation input from an input operation means (keyboard or the like) (not shown), and the program It has a compiler 8 that compiles into an instruction code composed of a machine language that can be understood by the processor 3, and a memory 9 that stores a program and an instruction code.

  The compiler 8 serves as a classification unit that classifies the devices included in the instruction code into a frequently used device and a less frequently used device based on the frequency of use in executing the instruction code when performing the above compilation. It has the function of. Further, the compiler 8 sets the storage location of the device data representing the state of the frequently used device as the built-in memory 6 of the processor 3, and sets the storage location of the device data representing the state of the low usage frequency as the data memory 5. As described above, it has a function as a distribution means for allocating storage locations of device data. Thus, device data representing the state of a device classified as having a higher usage frequency is stored in the internal memory 6 of the processor 3. For example, when a ladder program as shown in FIG. 2 is assembled, if it is determined that the frequency of use of the device R0 (in this case, a relay) is high, device data representing the state of the device R0 is stored in the internal memory of the processor 3 6 is stored. For this reason, the number of devices classified into the frequently used side is limited by the capacity of device data that can be stored in the internal memory 6 of the processor 3.

  The operation of the programming tool 2 will be described below with reference to the flowchart of FIG.

  The compiler 8 counts the number of times of use for each device on the program at the time of compilation (S1), and in order from the most frequently used device to the predetermined number of devices (the frequently used device) and other devices (the frequently used device). Low device). The programming tool 2 stores the device information (reference address, device type code, etc.) corresponding to the device in the instruction memory 4 of the PLC 1 for the device classified as having a higher use frequency (S2: Yes) (S3). In this way, it is possible to distinguish between a frequently used device and a less frequently used device on the PLC 1 side.

  Then, the device data of each device is stored in the data memory 5 of the PLC 1 (S4). When the storage of the device data for all devices is completed (S5: Yes), the compiled instruction code is stored in the instruction memory 4. After storing (S6), the programming tool 2 ends the operation.

  Next, the operation of the PLC 1 after the operation of the programming tool 2 described above will be described with reference to the flowchart of FIG.

  The processor 3 corresponds to the device classified into the frequently used side (that is, the device information in the instruction memory 4) based on the device information stored in the instruction memory 4 at the start of execution of the instruction code. Device data is read from the data memory 5 to the built-in memory 6 (S10). As a result, device data of a frequently used device is stored in the built-in memory 6.

  Thereafter, the processor 3 sequentially reads instruction codes from the instruction memory 4 (S11) and executes arithmetic processing. At this time, if it becomes necessary to use the device by the instruction code (that is, read or write device data), the processor 3 accesses the memory in which the device data is stored. In short, when the device data to be read or written is stored in the built-in memory 6 (S12: Yes), the processor 3 accesses the built-in memory 6 (S13), while the device to be read or written is stored. If the data is not stored in the internal memory 6 (S12: No), the processor 3 directly accesses (DMA) the data memory 5 (S14).

  According to the configuration described above, the processor 3 executes arithmetic processing by accessing the built-in memory 6 when using a device whose device data is stored in the built-in memory 6, so that the processor 3 transfers the data to the data memory 5. Compared with the case of accessing, it is possible to speed up the arithmetic processing. Here, the device in which the device data is stored in the built-in memory 6 is automatically selected when it is compiled with the programming tool 2 and is frequently used for executing the instruction code. Can create a program without intentionally limiting the devices to be used.

  In addition, since device data that is frequently used is stored in the built-in memory 6 before the execution of the instruction code, the device data in the built-in memory 6 is executed during the execution of the instruction code as in the cache method (see the background art column). As compared with the case where the data is replaced with the device data in the data memory 5 at any time, the number of accesses between the processor 3 and the data memory 5 can be reduced to speed up the arithmetic processing.

  Furthermore, if there is no problem in the operation of the PLC 1 even if the operation processing of a device that is less frequently used is slow, a cheaper memory than the high-speed SRAM can be used as the data memory 5. There is also an advantage that the cost can be reduced.

  By the way, in the present embodiment, device data is stored in the internal memory 6 of the processor 3 only for devices classified as being frequently used in the compiler 8, but this is not restrictive, and the device data is stored in the internal memory 6. Changing means that allows the user to arbitrarily change the device in which is stored may be added to the programming tool 2. The changing unit arbitrarily changes the device in which the device data is stored in the built-in memory 6 in accordance with the user operation input from the input operation unit described above. Thereby, even when the frequency of use is low, when there is a device that requires high-speed arithmetic processing, high-speed arithmetic processing of the device can be realized by storing device data of the device in the built-in memory 6. Therefore, the user can create a program without being aware of the frequency of use of the device, and the degree of freedom of program creation is improved.

  In this embodiment, the programming tool 2 temporarily stores all device data in the data memory 5, and stores device data of frequently used devices in the built-in memory 6 of the processor 3 on the PLC 1 side. However, the present invention is not limited to this example, and device data of a frequently used device may be directly stored in the built-in memory 6 of the processor 3 from the programming tool 2.

(Embodiment 2)
The sequence control system of the present embodiment is a mode other than the mode in which the programming tool 2 stores device data of a frequently used device in the built-in memory 6 of the processor 3 as described in the first embodiment (hereinafter referred to as an automatic mode). The sequence control system of the first embodiment is different in that the operation mode can be selected.

  In the present embodiment, the programming tool 2 can operate in a manual mode in which the user arbitrarily selects a device in which device data is stored in the built-in memory 6 in addition to the automatic mode. Furthermore, a fixed selection mode (corresponding to the fixed selection method described in the background art) in which a device storing device data in the built-in memory 6 is a predetermined device, and a predetermined range of device data are stored in the built-in memory 6. If the processor 3 accesses the device data in the data memory 5 during the execution of the instruction code, the device data is most accessed among the device data stored in the built-in memory 6. Operation is possible even in a cache mode (corresponding to the cache method described in the Background Art section) in which device data is replaced with a smaller number of times.

  Switching between these four operation modes (automatic mode, manual mode, fixed selection mode, and cache mode) is performed by mode switching means (not shown) provided in the programming tool 2, and the user selects the mode before compiling. An arbitrary operation mode is selected by the switching means. The selected operation mode is set in a system register (not shown) or the like in the PLC 1.

  According to the configuration described above, since the user can select an arbitrary operation mode from the four operation modes, there is an advantage that the degree of freedom of program creation is improved.

  Other configurations and functions are the same as those of the first embodiment.

It is a schematic block diagram which shows the structure of Embodiment 1 of this invention. It is explanatory drawing which shows an example of the ladder program used for the same as the above. It is a flowchart which shows operation | movement of a programming tool same as the above. It is a flowchart which shows operation | movement of PLC same as the above.

Explanation of symbols

1 Programmable controller (PLC)
2 Programming Tool 3 Processor 4 Instruction Memory 5 Data Memory 6 Built-in Memory 8 Compiler (Classification Method)

Claims (3)

  A programmable controller that performs sequence control according to an instruction code including a plurality of devices, and a programming tool that sets the instruction code in the programmable controller, the programmable controller including a built-in memory and executing the instruction code, and the instruction code And an instruction memory for storing device data representing a device state and a data memory used as a work area when the processor executes the instruction code. Classifying means for classifying the device into a high-use device and a low-use device based on the frequency of use in executing the instruction code, and the state of the high-use device Device data And a distribution means for allocating the storage location of the device data so that the storage location of the device data representing the state of the infrequently used device is used as the data memory. And a sequence control system.   The sequence control system according to claim 1, wherein the programming tool includes a changing unit that changes the device in which the device data is stored in the built-in memory according to a user operation. The programming tool includes an automatic mode in which the device in which the device data is stored in the internal memory is the frequently used device, and a manual mode in which the user selects a device in which the device data is stored in the internal memory; A fixed selection mode in which a device in which device data is stored in the built-in memory is a predetermined device, and a predetermined range of device data are stored in the built-in memory. A mode switching unit capable of switching between a cache mode in which the device data is replaced with device data having the smallest number of accesses among the device data stored in the internal memory when access to the device data occurs. The sequence according to claim 1 Control system.

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