JP2010124664A - Ac output unstable state detector and power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the positive-negative unbalance of a current value, and to detect the unstable state of an AC output, even when the AC output is a low load. <P>SOLUTION: Maximum values on the plus side and the negative side of an AC current flowing through an inverter bridge circuit (2) are detected by the first and second maximum value detectors (102 and 104). The detection output of the unstable state is obtained by comparators 111 to 114 and a logic circuit 120, when the ratio representing unbalances at the maximum values on the plus side and the minus side continues for a fixed time within a fixed value range X (1>X>0). The operation of an inverter bridge circuit is stopped, in response to the detecting output under the unstable state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an AC output unstable state detection circuit and a power conversion device.

  When detecting AC output instability (phase loss state) in a power converter, conventionally, it detects the imbalance between the positive and negative voltage values of the output voltage of the power converter, and checks whether there is an AC output phase loss. Judging. However, as the output capacity increases, the insulation transformer used in the power conversion device also becomes larger, so that the transformer does not saturate at low load current, and the output voltage does not become unbalanced until the phase loss detection level.

In the single-phase AC output state, if the operation is continued in a state where phase loss cannot be detected at low load, the temperature of the insulation transformer installed on the AC output side may continue to rise, which may lead to scorching. Therefore, it is necessary to detect an open phase even when the AC output is at a low load. There is a technique described in Patent Document 1 as an apparatus for detecting a phase loss. However, even with this technology, there was anxiety in detecting phase loss even when the AC output was low.
Japanese Patent Application No. 8-331750

  Therefore, the present invention provides an AC output unstable state detection circuit and a power conversion device that detect positive / negative imbalance of current values, and can detect an unstable state of AC output even when the AC output is low in load. For the purpose.

  One aspect of the present invention is a first maximum value detection circuit for detecting a maximum value within a predetermined time of a current flowing on the plus side of the output of the current detector of the inverter bridge circuit, and a minus side of the output of the current detector. A second maximum value detection circuit that detects a maximum value of a reversal current obtained by inverting the current within a predetermined time, and a comparison that confirms that the detected current value of the first maximum value detection circuit is smaller than the first set value A comparator for confirming that the detected current value of the second maximum value detecting circuit is larger than a second set value, and the detected current value of the first maximum value detecting circuit is more than the second set value. A comparator that confirms that it is large, a comparator that confirms that the detected current value of the second maximum value detecting circuit is smaller than the first set value, and the output of the comparator that flows to the plus side Current is less than the first set value, minus side Logically determine when the current flowing is greater than or equal to the second set value and when the current flowing to the plus side is greater than or equal to the second set value and the current flowing to the minus side is less than or equal to the first set value. And a logic circuit that obtains an unstable (phase loss) state detection output.

  By the above means, the unstable state of the AC output can be detected even when the AC output is at a low load, and the safety of the apparatus can be maintained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention.

  Reference numeral 1 denotes a DC power source, and the DC power source 1 is connected to an inverter bridge circuit 2. The inverter bridge circuit 1 forms a full bridge circuit using, for example, an insulated gate bipolar transistor (hereinafter abbreviated as IGBT). That is, the IGBTs 31 and 32 are connected in series, and the IGBTs 33 and 34 are connected in series. The series circuits are connected in parallel, the collectors of the IGBTs 31 and 33 are connected to the plus terminal of the DC power supply 1, and the emitters of the IGBTs 32 and 34 are connected to the minus terminal of the DC power supply 1. The gate circuits 41-44 are connected to the gate electrodes of the IGBTs 31-34, respectively, and the turn-on and turn-off timings of the transistors can be controlled.

  In the inverter bridge circuit 2, the first state in which the IGBTs 31 and 34 are turned on and the IGBTs 33 and 32 are turned off, and the second state in which the IGBTs 31 and 34 are turned off and the IGBTs 33 and 32 are turned on are repeatedly DC- AC conversion output can be obtained.

  One output terminal of the inverter bridge circuit 2 is derived from a connection point between the IGBT 31 and the IGBT 32, and is connected to one terminal of the primary winding 81 of the insulating transformer 8 through the reactor 6. The other output terminal of the inverter bridge circuit 2 is derived from a connection point between the IGBT 33 and the IGBT 34, and is connected to the other terminal of the primary winding 81 of the insulating transformer 8. A filter capacitor 7 is connected in parallel with the primary winding 81.

  With the above configuration, unnecessary harmonics included in the output of the inverter bridge circuit 2 are suppressed by the filtering function of the reactor 6 and the filter capacitor 7. Both terminals of the secondary winding 82 of the insulating transformer 8 are led out as conversion output terminals OUT1 and OU2.

  Here, the current flowing through the inverter bridge circuit 2 is detected by a current detector 101 having a detection coil 50. The current detection output from the current detector 101 is input to the first maximum value detection circuit 102, inverted by the inversion circuit 203, and input to the second maximum value detection circuit 104.

  The first and second maximum value detection circuits 101 and 104 are circuits that detect a maximum value within a predetermined time in which a current detection output is predetermined.

  Next, the detected current value of the first maximum value detection circuit 102 is input to the comparator 111. This comparison 111 is a circuit for confirming that the detected current value of the first maximum value detecting circuit 102 is smaller than the first set value. The comparator 111 outputs a high level when the detected current value of the first maximum value detection circuit 102 is smaller than the first set value, and outputs a low level otherwise.

  The detected current value of the second maximum value detection circuit 104 is input to the comparator 112. The comparator 112 is a circuit for confirming that the detected current value of the second maximum value detecting circuit 104 is larger than the second set value. The comparator 112 outputs a high level when the detected current value of the second maximum value detection circuit 104 is larger than the second set value, and outputs a low level otherwise.

  The detected current value of the first maximum value detection circuit 102 is input to the comparator 113. This comparison 113 is a circuit for confirming that the detected current value of the first maximum value detecting circuit 102 is larger than the second set value. The comparator 113 outputs a high level when the detected current value of the first maximum value detection circuit 102 is larger than the second set value, and outputs a low level otherwise.

  Furthermore, the detected current value of the second maximum value detection circuit 102 is input to the comparator 114. This comparison 114 is a circuit for confirming that the detected current value of the second maximum value detecting circuit 104 is smaller than the first set value. The comparator 114 outputs a high level when the detected current value of the second maximum value detection circuit 104 is smaller than the first set value, and outputs a low level otherwise.

  The outputs of the above-described comparators 111 to 114 are input to the logic circuit 120. The logic circuit 120 uses the outputs of the comparators 111 to 114 when the current flowing on the plus side is equal to or less than the first set value and the current flowing on the minus side is equal to or greater than the second set value, and plus When the current flowing to the side is equal to or greater than the second set value and the current flowing to the minus side is equal to or less than the first set value, a logical determination is made to obtain an unstable (missing phase) state detection output. The logic circuit 120 calculates the logical sum of the AND circuit 115 that obtains the logical product of the outputs of the comparators 111 and 112, the AND circuit 116 that obtains the logical product of the outputs of the comparators 113 and 114, and the output of the AND circuits 115 and 116. An OR circuit 117 is obtained. The output of the OR circuit 117 is input to a control circuit (not shown) that controls the inverter bridge circuit 2 via, for example, a 5-second delay circuit 118. The control circuit temporarily stops the inverter operation of the converter when an unstable state is detected. The delay circuit 118 is provided as a circuit for determining that the unstable state has continued for a certain time.

  In the comparators 111 to 114, the first set value is 40A and the second set value is 80A. However, this value is an example, and is arbitrarily set according to the standard or demand of each power converter.

FIG. 2 is a diagram for explaining the operation example of the above apparatus in a simplified manner. FIG. 2 shows the current detection output of the current detector 101, the detection outputs of the maximum value detection circuits 101 and 104, and the determination output of the comparators 111-114. In the periods t2 and t3, the logic circuit 120 determines that it is unstable. That is, in the comparators 111 to 114 and the logic circuit 120, the ratio representing the unbalance between the positive and negative maximum values of the current detected by the maximum value detection circuits 101 and 104 is a predetermined value range X (1 > X> 0). When a predetermined time is continued, an unstable state detection output is obtained.

  The present invention is not limited to the above embodiment. In the above embodiment, the current in the inverter bridge circuit 2 is detected, but the current on the output side of the apparatus may also be detected.

  FIG. 3 shows still another embodiment of the present invention. Different parts from the embodiment of FIG. 1 will be described. A current detector 121 for detecting the current on the output side of the insulating transformer 8 via the detection coil 52 is added. The detection output of the current detector 121 is input to the comparator 122. The comparator 122 detects whether the current value is 40 A or less, and outputs a high level when the current value is 40 A or less. This determination output is input to the AND circuits 115 and 116. Other portions have the same configuration as the embodiment shown in FIG. According to the above embodiment, since the unstable state is further confirmed on the output side of the apparatus, it is possible to accurately detect the unstable state.

  FIG. 4 further shows another embodiment of the present invention. A different part from embodiment of FIG.1 and FIG.3 is demonstrated. In this embodiment, the control function of the system control unit 300 is shown. The instability detection output of the delay circuit 118 is input to the system control unit 300. When an unstable state occurs, the stop control unit 301 can stop the operation of the apparatus by controlling the gate circuit of the inverter bridge circuit 2. The stop control unit 301 may further output a warning when the operation of the apparatus is stopped. Further, a function of restarting when a certain time has elapsed may be provided.

  Further, the system control unit 300 includes a comparison value adjustment unit 302. The comparison value adjustment unit 302 can vary the compared values of the comparators 111 to 114 and 122. This variable is executed in response to a user operation input. When the comparison value is varied, the instability detection sensitivity with respect to the positive / negative unbalance amount of the current flowing through the inverter bridge circuit changes.

  Furthermore, the system control unit 300 includes a delay time adjusting unit 303, and the delay time adjusting unit 303 varies the delay time of the delay circuit 118. This variable is executed in response to a user operation input. When the delay time is changed, the time from when the instability is detected until the device is stopped changes.

  The user adjusts the delay time and the value to be compared, but measures the ratio of the positive / negative imbalance of the current flowing through the inverter bridge circuit, and sets the table data according to the measurement result. May be used to automatically control the delay time and the value to be compared.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

It is a circuit configuration explanatory view showing an embodiment of the present invention. 2 is a timing chart illustrating an operation example of the circuit illustrated in FIG. 1. It is circuit configuration explanatory drawing which shows other embodiment of this invention. It is circuit structure explanatory drawing which shows other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... Inverter bridge circuit, 6 ... Reactor, 7 ... Filter capacitor, 8 ... Insulation transformer, 31-34 ... IGBT, 41-44 ... Gate Circuit, 101, 121 ... Current detector, 102, 104 ... Maximum value detection circuit, 203 ... Inversion circuit, 111-114, 122 ... Comparator, 115, 116 ... AND circuit, 117 ... OR circuit, 118 ... delay circuit.

Claims (5)

A first maximum value detection circuit for detecting a maximum value within a predetermined time of a current flowing on the plus side of the output of the current detector of the inverter bridge circuit;
A second maximum value detection circuit for detecting a maximum value within a predetermined time of an inversion current obtained by inverting the current flowing on the negative side of the output of the current detector;
A first comparator for confirming that a detected current value of the first maximum value detecting circuit is smaller than a first set value;
A second comparator for confirming that a detected current value of the second maximum value detecting circuit is larger than a second set value;
A third comparator for confirming that a detected current value of the first maximum value detecting circuit is larger than a second set value;
A fourth comparator for confirming that a detection current value of the second maximum value detection circuit is smaller than a first set value;
Using the output of the comparator, when the current flowing on the plus side is equal to or less than the first set value and the current flowing on the minus side is in the first state equal to or greater than the second set value, the current flows to the plus side. A logic circuit for logically determining when the current is equal to or greater than the second set value and the current flowing on the negative side is equal to or less than the first set value to obtain an unstable state detection output;
An AC output unstable state detection circuit characterized by comprising:   2. The AC output unstable state detection circuit according to claim 1, further comprising a stop control unit that stops the operation of the inverter bridge circuit on condition that the output current is equal to or less than a predetermined value.   3. The AC output unstable state detection circuit according to claim 1, further comprising a comparison value adjustment unit that changes a comparison target current value of each of the first to fourth comparators.   3. The delay circuit for obtaining a delay time from the time when the unstable state detection output is obtained from the logic circuit until the operation of the inverter circuit is stopped, and the delay time of the delay circuit are changed. An AC output unstable state detection circuit comprising a delay time adjustment unit that In a power converter having an inverter bridge circuit and an insulating transformer for converting an output voltage of the inverter bridge circuit,
A first and second maximum value detection circuit for detecting a maximum value on the plus side and a minus side of the alternating current flowing in the inverter bridge circuit;
A circuit unit including a comparator and a logic circuit that obtains an unstable state detection output when the ratio representing the unbalance between the maximum value on the plus side and the minus side continues for a predetermined time in a predetermined value range X (1 > X> 0). When,
And a control unit that stops the operation of the interbridge circuit in response to the detection output of the unstable state.

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