JP2010124166A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably recover a normal lock state in a short period of time even when lock-off occurs to a DLL circuit. <P>SOLUTION: When a delay time of a delay circuit 13 is smaller than 1 cycle, a minimal delay time detection signal K2 is outputted by a delay detection circuit 15. When a phase frequency comparator 11 outputs an UP pulse, 2 NOR logic (NOR circuit 21) of the minimal delay time detection signal K2 and the UP pulse communicates a clock to an UP pulse counter 19, a lock-off detection signal K3 at an H level is outputted, and an L level is inputted to a reset period hold counter 17. Thus, the reset period hold counter 17 starts counter operation, sets the reset signal at the L level, short-circuits control voltage CNTL to source voltage for a prescribed period, and resets a phase frequency comparator 11. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for generating a sampling clock used in a semiconductor integrated circuit device, and more particularly to a technique effective for generating a sampling clock used in a digital camera or the like.

  A DLL (Delay Locked Loop) circuit is widely used for adjusting a sampling clock in a digital camera or the like. This DLL circuit is a negative feedback circuit including a delay element, a phase frequency comparator, a charge pump, and a loop filter as a basic configuration.

  The expected function of this circuit is to lock the output clock of the delay element to exactly one cycle behind the input clock. The negative feedback operation can generate a clock delay independent of process, power supply voltage, and temperature variations.

  Since the phase frequency comparator constituting the DLL circuit includes a latch circuit therein, it is necessary to reset the internal state of the latch circuit in advance in order for the DLL circuit to perform an expected operation so as to be delayed by one cycle.

  In addition, even if the operation is performed as expected by resetting at the start of the operation, for example, when a surge is applied and an unexpected pulse is generated in the two input clocks of the phase frequency comparator and its edge is detected, The normal lock will be lost.

  In that case, it is locked to a delay time of two cycles or an integer multiple cycle (pseudo lock). Or, it tries to lock in the 0th cycle and falls into a phenomenon that converges to the minimum delay time of the delay element. The former pseudo-lock can be countered by providing a delay detection circuit that detects the delay time of multiple clocks output from each stage of the variable delay line, but the latter phenomenon, that is, loss of lock requires a new countermeasure. It became.

  As a countermeasure technique against the loss of lock in the DLL circuit, for example, there is a technique of resetting the phase frequency comparator by paying attention to the control voltage that is the loop filter capacitance voltage value when the delay time of the delay element becomes the minimum value.

  When the delay element has a transfer characteristic in which the control voltage increases as the delay time becomes smaller, it is determined that the lock is lost when the delay element exceeds a certain voltage value. As a circuit configuration, a voltage comparator is provided, and a control voltage is given to one input, and a bias voltage arbitrarily set is given to the other input.

  For example, in a circuit whose power supply voltage is about 3V, about 2.5V is applied as a bias voltage, and when the control voltage is about 2.5V or more, it is determined that the lock is lost, and the phase frequency comparator and the control voltage are reset. . If it is less than about 2.5 V, it is determined that the lock is normal.

In this type of DLL circuit, when the control circuit starts supplying the first clock, the phase frequency comparator uses the edge of the second clock as the edge of the previous timing, and the first frequency immediately after this timing. The comparison operation with the clock edge is executed, and when the delay circuit is set to a delay time smaller than one clock cycle, the second clock edge is set one cycle later than the corresponding edge of the first clock signal. It is known that the delay time is stabilized to one cycle of an input clock by comparing with an edge (see, for example, Patent Document 1).
JP 2005-311543 A

  However, the present inventor has found that there is the following problem in the technique for preventing the loss of lock in the DLL circuit having the voltage comparison as described above.

  In other words, since the above-mentioned countermeasure against loss of lock requires supplying a bias voltage for determination from the outside, it is necessary to select the bias voltage setting in consideration of the power supply voltage, operating frequency, process, temperature, etc. There is a problem that is difficult.

  Further, since a new comparator for comparing the control voltage and the bias voltage must be provided, there arises a problem that the power consumption increases.

  Furthermore, in the technique of Patent Document 1, a separate oscillator is required to automatically return from lock loss to normal lock, which may cause problems such as layout area, power consumption, and noise increase. is there.

  An object of the present invention is to provide a technique capable of reliably returning to a normal lock state in a short time even when a lock loss occurs in a DLL circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a DLL circuit, comprising a plurality of delay elements connected in series, a delay circuit that delays a basic clock that is an input clock to the DLL circuit and outputs the delayed clock, and the delay circuit generates the delay circuit A phase frequency comparator that detects a phase difference between the delayed clock and the basic clock and generates an UP pulse or DOWN pulse, and a control voltage according to the UP pulse or DOWN pulse output from the phase frequency comparator The delay time of the delay element is reduced from the delay signal output from the delay element in the delay circuit and the charge pump circuit that generates the error, the lock failure that converges to the minimum value is detected, and the lock is restored from the failure to the normal lock And a clock generation unit having a lock deviation detection control means for performing control.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the lock loss detection control means takes in the voltage level of the delay signal output from each delay element, and outputs the minimum delay time detection signal when the combination of the taken voltage levels becomes a predetermined combination. A delay detection circuit that outputs a minimum deviation time detection signal from the delay detection circuit and an UP pulse from the phase frequency comparator. A loss detection unit and a reset control unit that outputs a reset signal for a predetermined period and resets the phase frequency comparator based on the lock loss detection signal output from the lock loss detection unit.

  Further, according to the present invention, the predetermined combination of voltage levels at which the delay detection circuit outputs the minimum delay time detection signal is a combination in which H level signals are output from all the delay elements.

  According to the present invention, the lock loss detection control means includes a switch unit that short-circuits the control voltage output from the charge pump circuit to the power supply voltage based on a reset signal output from the reset control unit. .

  Further, according to the present invention, the delay detection circuit outputs an 8 / 9-phase clock generated by the delay circuit as a minimum delay time detection signal in order to mask the glitch of the UP pulse.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) It is possible to surely eliminate the loss of lock and generate a stable and highly accurate sampling clock.

  (2) According to the above (1), when used in an electronic device such as a digital camera, the performance and reliability of the electronic device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of an image preprocessing unit used in a digital camera system or the like according to an embodiment of the present invention, and FIG. 2 shows an example of a configuration of a DLL circuit provided in the image preprocessing unit of FIG. FIG. 3 is a circuit diagram showing an example of a phase frequency comparator used in the DLL circuit of FIG. 2, FIG. 4 is a state transition diagram in the phase frequency comparator of FIG. 3, and FIG. FIG. 6 is an explanatory diagram showing an example of a clock waveform at each stage of the delay element provided in the DLL circuit of FIG. 2, and FIG. 7 is a phase frequency comparison provided in the DLL circuit of FIG. FIG. 8 is an explanatory diagram showing a circuit configuration example of a delay detection circuit provided in the DLL circuit of FIG. 2, and FIG. 9 is a minimum output from the delay detection circuit of FIG. It is explanatory drawing of a delay time detection signal.

  In the first embodiment, the image preprocessing unit 1 is a semiconductor integrated circuit device for image preprocessing used in, for example, a digital camera system. The image preprocessing unit 1 alternately samples the signal level captured from each pixel and the reference black level, and determines the signal level by comparing them.

  As shown in FIG. 1, the image preprocessing unit 1 includes a CDS (differential voltage detection unit) 2, a PGA (differential voltage amplification unit) 3, an A / D converter 4, a logic circuit 5, and a DLL circuit serving as a clock generation unit. 6 and the timing generator 7, which are configured as a semiconductor integrated circuit device on one chip.

  An image sensor 8 is connected to the CDS 2. The image sensor 8 is composed of, for example, a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor) sensor, and the like, and converts an image formed by the lens into a voltage signal. The image sensor 8 alternately outputs a reference black level and a captured signal level.

  CDS2 is a correlated double sampling circuit that samples the black level and signal level output from the image sensor 8 in synchronization with the black level sampling clock SPBLK and signal sampling clock SPSIG output from the DLL circuit 6, and Output the difference signal.

  The difference signal detected by the CDS 2 is amplified by the PGA 3, converted into a digital value by the A / D converter 4, and output. A DSP 9 is connected to the A / D converter 4. The DSP 9 processes the digital data output from the A / D converter 4.

  A DLL circuit 6 is connected to the logic circuit 5. The logic circuit 5 outputs a phase delay setting signal. A timing generator 7 is connected to the DLL circuit 6.

  The timing generator 7 generates and outputs a basic clock REF to be supplied to the DLL circuit 6 from an externally input external clock. The DLL circuit 6 includes a signal sampling clock SPSIG supplied to the CDS 2, a black level sampling clock SPBLK, a sampling signal supplied to the image sensor 8, a sampling signal supplied to the PGA 3, and an A / D converter from the input basic clock. 4 respectively generate sampling signals to be supplied.

  FIG. 2 is a block diagram showing an example of the configuration of the DLL circuit 6.

  As shown in the figure, the DLL circuit 6 includes a clock generator 10, a phase frequency comparator 11, a charge pump 12, a delay circuit 13, a loop filter capacitor 14, a delay detection circuit 15 constituting a lock loss detection control means, and a lock error. The lock disengagement detection control unit 16 is included in the detection control means.

  The lock detachment detection control unit 16 detects that a lock detachment described later has occurred in the DLL circuit 6, and performs control to return from the lock detachment to the normal lock.

  Further, the unlock detection control unit 16 includes a reset period holding counter 17, a control voltage shorting switch 18, an UP pulse counter 19, a counter control unit 20, a counter input control unit 21, and a counter reset control unit 22 serving as a reset control unit. It is composed of

  Further, the control voltage short-circuit switch 18, the UP pulse counter 19, the counter control unit 20, the counter input control unit 21, and the counter reset control unit 22 constitute an unlock detection unit.

  The basic clock output from the clock generator 10 is connected to one input section of the phase frequency comparator 11 and the input section of the delay detection circuit 15, respectively.

  The other input unit of the phase frequency comparator 11 is connected to the output unit of the delay circuit 13. The phase frequency comparator 11 compares the phase difference between the basic clock and the delay clock output from the delay circuit 13, and generates an UP pulse and a DOWN pulse.

  A charge pump 12 is connected to the phase frequency comparator 11, and a loop filter capacitor 14 is connected to the charge pump 12. The charge pump 12 generates a charging current or a discharging current in a pulsed manner in response to the UP or DOWN pulse output from the phase frequency comparator 11.

  The loop filter capacitor 14 time-integrates the charge / discharge current generated by the charge pump 12 to generate a control voltage CNTL and outputs the control voltage CNTL to the delay circuit 13. The delay circuit 13 outputs a delay clock delayed by a time corresponding to the voltage control CNTL with respect to the basic clock.

  The delay circuit 13 has a configuration in which a plurality of delay elements are connected in series, and the delay element includes, for example, two inverters connected in series. Furthermore, a plurality of input sections provided in the delay detection circuit 15 are connected to the output sections of the delay elements constituting the delay circuit 13.

  The delay detection circuit 15 detects the delay time of the delay element, and outputs a pseudo lock detection signal K1 and a minimum delay time detection signal K2 according to the detection result. The counter control unit 20 includes an inverter 20a and a negative OR circuit 20b.

  The counter control unit 20 controls the operation of the reset period holding counter 17 in accordance with the pseudo lock detection signal K1 and the signal state of the lock loss detection signal K3 output from the UP pulse counter 19.

  The pseudo lock detection signal K1 output from the delay detection circuit 15 is connected to the input part of the inverter 20a, and one input of the negative OR circuit 20b is connected to the output part of the inverter 20a. Are connected.

  The other input part of the negative logical sum circuit 20b is connected so that the unlock detection signal K3 is inputted, and one input of the reset period holding counter 17 is connected to the output part of the negative logical sum circuit 20b. Are connected.

  The counter input control unit 21 includes a negative OR circuit, and is connected so that the minimum delay time detection signal K2 output from the delay detection circuit 15 is input to one input unit of the negative OR circuit. The other input part of the NOR circuit is connected so that the UP pulse of the phase frequency comparator 11 is input.

  One input portion of the UP pulse counter 19 is connected to the output portion of the NOR circuit. The counter reset control unit 22 includes an AND circuit, and one input unit of the AND circuit is connected to an external reset terminal to which an external reset signal is input. An external reset signal from the external reset terminal is connected to be input to the reset period holding counter 17 as well.

  The reset signal output from the reset period holding counter 17 is input to the other input unit of the AND circuit, the control terminal of the control voltage shorting switch 18 serving as the switch unit, and the control terminal of the phase frequency comparator 11. So that each is connected.

  The output of the counter reset controller 22 is connected to the reset terminal of the UP pulse counter 19. The reset period holding counter 17 outputs a reset signal for a predetermined period based on an output signal from the counter control unit 20 or an external reset signal. The control voltage short-circuit switch 18 shorts the control voltage CNTL output from the charge pump 12 to the power supply voltage based on the reset signal output from the reset period holding counter 17.

  Here, the unlocking will be described.

  FIG. 3 shows an example of the phase frequency comparator 11 used in this embodiment, and FIG. 4 shows a state transition diagram in the phase frequency comparator 11. As shown in FIG. 3, the phase frequency comparator 11 includes inverters Iv1 to Iv3 and NAND circuits ND1 to ND9.

  In FIG. 4, circles in the drawing represent the internal state and the output state, and the states A and B shown in FIG. 3 and the states of the UP and DOWN terminals, which are outputs, are shown in order from the left in the circle. An arrow connecting the circles represents a state transition, and the condition for the state transition occurs when the state of the input terminals DEL and REF is a combination of H and L shown in the vicinity of the arrow.

  In addition, X in the states of DEL and REF which are input terminals indicates that either the H level or the L level may be used. Based on this state transition diagram and the timing chart of FIG. 5, the mechanism in which the locked state and the unlocking occur will be described below.

  In FIG. 5, from the top to the bottom, the basic clock terminal REF to which the basic clock input to the phase frequency comparator 11 is input and the delay clock from the delay circuit input to the phase frequency comparator 11 are input. The signal states of the delayed clock terminal DEL, the output terminal UP from which the UP pulse output from the phase frequency comparator 11 is output, and the output terminal DOWN from which the DOWN pulse output from the phase frequency comparator 11 is output are shown. This is a process of making a state transition from the locked state to the unlocked state when a hazard enters the delayed clock terminal DEL.

  In the locked state in which the edge of the basic clock terminal REF and the L level match, ideally, the state J101 and the state J104 continue to alternate alternately as shown in FIG. At this time, the UP pulse, which is the output of the phase frequency comparator 11, continues to output the H level, and the DOWN pulse continues to output the L level, and the charge pump is not charged or discharged.

  When the hazard enters the DEL terminal in the state J101, it can be read in correspondence with FIGS. 4 and 5 that the rise edge of the hazard is detected and the state transitions from the state J101 to the state J105.

  4 represents the state transition after the occurrence of the hazard in FIG. In the state J105, the charge pump performs a charging operation by outputting an UP pulse that is not originally output. As a result, the delay time of the delay element is reduced and converges to the minimum value. This phenomenon is out of lock.

  FIG. 6 shows the clock waveforms with the main number of stages, with the total number of stages of delay elements being 72. FIG. 6A shows a case where the lock is stably released, FIG. 6B shows a case where the lock is stable, and FIG. 6C shows a case where the lock is stable. Shows the case.

  FIG. 7 shows the transfer characteristics of the phase frequency comparator 11. FIG. 7 (a) is out of lock, FIG. 7 (b) is normal lock, and FIG. 7 (c) is in pseudo lock state. is there. In FIG. 7, the horizontal axis represents the delay time of the delay element, and the vertical axis represents the output of the phase frequency comparator, which is the pulse width of the UP pulse for charging the subsequent charge pump and the DOWN pulse for discharging the charge pump. .

  Referring to the normal lock state of FIG. 7B, which is an expected operation, when the delay time is one cycle, the UP pulse and the DOWN pulse are not generated, so that the transfer characteristics cross the horizontal axis.

  When the delay time is smaller than one cycle, a DOWN pulse is generated, so that a DOWN pulse corresponding to the transfer characteristic is generated. Conversely, when the delay time is longer than one period, an UP pulse corresponding to the transfer characteristic is generated.

  Similarly, in the case of the two-cycle delayed pseudo lock shown in FIG. 7C, the intersection of the transfer characteristic with the horizontal axis, that is, the lock point is delayed by two cycles, and the transfer characteristic is just translated in the horizontal axis direction. .

  7A corresponds to the fact that the lock point of the transfer characteristic is translated in the zero period due to the hazard. As a result, since the UP pulse is always output, the delay time of the delay element does not actually become zero, so that the delay time converges to the minimum value.

  Next, the operation of the DLL circuit 6 according to this embodiment will be described.

  The pseudo lock detection signal K1 output from the delay detection circuit 15 is activated when it is in the pseudo lock range according to the HL pattern that is the output voltage level of each stage of the delay elements of the delay circuit 13.

  This HL pattern is defined as the combination of the output voltage at the nth stage and the (n + 1) th stage of the delay element when the rising edge reaches the final stage of the delay element, being a combination of the H level and the L level.

  With the configuration of the delay detection circuit 15 shown in FIG. 8 described later, the voltage H or L level of each stage of the delay element is stored every time the rising edge reaches the final stage of the delay element. Based on the combination of the voltages stored in the flip-flops of these stages, the conditions for the pseudo lock are specified by the above-described HL pattern, and the lock loss is detected.

  First, the operation of each signal will be described with reference to FIG. 2 in the case of normal lock, pseudo lock, and unlock.

  First, in the normal lock state, the pseudo lock detection signal K is set to the H level, and the unlock detection signal K3 is set to the L level. Therefore, the input to the reset period holding counter 17 is held at the H level, the counter operation is not performed, and the reset signal is held at the H level.

  Thereafter, when a false lock is detected, the false lock detection signal K1 changes to the L level, so the input to the reset period holding counter changes to the L level and starts the counter operation, and the reset signal is set to the L level for a predetermined period. Then, the control voltage shorting switch 18 is turned ON to short the control voltage CNTL to the power supply voltage, and the phase frequency comparator 11 is reset.

  Next, a case where the lock is lost will be described.

  The minimum delay time detection signal K2 output from the delay detection circuit 15 is activated under the condition that the delay time of the delay element is shorter than one cycle by using the HL pattern similarly to the pseudo lock detection signal K1.

  For example, in order to specify a case where the delay time of the delay element is smaller than one cycle, it is only necessary to detect that the above-described HL pattern does not occur in all stages. When there is no HL pattern at these stored voltage levels, it can be specified that the delay time of the delay element is smaller than one cycle.

  Under the condition that the delay time of the delay element becomes smaller than one cycle, for example, the clock of the 8 / 9th phase is output to the UP pulse counter 19 as the minimum delay time detection signal K2 for the reason described later, and this is activated. And

  In other conditions where the delay time of the delay element is one cycle or more, that is, in the normal lock state or the pseudo lock state, no clock is output to the UP pulse counter 19 and an L fixed level is output.

  As described above, it is first determined whether or not the delay time of the delay element is smaller than one cycle based on whether or not the minimum delay time detection signal K2 is active, and whether or not the phase frequency comparator 11 outputs an UP pulse. In each case, it is determined whether the state is out of lock or in a transitional state in which the lock is normally locked and delayed by one cycle.

  That is, when the lock is lost, since the UP pulse is output from the phase frequency comparator 11, the clock is supplied to the UP pulse counter 19 by the 2NOR logic (negative OR circuit 21) of the minimum delay time detection signal K2 and the UP pulse. Then, the lock loss detection signal K3 is changed to H level, and the input to the reset period holding counter 17 is changed to L level to start the counter operation, and the reset signal is set to L level for a predetermined period to control voltage. CNTL is short-circuited to the power supply voltage, and the phase frequency comparator 11 is also reset.

  Further, if the UP pulse is not output, it is determined that the transition period is a normal lock and no reset is performed. However, in the normal lock state, an UP pulse is ideally not output, but in reality, a thin UP pulse like a glitch can be generated. Therefore, in order to mask this glitch, the above 8/9 phase clock is used. Logical OR with UP pulse.

  As a result, when the state with the minimum delay time is detected, if the lock is lost, the clock is applied to the UP pulse counter 19 and the counting is started. On the other hand, in the transition period in which normal lock is drawn, the L signal fixed level is applied to the UP pulse counter 19 and the counter does not operate.

  In this way, it is possible to discriminate between the case of a loss of lock and the case of a transition period during which a normal lock is drawn by the presence or absence of the counter operation. The number of times of the UP pulse counter 19 may be any number as long as it is plural, for example, 8 times is selected.

  Since the reset operation is also performed by pseudo lock, the logic of the lock release detection signal K3 and the pseudo lock detection signal K1 is obtained by the input of the reset period holding counter 17 by the inverter 20a and the negative OR circuit 20b of the counter control unit 20. .

  As described above, the mechanism for identifying the lock failure and the mechanism for recovering from the lock failure has been described.

  Next, the internal configuration of the delay detection circuit 15 that generates the minimum delay time detection signal newly required for countermeasures against lock loss will be described.

  First, in order to specify a case where the delay time of the delay element is smaller than one cycle, it is only necessary to detect that the above-described HL pattern does not occur in all stages.

  FIG. 8 is an explanatory diagram showing a circuit configuration example of the delay detection circuit 15. In FIG. 8, for example, the case where the delay element of the delay circuit 13 is composed of 72 stages is described.

As shown, the delay detection circuit 15 includes flip-flops 23 ₁ to 23 _n , inverters 24 _{1 to} 24 _m , NAND circuits 25 _{1 to} 25 _m , an AND circuit 26, an inverter 27, an OR circuit 28, and An AND circuit 29 is used.

The output terminals of the first to 72nd stages of the delay elements of the delay circuit 13 are connected to the data terminals D of the flip-flops 23 ₁ to 23 _n , respectively. In addition, the clock terminals CK of the flip-flops 23 ₁ to 23 _n are connected so that a delay clock output from the final delay element (the 72nd delay element) in the delay circuit 13 is input.

As a result, the output voltage levels of the stages of the delay elements connected in series immediately after the rising edge is output from the output terminal of the 72nd stage delay element, which is the final stage, are stored in the flip-flops 23 ₁ to 23 _n , respectively. Can do.

One input portion of the NAND circuit 25 _{1 to} 25 _m is connected to the output terminal Q of each of the flip-flops 23 ₁ to 23 _n−1 . Further, the input of inverter 24 ₁ to 24 _m, and the output terminal Q of the flip-flop 23 ₂ ~ 23 _n are connected, respectively, to the output of the inverter 24 ₁ to 24 _m, the NAND circuit 25 The other input units _{1 to} 25 _m are connected to each other, and the presence / absence of the n-th HL pattern is determined.

An input unit is connected to the logical product circuit 26 at the output units of the negative logical product circuits 25 _{1 to} 25 _m , and an input unit of the inverter 27 is connected to the output unit of the logical product circuit 26. .

  One input part of the OR circuit 28 is connected to the output part of the inverter 27, and the output part of the 64th stage delay element in the delay circuit 13 is connected to the other input part of the OR circuit 28. Has been.

  The signal output from the output section of the OR circuit 28 becomes the minimum delay time detection signal K2 in the delay detection circuit 15.

Further, the output units of the NOT logic product circuits 25 _{27 to} 25 _m are connected to the respective input units of the logical product circuit 29, and the signal output from the output unit of the logical product circuit 29 is a pseudo lock. The detection signal K1.

Since the NAND circuit 25 _{1 to} 25 _m outputs an L level if there is an HL pattern, and outputs an H level if there is no HL pattern, the AND circuit 26 detects that no HL pattern occurs in all stages. This can be realized by taking the logical product of the signals output from the negative logical product circuits 25 _{1 to} 25 _m .

  As a result, when the delay time of the delay element is smaller than one cycle, the HL pattern is not generated in all stages, so that the output of the AND circuit 26 becomes H level. The output of the logical product circuit 26 is inverted by an inverter 27, and a logical sum with an 8/9 phase clock, here, a clock output from a delay element at the 64th stage is taken by a logical sum circuit 28 to detect the minimum delay time. A signal K2 is generated.

  Accordingly, when the delay time of the delay element is smaller than one cycle, the 64th stage clock is output as the minimum delay time detection signal K2, and when the delay time is larger than one cycle, the H fixed level is output as the minimum delay time detection signal K2. To do.

  As described above, the minimum delay time detection signal K2 has a role of determining whether or not the delay time of the delay element is delayed by one cycle.

Further, the AND circuit 29 that generates the pseudo lock detection signal K1 is expected to operate at an H level output when the lock is normal and at an L level output when the pseudo lock is detected, and the HL detected by the flip-flops 23 ₁ to 23 _n. When the delay time of the delay element exceeds a certain value due to the pattern, it is determined as a pseudo lock.

  As a value to be determined, in the case of the phase frequency comparator 11 in the present embodiment, the maximum value of the normal lock region has two periods, but in order to secure a margin, the delay time is set to a delay time smaller than two periods.

For example, if the delay time is 1.4 cycles or more, it is determined as a pseudo lock area. In the case of FIG. 8, the circuit configuration for this purpose may be determined as a pseudo-lock region if an HL pattern is generated after the 27th stage of the delay element, and the net _{27 to} net 70 (negative logical product circuits 25 _{27 to} 25 shown in FIG. The logical product up to the output portion of _m ) can be realized by the logical product circuit 26.

  Next, the expected operation of the delay detection circuit 15 will be described.

  First, the reason why the 8/9 phase clock, in this case, the clock output from the 64th delay element is selected as the minimum delay time detection signal K2, will be described with reference to FIG.

  FIG. 9A shows a clock waveform in the case of the normal lock region, and FIG. 9B shows a clock waveform in the case of the lock release.

  In the normal lock area, if it is left as it is, it is normally locked with a delay of one cycle. Although the UP output of the phase frequency comparator 11 is ideally fixed at the H level, in reality, a glitch occurs as shown in FIG. 9, which may cause the UP pulse counter 19 to malfunction.

  In order to mask this glitch, the 64th stage clock was selected as the minimum delay time detection signal K2. The clock of the minimum delay time detection signal K2 may be any clock that can prevent this glitch. If glitch prevention can be achieved, clocks with other stages are possible.

  In this way, in the normal lock region, the UP pulse glitch is masked by the minimum delay time detection signal K 2, and a fixed L level is output to the UP pulse counter 19.

  If the lock is lost, the logic of the minimum delay time detection signal K2 and the UP pulse output is obtained by the negative OR circuit 21 to the UP pulse counter 19, and the clock generated by the logic is input to the counter. Start operation.

  The basic configuration of the UP pulse counter 19 that receives the minimum delay time detection signal K2 generated in the delay detection circuit 15, the UP pulse of the phase frequency comparator 11, and the clock generated by the negative OR circuit 21 as described above is input. As a countermeasure, a loss of lock is taken.

  In this example, the preceding stage of the input of the UP pulse counter 19 is configured using the negative OR circuit 21, but may be a logical OR circuit.

  As a result, according to the present embodiment, it is possible to determine the conditions specific to the loss of lock based on the combination (HL pattern) of the voltage levels in the delay elements in the delay circuit 13 which is a digital value. The loss of lock can be reliably eliminated.

  The present invention is suitable for a technique for generating a highly accurate sampling clock used in a digital camera or the like.

It is a block diagram of the image pre-processing part used for the digital camera system etc. by one embodiment of this invention. FIG. 2 is a block diagram illustrating an example of a configuration in a DLL circuit provided in the image preprocessing unit in FIG. 1. FIG. 3 is a circuit diagram illustrating an example of a phase frequency comparator used in the DLL circuit of FIG. 2. FIG. 4 is a state transition diagram in the phase frequency comparator of FIG. 3. It is a timing chart in the state transition of FIG. FIG. 3 is an explanatory diagram showing an example of a clock waveform at each stage of delay elements provided in the DLL circuit of FIG. 2. FIG. 3 is an explanatory diagram showing transfer characteristics of a phase frequency comparator provided in the DLL circuit of FIG. 2. FIG. 3 is an explanatory diagram illustrating a circuit configuration example of a delay detection circuit provided in the DLL circuit of FIG. 2. It is explanatory drawing of the minimum delay time detection signal output from the delay detection circuit of FIG.

Explanation of symbols

1 Image preprocessing unit 2 CDS
3 PGA
4 A / D converter 5 Logic circuit 6 DLL circuit 7 Timing generator 8 Image sensor 9 DSP
DESCRIPTION OF SYMBOLS 10 Clock generator 11 Phase frequency comparator 12 Charge pump 13 Delay circuit 14 Loop filter capacity 15 Delay detection circuit 16 Lock | disconnection detection control part 17 Reset period holding counter 18 Control voltage short switch 19 UP pulse counter 20 Counter control part 20a Inverter 20b NAND circuit 21 Counter input control unit 22 Counter reset control unit 23 ₁ to 23 _n flip-flops 24 _{1 to} 24 _m inverter 25 _{1 to} 25 _m NAND circuit 26 AND circuit 27 inverter 28 OR circuit 29 AND Circuit K1 Pseudo lock detection signal K2 Minimum delay time detection signal K3 Lock loss detection signal

Claims (5)

A delay circuit composed of a plurality of delay elements connected in series, arbitrarily delaying a basic clock and outputting it as a delayed clock signal;
A phase frequency comparator that detects a phase difference between a delayed clock signal generated by the delay circuit and a basic clock signal, and generates an UP pulse or a DOWN pulse;
A charge pump circuit for generating a control voltage in response to an UP pulse or a DOWN pulse output from the phase frequency comparator;
The delay time of the delay element is reduced from the delay clock signal output from each of the delay elements in the delay circuit, the lock loss that converges to the minimum value is detected, and control is performed to restore the lock to normal lock. A semiconductor integrated circuit device comprising: a clock generation unit including a lock loss detection control unit. The semiconductor integrated circuit device according to claim 1.
The unlock detection control means includes:
A delay detection circuit that takes in the voltage level of the delayed clock signal output from each of the delay elements, and outputs a minimum delay time detection signal when the combination of the voltage levels becomes an arbitrary combination;
When a minimum delay time detection signal is output from the delay detection circuit and an UP pulse is output from the phase frequency comparator, it is determined that lock is lost, and a lock error detection unit that outputs a lock error detection signal;
A semiconductor integrated circuit comprising: a reset controller that outputs a reset signal for an arbitrary period based on the lock deviation detection signal output from the lock deviation detection unit and resets the phase frequency comparator apparatus. The semiconductor integrated circuit device according to claim 2.
2. The semiconductor integrated circuit device according to claim 1, wherein any combination of the voltage levels at which the delay detection circuit outputs a minimum delay time detection signal is a combination in which H signals are output from all the delay elements. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The unlock detection control means includes:
A semiconductor integrated circuit device comprising: a switch unit that short-circuits a control voltage output from the charge pump circuit to a power supply voltage based on a reset signal output from the reset control unit. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The delay detection circuit includes:
8. A semiconductor integrated circuit device, wherein an 8/9 phase clock signal generated by the delay circuit is output as a minimum delay time detection signal.

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