JP2010122483A - Electrooptical panel, electrooptical device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrooptical panel, an electrooptical device, and an electronic device, attaining improvement in signal characteristic or reduction in noise, when high-speed serial transfer is adopted, by adjusting the structure of signal lines of an electrooptical substrate. <P>SOLUTION: First signal lines 11e-11h and second signal lines 11a-11d larger in width dimension than the first signal lines 11e-11d are formed on an element substrate 10 of the electrooptical device. Therefore, the second signal lines 11a-11d with large width dimension are used for high-speed serial transfer, while the first signal lines 11e-11h with small width dimension are used as signal lines for serial transfer with low transfer rate, compared with the second signal lines 11a-11d, or signal lines for parallel transfer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to an electro-optical panel, an electro-optical device, and an electronic apparatus. More specifically, the present invention relates to a technique for reducing impedance of a signal line formed on a substrate for an electro-optical device.

In recent years, LVDS (Low Vos) has been used as an interface for the purpose of reducing EMI noise.
ltage Differential Signaling) and other high-speed serial transfers are in the spotlight. A high-speed serial interface circuit (HSSSIF / High S) for performing such high-speed serial transfer
Peed Serial Interface) is realized by a transmitter circuit that transmits serialized data using a differential signal and a receiver circuit that differentially amplifies the differential signal (see Patent Document 1).

In addition, high-speed serial transfer has an advantage that the number of wirings can be reduced. For this reason, a foldable mobile phone or the like is provided with a first device portion provided with buttons for inputting a telephone number and characters, an electro-optical device such as an LCD (Liquid Crystal Display), and a camera device. When the second device part is connected by a connecting part such as a hinge, data transfer is performed between the first device part and the second device part via the connecting part such as the hinge. Is suitable.

When adopting such high-speed serial transfer, it is necessary to control the impedance of the high-speed line in terms of improving signal characteristics and reducing noise. Therefore, impedance control is required for flexible wiring boards and connectors connected to the electro-optical panel. What has been done is used.
JP 2005-257854 A

However, when high-speed serial transfer is adopted in an electro-optical device such as a liquid crystal device, there is a problem that signal characteristics cannot be sufficiently improved and noise cannot be sufficiently reduced even if impedance control of a flexible wiring board or connector is performed. .

As a result of studying such problems, the inventors of the present application have obtained new knowledge that the wiring formed on the substrate for the electro-optical device applies the design for the conventional MPU interface as it is.

Here, an object of the present invention is to optimize the signal line configuration of the electro-optic substrate, thereby improving the signal characteristics and reducing the noise when employing high-speed serial transfer, To provide an electro-optical device and an electronic apparatus.

In order to solve the above-described problems, in the electro-optical panel of the present invention, an electro-optical device substrate including a pixel array region in which a plurality of pixels are arrayed, and a first portion provided at an end of the electro-optical device substrate. One pad, a first signal line provided on the electro-optical device substrate and extending from the first pad toward a side where the pixel array region is located, and provided on an end portion of the electro-optical device substrate And a second signal provided on the electro-optical device substrate and extending from the second pad toward the side where the pixel array region is located with a width that is wider than the first signal line. The second signal line is a signal line for serial transfer, and the first signal line is
It is a signal line for serial transfer or a signal line for parallel transfer whose transfer speed is lower than that of the second signal line.

In the present invention, a first signal line and a second signal line having a wider width than the first signal line are formed on the electro-optical device substrate. For this reason, when an electro-optical device is configured using an electro-optical panel, the second signal line can be used as a signal line for high-speed serial transfer, and the second signal line can be used as the second signal line. It can be used as a signal line for serial transfer or a signal line for parallel transfer whose transfer speed is slower than that of the line. For this reason, when high-speed serial transfer is adopted, the impedance of the high-speed line is, for example, 100
Impedance control of high-speed lines such as Ω can be performed.
Therefore, when high-speed serial transfer is employed, signal characteristics can be improved and noise can be reliably reduced.

The present invention is particularly effective when applied to a case where the second signal line is a differential signal line that performs high-speed serial transfer by a set of two. In this case, one of the two differential signal lines is A configuration is adopted in which the width per book is wider than that of the first signal line.

In the present invention, the second pad may be formed of a conductive pattern having a wider width than the first pad.

In the present invention, the second pad may be composed of a plurality of conductive patterns having the same width dimension as the first pad.

An electro-optical device including an electro-optical panel to which the present invention is applied includes a terminal connected to an end portion of a signal line extending from the pixel array region, and an end located on the pixel array region side in the first signal line An integrated circuit device including a terminal connected to a portion and a terminal connected to an end located on the pixel array region side in the second signal line; a terminal connected to the first pad; and a second pad And a wiring board provided with terminals to be connected.

Such an electro-optical device is used in electronic devices such as a mobile phone, a car navigation system, and a personal computer.

Hereinafter, preferred embodiments of the present invention will be described in detail. Note that in the drawings referred to in the following description, the scales and the like are different in order to make each region recognizable on the drawing. Further, the number of electrodes and wirings is also shown in a simplified manner.

[Embodiment 1]
(Overall configuration of electro-optical device)
FIGS. 1A and 1B are plan views of an electro-optical device (liquid crystal device) to which the present invention is applied, as viewed from the counter substrate side, together with each component formed thereon, and HH thereof. It is a cross-sectional view. 1A and 1B, an electro-optical device 100 according to this embodiment includes a TN (Twisted Nema).
tic) mode, ECB (Electrically Controlled Birefringence) mode, VAN (Vert
It is an active matrix type liquid crystal device in ical aligned nematic mode. The electro-optical device 100 includes an electro-optical panel 30 (liquid crystal panel) in which a rectangular element substrate 10 (electro-optical device substrate) and a rectangular counter substrate 20 are bonded together with a sealing material 22 therebetween. A liquid crystal 1 f is held between the element substrate 10 and the counter substrate 20.

The sealing material 22 is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the element substrate 10 and the counter substrate 20 around them, and is used for setting the distance between the substrates to a predetermined value. Gap materials such as glass fiber or glass beads are blended. A liquid crystal injection port 25 is formed in the sealing material 22 by the interrupted portion, and after the liquid crystal 1f is injected, the sealing material 22 is sealed with a sealing material 27.

In the element substrate 10, the area surrounded by the sealing material 22 is a pixel array area 10a in which the pixel electrodes 2a and the pixel transistors 2c are arranged in a matrix, and the pixel electrode 2a.
An alignment film 19 is formed on the surface. On the counter substrate 20, a frame 26 (not shown in FIG. 1B) made of a light-shielding material is formed in the inner region of the sealing material 22, and the inner side is an image display region 1 a. Although not shown in the figure, a light shielding film called a black matrix or black stripe is formed in a region facing the vertical and horizontal boundary regions of each pixel on the counter substrate 20. An alignment film 29 is formed. In the counter substrate 20, an RGB color filter (not shown) is formed together with the protective film in a region facing each pixel of the element substrate 10, whereby the electro-optical device 1.
00 can be used as a color display device for electronic devices such as mobile computers, mobile phones, and liquid crystal televisions. The electro-optical device 100 is an IPS (In Plane Switch).
ing) mode or FFS (Fringe Field Switching) mode active matrix type liquid crystal device, the common electrode 28 is formed on the element substrate 10 side.

The element substrate 10 is larger than the counter substrate 20, and the element substrate 10 includes a protruding region 15 that protrudes from the end of the counter substrate 20 outside the sealing material 22. An IC mounting region 1 s is formed in the overhanging region 15, and the integrated circuit device 60 incorporating a scan driver (scanning line driving circuit), a data driver (source line driving circuit), and the like in the IC mounting region 1 s.
(Semiconductor integrated device) is mounted on COG (Chip On Glass).

In the projecting region 15 of the element substrate 10, a substrate connection region 1t is formed at an end adjacent to the IC mounting region 1s, and a flexible wiring substrate 70 as a wiring substrate is connected to the substrate connection region 1t. Yes. Various wiring patterns are formed on the flexible wiring board 70, and an electrical connection is made between the integrated circuit device 60 and the liquid crystal device controller 300 side. In this manner, the electro-optical device 100 is mounted on the electronic apparatus illustrated with reference to FIG.

Here, in the element substrate 10, from the pixel array region 10a toward the IC mounting region 1s, the lead wiring 16 extending from the scanning line 3a and the data line 6a described later through the outer region 1b of the pixel array region 10a, 17 is formed, and the ends of the routing wires 16 and 17 are
It is a pad for mounting the integrated circuit device 60.

In addition, the liquid crystal device controller 300 is provided between the IC mounting area 1s and the board connection area 1t.
A wiring group 11 for supplying a constant potential and a signal output from the through the flexible wiring board 70 to the integrated circuit device 60 is formed.

(Electrical configuration of electro-optical device)
FIG. 2 is an explanatory diagram showing an electrical configuration of the electro-optical device to which the present invention is applied. In the electro-optical device 100 of this embodiment, the element substrate 10 used in the electro-optical panel 30 includes a plurality of data lines 6a (source lines) and a plurality of scanning lines 3a (extending in a direction intersecting the data lines 6a). Gate line) and a plurality of pixels 10b corresponding to intersections of the data lines 6a and the scanning lines 3a, and the pixel array region 1 is formed by a region in which the pixels 10b are arrayed in a matrix.
0a is configured.

In each of the plurality of pixels 10b, a pixel electrode 2a and a pixel transistor 2c (field effect transistor) for controlling the pixel electrode 2a are formed. The data line 6a is electrically connected to the source of the pixel transistor 2c, and the scanning line 3a is electrically connected to the gate of the pixel transistor 2c. The pixel electrode 2a is electrically connected to the drain of the pixel transistor 2c. In the electro-optical device 100, the pixel transistor 2c is turned on for a certain period of time, so that an image signal supplied from the data line 6a is received. Write to the liquid crystal capacitance of each pixel 10b at a predetermined timing. An image signal of a predetermined level written in the liquid crystal capacitor is supplied to the pixel electrode 2 a formed on the element substrate 10 and the common electrode 28 on the counter substrate 20.
(See FIG. 1B) for a certain period. A holding capacitor 2e is added to the pixel electrode 2a, and the voltage of the pixel electrode 2a is held for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and the electro-optical device 100 capable of performing display with a high contrast ratio is realized. In this embodiment, the storage capacitor 2e
In the configuration, the capacitor line 3b is formed in parallel with the scanning line 3a. However, the storage capacitor 2e may be formed between the scanning line 3a in the previous stage.

(Configuration of integrated circuit device 60)
In the electro-optical device 100 of this embodiment, the integrated circuit device 60 includes a plurality of circuit blocks. In the integrated circuit device 60, the end portion on the side where the pixel array region 10a is located is a bump array region 66, 67 connected to the end portion of the lead wirings 16, 17 extending from the pixel array region 10a. . In the integrated circuit device 60, the end portion on the side where the substrate connection region 1 t is located is a bump array region 68 that is connected to a pad formed by the end portion of the wiring group 11.

In the present embodiment, in the integrated circuit device 60, the scan driver 610 is provided by a circuit block.
, Data driver 620, power supply circuit 630, gradation voltage generation circuit 640, logic circuit 68
0, a memory (not shown), and the like are configured. The memory is composed of a RAM or the like, and stores image data (display data) for at least one frame (one screen).

The logic circuit 680 includes a control circuit, a display timing control circuit, and the like. In the logic circuit 680, the control circuit has a function of generating various control signals and controls the entire apparatus. Specifically, the control circuit outputs a gradation adjustment data (γ correction data) for adjusting a gradation characteristic (γ characteristic) to the gradation voltage generation circuit 640, or a power supply circuit 630. The power supply adjustment data for adjusting the power supply voltage is output. The control circuit also has a function of controlling write / read processing to the memory. The display timing control circuit generates various control signals for controlling the display timing, and controls reading of image data from the memory to the electro-optical panel 30.

The data driver 620 is a circuit that generates a data signal for driving the data line 6 a of the electro-optical panel 30. Specifically, the data driver 620 receives image data (gradation data) from the memory, and receives a plurality of (for example, 256 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 640. A voltage corresponding to the image data is selected from the plurality of gradation voltages, and the data line 6 of the electro-optical panel 30 is selected as a data signal (data voltage).
output to a.

The scanning driver 610 is a circuit that generates a scanning signal for driving the scanning line 3 a of the electro-optical panel 30. Specifically, the scanning driver 610 sequentially shifts signals in a built-in shift register, and outputs a signal obtained by level-converting the shifted signal to each scanning line 3a of the electro-optical panel 30 as a scanning signal.

The power supply circuit 630 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor including a built-in boosting circuit. Then, the voltage obtained by boosting is supplied to the data driver 62.
0, supplied to the scan driver 610, the gradation voltage generation circuit 640, and the like.

A gradation voltage generation circuit (γ correction circuit) 640 is a circuit that generates a gradation voltage and supplies it to the data driver 620.

(Configuration for data transfer)
FIG. 3 is an explanatory diagram showing a configuration for high-speed serial transfer in the electro-optical device 100 and the electronic apparatus 1000 to which the present invention is applied. In FIG. 3, the integrated circuit device 60 is shown.
Is the client (C) side, the liquid crystal device controller 300 is the host (H) side, H is added to the end of the enable signal ENB, clock signal CK, and data signal DATA used in the liquid crystal device controller 300, and the integrated circuit device 60 side Enable signal ENB used in
C is added to the end of the clock signal CK and the data signal DATA.

As shown in FIGS. 2 and 3, the integrated circuit device 60 has an interface circuit as an interface circuit.
A first interface circuit 660 is provided that performs a clock-synchronized serial interface or a parallel interface with a relatively low interface speed.
The integrated circuit device 60 includes a second interface circuit 670 that performs high-speed serial transfer as an interface circuit.

In the present embodiment, the first interface circuit 660 is a parallel interface circuit, and outputs a write signal WR, a read signal RD, which are output from the liquid crystal device controller 300.
Commands such as a reset signal RS and a chip select signal CS are received. Here, the write signal WR, the read signal RD, the reset signal RS, and the chip select signal CS are CMOS (
Complementary Metal Oxide Semiconductor) A signal whose amplitude is larger than the level. Note that as signals corresponding to the first interface circuit 660, a write signal WR, a read signal RD, a reset signal RS, and a chip select signal CS are illustrated in FIG.
Examples of signals corresponding to the first interface circuit 660 include signals corresponding to an address, standby, and the like in addition to the above commands.

The second interface circuit 670 is a circuit that realizes high-speed serial transfer via a serial bus. Specifically, high-speed serial transfer with the liquid crystal device controller 300 is realized by current driving or voltage driving the differential signal line of the serial bus. In the second interface circuit 670, a signal having a small amplitude of the CMOS level (differential signal) is input. More specifically, small-amplitude differential data signals DP and DM and small-amplitude differential clock signals CKP and CKM are input, and differential data signals DP and DM are differentially amplified and differential clock signals CKP. , CKM differential amplification is performed, and data from the liquid crystal device controller 300 is received. Here, the differential data signals DP and DM include image data displayed on the electro-optical device 100. The differential data signals DP and DM are related to an inverted differential signal, and the differential clock signals CKP and CKM are related to an inverted differential signal.

For the purpose of performing such high-speed serial transfer, the second interface circuit 670 (receiving unit) includes a clock receiver circuit 671, a data receiver circuit 672, a serial-parallel conversion circuit (not shown), and the like. Further, the liquid crystal device controller 300 side includes a transmission unit 310 including a clock transmitter circuit 301, a data transmitter circuit 302, a parallel-serial conversion circuit (not shown), and the like. The clock transmitter circuit 301 outputs differential clock signals CKP and CKM, and the clock receiver circuit 671 performs differential amplification of the differential clock signals CKP and CKM, and uses the obtained clock CKC as a subsequent circuit. Output. Further, the data transmitter circuit 302 outputs differential data signals DP and DM, and the data receiver circuit 672 performs differential amplification of the differential data signals DP and DM, and outputs the obtained data signal DATAC to the subsequent stage. Output to the circuit.

Furthermore, in this embodiment, the ground potential GND and the drive potential Vd are supplied from the liquid crystal device controller 300 to the integrated circuit device 60.

(Configuration of wiring group 11)
FIG. 4 is an explanatory diagram showing a planar configuration of wirings and the like formed on the element substrate 10 in the electro-optical panel 30, the electro-optical device 100, and the electronic apparatus 1000 according to the first embodiment of the present invention. In the pad shown in FIG. 4, the area to which the integrated circuit device 60 and the flexible wiring board 70 are connected is hatched.

In the electro-optical device 100 and the electronic apparatus 1000 according to the present embodiment, the data transfer and power supply described with reference to FIG. 3 are performed in accordance with the liquid crystal device controller 300 and the electro-optical device as shown in FIGS. This is performed by the flexible wiring board 70 connecting the panel 30 and the wiring group 11 formed on the element substrate 10. Here, when high-speed serial transfer is employed, unlike parallel transfer, high-speed line impedance control is necessary in terms of improving signal characteristics and reducing noise. In particular, in the case of high-speed serial transfer, since the amplitude of the inverted differential signal is small, if the impedance is not appropriate, the amplitude may be reduced and the signal level may be inverted.

Therefore, in this embodiment, a flexible wiring board 70 or a connector (not shown) that has been subjected to impedance control is used. In the element substrate 10, the structure described below with reference to FIGS. 3 and 4 is adopted for the wiring group 11.

As shown in FIGS. 3 and 4, at the end of the element substrate 10, the substrate connection region 1t has
First pads 12e to 12h to which a write signal WR, a read signal RD, a reset signal RS, a chip select signal CS and the like are supplied from the liquid crystal device controller 300 via the flexible wiring board 70 are formed, and the first pads 12e to 12h are formed. Flexible wiring board 7
Zero terminals are connected by an anisotropic conductive film or the like. In the element substrate 10, the first signal lines 11 e to 11 h extend from the first pads 12 e to 12 h toward the IC mounting region 1 s (the side where the pixel array region 10 a is located). In the IC mounting region 1s, the first signal line 11e
˜11h are pads 13e to 13h for mounting the integrated circuit device 60, and bumps of the integrated circuit device 60 are connected to the pads 13e to 13h by an anisotropic conductive film or the like. In this way, the first pads 12e to 12h and the first signal lines 11e to 11h.
h and the pads 13e to 13h are electrically connected to the first interface circuit 660.

Here, the first pad 12e and the first signal line 11e correspond to the write signal WR, the first pad 12f and the first signal line 11f correspond to the read signal RD, and the first pad 12g and the first signal line 11g Corresponding to the reset signal RS, the first pad 12h and the first signal line 11
h corresponds to the chip select signal CS.

In the substrate connection region 1t, second pads 12a to 12d to which the differential clock signals CKP and CKM and the differential data signals DP and DM are supplied from the liquid crystal device controller 300 through the flexible wiring board 70 are formed. The terminals of the flexible wiring board 70 are connected to the second pads 12a to 12d by an anisotropic conductive film or the like. The element substrate 10
Then, the second signal lines 11 a to 11 are directed from the second pads 12 a to 12 d to the IC mounting region 1 s.
d is extended. In the IC mounting region 1 s, the ends of the second signal lines 11 a to 11 d are pads 13 a to 13 d for mounting the integrated circuit device 60.
Bumps of the integrated circuit device 60 are connected to a to 13d by an anisotropic conductive film or the like. In this way, the second pads 12a to 12d, the second signal lines 11a to 11d, and the pad 13
a to 13 d are electrically connected to the second interface circuit 670.

Here, the second pad 12a and the second signal line 11a correspond to the differential clock signal CKP, the second pad 12b and the second signal line 11b correspond to the differential clock signal CKM,
A pair of the second signal line 11a and the second signal line 11b is a pair of differential signal lines 1 for high-speed serial transfer.
1x is configured. The second pad 12c and the second signal line 11c correspond to the differential data signal DP, and the second pad 12d and the second signal line 11d correspond to the differential data signal DM. A pair of the second signal lines 11d constitutes a differential signal line pair 11y for high-speed serial transfer. In this embodiment, the second signal lines 11a and 11b constituting the differential signal line pair 11x extend at adjacent positions, and the second signal line 1 constituting the differential signal line pair 11y.
1c and 11d extend at adjacent positions.

Further, the substrate connection region 1t is supplied with the ground potential GND and the drive potential Vd from the liquid crystal device controller 300 via the flexible wiring board 70.
12k is formed, and the terminals of the flexible wiring board 70 are connected to the third pads 12i to 12k by an anisotropic conductive film or the like. In the element substrate 10, the third pad 12 i
The constant potential lines 11i to 11k extend from ˜12k toward the IC mounting region 1s. In the IC mounting region 1s, the ends of the constant potential lines 11i to 11k are pads 13i to 13k for mounting the integrated circuit device 60, and the integrated circuit device 6 is connected to the pads 13i to 13k.
Zero bumps are connected by an anisotropic conductive film or the like.

In this embodiment, two wirings are used to supply the drive potential Vd, and the third pad 1
2i, 12j and constant potential lines 11i, 11j correspond to the drive potential Vd. Third pad 12
k and the constant potential line 11k correspond to the ground potential GND. In the present embodiment, the constant potential lines 11i to 11k are arranged so as to sandwich the differential signal line pair 11x and 11y for high-speed serial transfer on both sides, and the differential signal line pair 11x for high-speed serial transfer. 11y is arranged on both sides, and has a function of reducing noise emitted from the differential signal line pair 11x, 11y.

Each of the wiring groups 11 is formed at the same time as the conductive film constituting the pixel transistors 2c, the data lines 6a, and the scanning lines 3a in the pixel array region 10a. The above-described pad is configured by laminating conductive films constituting the pixel electrode 2a.

In the electro-optical panel 30 configured as described above, the widths of the first signal lines 11e to 11h and the constant potential lines 11i to 11k are W1. On the other hand, the width dimension of the second signal lines 11a to 11d is W2, and the width dimensions W1 and W2 are as follows: W1 <W2
The relationship is set. For example, the second signal lines 11a to 11d used for high-speed serial transfer
Of the first signal lines 11e to 11h and the constant potential lines 11i to 11k.
It is wider than 1. For example, the width dimension W2 of the second signal lines 11a to 11d is set to the first signal lines 11e to 11e.
1h, and about twice or more the width dimension W1 of the constant potential lines 11i to 11k. More specifically, the width dimension W1 of the first signal lines 11e to 11h and the constant potential lines 11i to 11k is 100.
μm, the gap is 50 μm, and the width dimension W2 of the second signal lines 11a to 11d is 150 μm.
The gap is 50 μm.

Here, the first pads 12e to 12h have the same width dimension W1 as the first signal lines 11e to 11h.
The third pads 12i to 12k have the same width W1 as the constant potential lines 11i to 11k. The second pads 12a to 12d have the same width dimension W2 as the second signal lines 11a to 11d.
It is. For this reason, the width dimension W2 of the second pads 12a to 12d used for high-speed serial transfer is wider than the width dimension W1 of the first pads 12e to 12h and the third pads 12i to 12k.

The pads 13e to 13h have the same width dimension W1 as the first signal lines 11e to 11h, and the pads 13i to 13k have the same width dimension W1 as the constant potential lines 11i to 11k. Also,
The pads 13a to 13d have the same width dimension W2 as the second signal lines 11a to 11d. Therefore, the width dimension W2 of the pads 13a to 13d used for the high-speed serial transfer is set to the pads 13e to 1d.
It is wider than the width dimension W1 of 3k.

(Main effects of this form)
As described above, in the electro-optical panel 30, the electro-optical device 100, and the electronic apparatus 1000 according to the present embodiment, the first signal lines 11e to 11h are formed on the element substrate 10 (electro-optical device substrate).
The second signal lines 11a to 11d having a width wider than the first signal lines 11e to 11h are formed. Therefore, the second signal lines 11a to 11d having a large width can be used for high-speed serial transfer, and the first signal lines 11e to 11h having a small width can be used as signal lines for parallel transfer. For this reason, when high-speed serial transfer is employed, the impedance of the high-speed line can be controlled, for example, the impedance of the high-speed line can be set to 100Ω. Therefore, according to this embodiment, when high-speed serial transfer is employed, it is possible to reliably improve signal characteristics and reduce noise.

[Embodiment 2]
FIG. 5 is an explanatory diagram illustrating a planar configuration of wirings and the like formed on the element substrate 10 in the electro-optical panel 30, the electro-optical device 100, and the electronic device 1000 according to the second embodiment of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, portions having common functions are denoted by the same reference numerals and description thereof is omitted.

Also in the electro-optical device 100 and the electronic apparatus 1000 according to the present embodiment, in the same manner as in the first embodiment, in terms of improving signal characteristics and reducing noise when high-speed serial transfer is employed, FIG.
The configuration shown in FIG. 5 is adopted.

As shown in FIGS. 3 and 5, first, the element substrate 10 is provided with a write signal WR, a read signal RD, a reset signal RS, and a chip from the liquid crystal device controller 300 via the flexible wiring board 70, as in the first embodiment. First signal line 11e to which a select signal CS and the like are supplied
... 11 h are formed, and the first signal lines 11 e to 11 h are electrically connected to the first interface circuit 660. Further, in the element substrate 10, as in the first embodiment,
Differential clock signal C from the liquid crystal device controller 300 via the flexible wiring board 70
Second signal lines 11a to 11d to which KP and CKM and differential data signals DP and DM are supplied are formed. The second signal lines 11a to 11d are connected to the second interface circuit 670.
Is electrically connected. Further, as in the first embodiment, constant potential lines 11i to 11k to which the ground potential GND and the driving potential Vd are supplied from the liquid crystal device controller 300 via the flexible wiring substrate 70 are formed on the element substrate 10.

In this embodiment, the width dimension of the second signal lines 11a to 11d is W2, whereas the width dimension of the first signal lines 11e to 11h is W1, and the width dimensions W1 and W2 are expressed as W1 <W2 below.
The relationship is set.

Here, the width dimensions of the constant potential lines 11i to 11k are W3, and the width dimensions W1, W2, and W3 are as follows: W1 <W2 <W3
The relationship is set.

Thus, in this embodiment, the width W2 of the second signal lines 11a to 11d is equal to the constant potential line 11i.
Although narrower than the width dimension W3 of ˜11k, it is wider than the width dimension W1 of the first signal lines 11e to 11h.

The first pads 12e to 12h and the pad 1 corresponding to the first signal lines 11e to 11h
3e to 13h have the same width as the first signal lines 11e to 11h. The second signal line 11a
The second pads 12a to 12d and the pads 13a to 13d corresponding to ˜11d have the same width as the second signal lines 11a to 11d. Further, the third pads 12i to 12k and the pads 13i to 13k corresponding to the constant potential lines 11i to 11k have the same width as the constant potential lines 11i to 11k.

As described above, also in the present embodiment, in the electro-optical panel 30, the electro-optical device 100, and the electronic apparatus 1000 according to the present embodiment, the first signal lines 11e to 11e on the element substrate 10 (electro-optical device substrate).
1h and second signal lines 11a to 11d having a wider width than the first signal lines 11e to 11h are formed. Therefore, the second signal lines 11a to 11d having a large width can be used for high-speed serial transfer. Therefore, when high-speed serial transfer is employed, signal characteristics can be improved and noise can be reliably reduced.

[Embodiment 3]
FIG. 6 is an explanatory diagram illustrating a planar configuration of wirings and the like formed on the element substrate 10 in the electro-optical panel 30, the electro-optical device 100, and the electronic device 1000 according to the third embodiment of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, portions having common functions are denoted by the same reference numerals and description thereof is omitted.

Also in the electro-optical device 100 and the electronic apparatus 1000 according to the present embodiment, in the same manner as in the first embodiment, in terms of improving signal characteristics and reducing noise when high-speed serial transfer is employed, FIG.
The configuration shown in FIG. 6 is adopted.

As shown in FIGS. 3 and 6, first, the element substrate 10 is provided with the write signal WR, the read signal RD, the reset signal RS, and the chip from the liquid crystal device controller 300 via the flexible wiring board 70 as in the first embodiment. First signal line 11e to which a select signal CS and the like are supplied
... 11 h are formed, and the first signal lines 11 e to 11 h are electrically connected to the first interface circuit 660. Further, in the element substrate 10, as in the first embodiment,
Differential clock signal C from the liquid crystal device controller 300 via the flexible wiring board 70
Second signal lines 11a to 11d to which KP and CKM and differential data signals DP and DM are supplied are formed. The second signal lines 11a to 11d are connected to the second interface circuit 670.
Is electrically connected. Further, as in the first embodiment, constant potential lines 11i to 11k to which the ground potential GND and the driving potential Vd are supplied from the liquid crystal device controller 300 via the flexible wiring substrate 70 are formed on the element substrate 10.

In the electro-optical panel 30 configured as described above, the width of the second signal lines 11a to 11d and the constant potential lines 11i to 11k is W1, whereas the width of the second signal lines 11a to 11d is W2. Yes, width dimensions W1 and W2 are below W1 <W2
The relationship is set.

In this embodiment, the first pads 12e to 12h have the same width dimension W1 as the first signal lines 11e to 11h, and the third pads 12i to 12k have the same width dimension W1 as the constant potential lines 11i to 11k. . On the other hand, the second signal line 11a includes two second pads 12a1 and 12a2.
The second signal line 11b is formed to straddle the two second pads 12b1 and 12b2. In addition, the second signal line 11c includes two second pads 12c1 and 12c.
The second signal line 11d is formed so as to straddle c2, and the two second pads 12d1, 12d2
It is formed to straddle. Here, the first pads 12e to 12h and the second pads 12a1.
, 12a2, second pads 12b1, 12b2, second pads 12c1, 12c2, second pads 12d1, 12d2, and third pads 12i-12k are formed at equal pitches with equal width dimensions.

The pads 13e to 13h have the same width dimension W1 as the first signal lines 11e to 11h, and the pads 13i to 13k have the same width dimension W1 as the constant potential lines 11i to 11k. On the other hand, the second signal line 11a is formed so as to straddle the two pads 13a1 and 13a2.
The second signal line 11b is formed so as to straddle the two pads 13b1 and 13b2. The second signal line 11c is formed so as to straddle the two pads 13c1 and 13c2,
The signal line 11d is formed so as to straddle the two pads 13d1 and 13d2. Here, the pads 13a to 13k are formed at equal pitches with equal width dimensions.

As described above, also in the present embodiment, in the electro-optical panel 30, the electro-optical device 100, and the electronic apparatus 1000 according to the present embodiment, the first signal lines 11e to 11e on the element substrate 10 (electro-optical device substrate).
1h and second signal lines 11a to 11d having a wider width than the first signal lines 11e to 11h are formed. Therefore, the second signal lines 11a to 11d having a large width can be used for high-speed serial transfer. Therefore, when high-speed serial transfer is employed, signal characteristics can be improved and noise can be reliably reduced.

[Other configurations]
In the above embodiment, the second signal lines 11a to 11d having a large width are used for high-speed serial transfer, and the first signal lines 11e to 11h having a small width are used for parallel transfer.
The first signal lines 11e to 11h having a narrow width may be used for serial transfer having a lower transfer speed than the second signal lines 11a to 11d. In the above embodiment, high-speed serial transfer is used for transferring image data and clocks. However, the present invention may be applied when high-speed serial transfer is used for transferring various commands.

In the above embodiment, a liquid crystal device is exemplified as the electro-optical device 100, but the present invention may be applied to an organic electroluminescence device or a plasma display device.

[Example of mounting on electronic devices]
Next, an electronic apparatus to which the electro-optical device 100 according to the above-described embodiment is applied will be described. FIG. 7A shows a configuration of a mobile personal computer including the electro-optical device 100. The personal computer 2000 is an electro-optical device 1 as a display unit.
00 and main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 7B shows a configuration of a mobile phone provided with the electro-optical device 100. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled. FIG. 7C shows a portable information terminal (PDA: Personal D) to which the electro-optical device 100 is applied.
igital Assistants). The information portable terminal 4000 includes a plurality of operation buttons 400.
1 and a power switch 4002, and the electro-optical device 100 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 100.

As an electronic apparatus to which the electro-optical device 100 is applied, in addition to those shown in FIG. 7, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, Electronic devices such as a calculator, a word processor, a workstation, a videophone, a POS terminal, and a bank terminal are included. The electro-optical device 100 described above can be applied as a display unit of these various electronic devices.

(A), (b) is the top view which looked at the electro-optical apparatus (liquid crystal device) to which this invention is applied from the opposite substrate side with each component formed on it, and its HH 'cross section FIG. It is explanatory drawing which shows the electrical structure of the electro-optical apparatus to which this invention is applied. FIG. 7 is an explanatory diagram illustrating a configuration for high-speed serial transfer in an electro-optical device and an electronic apparatus to which the present invention is applied. In the electro-optical panel, the electro-optical device, and the electronic apparatus according to the first embodiment of the present invention, it is an explanatory diagram illustrating a planar configuration such as wiring formed on an element substrate. FIG. In the electro-optical panel, the electro-optical device, and the electronic device according to the second embodiment of the present invention, it is an explanatory diagram showing a planar configuration such as wiring formed on the element substrate. In the electro-optical panel, the electro-optical device, and the electronic device according to the third embodiment of the present invention, it is an explanatory diagram showing a planar configuration such as wiring formed on an element substrate. It is explanatory drawing of the electronic device using the electro-optical apparatus which concerns on this invention.

Explanation of symbols

10 .... Element substrate (electro-optical device substrate), 11 .... Wiring group, 11a to 11d ..., second signal line, 11e to 11h ..., first signal line, 11i to 11k ..., constant potential line, 11x, 11y
Differential signal line pairs, 12a to 12d, second pad, 12e to 12h, first pad, 12
i to 12k ··· Third pad, 20 · · Opposing substrate, 30 · · Electro-optical panel, 60 · · Integrated circuit device, 70 · · Flexible wiring substrate (wiring substrate), 100 · · Electro-optical device, 10
00..Electronic equipment, 660..First interface circuit, 670..Second interface circuit

Claims (6)

An electro-optical device substrate including a pixel array region in which a plurality of pixels are arrayed;
A first pad provided at an end of the electro-optical device substrate;
A first signal line provided on the electro-optical device substrate and extending from the first pad toward a side where the pixel array region is located;
A second pad provided at an end of the electro-optical device substrate;
A second signal line provided on the electro-optical device substrate and extending from the second pad toward the side where the pixel array region is located with a width that is wider than the first signal line;
Have
The second signal line is a signal line for serial transfer,
The first signal line is a serial transfer signal line whose transfer speed is lower than that of the second signal line,
Alternatively, the electro-optical panel is a signal line for parallel transfer. The second signal line includes a differential signal line that performs high-speed serial transfer,
2. The electro-optical panel according to claim 1, wherein the width of each differential signal line is wider than that of the first signal line. The electro-optical panel according to claim 1, wherein the second pad is formed of a conductive pattern having a width that is wider than that of the first pad. The electro-optical panel according to claim 1, wherein the second pad includes a plurality of conductive patterns having the same width as the first pad. An electro-optical device comprising the electro-optical panel according to claim 1,
A terminal connected to an end of a signal line extending from within the pixel array region, a terminal connected to an end located on the pixel array region side in the first signal line, and the pixel array in the second signal line An integrated circuit device having a terminal connected to an end located on the region side;
A wiring board comprising a terminal connected to the first pad and a terminal connected to the second pad;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 5.

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