JP2010114514A - Semiconductor integrated circuit having connection detecting function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the connection of a semiconductor integrated circuit including a video signal processing circuit and a video apparatus without providing a terminal for connection detection. <P>SOLUTION: The semiconductor integrated circuit includes a signal processing circuit, an output terminal for outputting the output video signals of the signal processing circuit to the outside, a pull-up resistor connected to the output terminal, an input signal detection circuit for detecting whether or not video signals are input to the signal processing circuit, a simulation output stage for outputting a current corresponding to a current outputted from the signal processing circuit, a connection current detection circuit for detecting an output current value from the simulation output stage, and a control circuit. The control circuit turns off the signal processing circuit and determines whether or not the video apparatus is connected to the output terminal on the basis of the voltage of the output terminal when the video signals are not input to the signal processing circuit, and determines whether or not the video apparatus is connected to the output terminal on the basis of the value of the current detected in the connection current detection circuit when the video signals are input. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a function of detecting connection between a semiconductor integrated circuit including a video signal processing circuit and video equipment.

  As a connection detection circuit for detecting a connection between a semiconductor integrated circuit built in a portable electrical device such as a digital camera, a camcorder, or a mobile phone and a video device main body such as a TV or a DVD player, it has been described in Patent Document 1, for example. A connection detection circuit is known. This connection detection circuit detects the connection between the video equipment body and its peripheral video equipment.

  FIG. 8 is a circuit diagram showing the configuration of this conventional connection detection circuit. In FIG. 8, the applicant appropriately adds components necessary for explanation to the circuit diagram described in Patent Document 1. In FIG. 8, the signal processing circuit 201 of the video equipment main body is built in a semiconductor integrated circuit 235. The video signal is input to the signal processing circuit 201 via the DC cut capacitor 202 and amplified there. This amplified video signal passes through the DC cut capacitor 136 and the terminating resistor 205, and is input to the peripheral video equipment 232 when the connector (cable 13) is connected. Here, reference numeral 210 indicates a monitor terminal.

  In FIG. 8, the voltage V1 at the input terminal and the voltage V2 at the output terminal of the termination resistor 205 change as follows depending on whether or not the connector is connected.

  When the connector is connected, the voltage V1 and the voltage V2 are obtained by dividing the bias voltage Vs by the bias power source 234 by the resistance value Rs of the resistor 233, the resistance value Rt of the resistor 205, and the resistance value Rr of the resistor 206. Become a thing. Specifically, it is as follows.

V1 ≒ Vs × (Rt + Rr) / (Rs + Rt + Rr)
V2 ≒ Vs × Rr / (Rs + Rt + Rr)
When the connector is not connected, the voltage V1 and the voltage V2 are equal to each other.

V1 = V2
Here, since Rt and Rr have the same resistance value (75Ω), V1 = 2 × V2 when the connector is connected. In other words, V2 = V1 / 2. Therefore, by comparing the voltage V2 with a reference voltage that is 2/3 of the voltage V1, it is possible to detect whether or not the connector is connected depending on whether or not the voltage V2 is lower than the reference voltage.

In this conventional example, the voltage V 1 is divided by a resistor 207 and a resistor 208 to create a reference voltage, which is input to the + input terminal of the comparator 204. Here, since the resistance value Re of the resistor 208 is twice the resistance value Rd of the resistor 207, the reference voltage is V1 × 2/3. On the other hand, the voltage V 2 is input to the negative input terminal of the comparator 204. Thereby, when the connector is connected, the comparator 204 outputs a positive voltage because the voltage V2 (= V1 / 2) is smaller than the reference voltage (= V1 × 2/3), and the connector is connected. If not, the voltage V2 (= V1) is larger than the reference voltage (= V1 × 2/3), so a negative voltage is output. Thereby, the comparator 204 can detect whether or not the connector is connected. Such a conventional example can realize a power reduction function in a battery-driven video device.
Patent No. 3393409 Patent Publication (refer to FIG. 1 in particular)

  However, in the connection detection circuit described in Patent Document 1, since it is necessary to monitor the voltage of the termination resistor 205 on the semiconductor integrated circuit 235 side, it is necessary to provide the monitoring terminal 210.

  The present invention has been made to solve such problems, and can detect a connection between a semiconductor integrated circuit including a video signal processing circuit and a video device without providing a terminal for connection detection. An object of the present invention is to provide a semiconductor integrated circuit having a simple connection detection function.

  In order to solve the above problems, a semiconductor integrated circuit having a connection detection function according to the present invention processes a video signal that is input and outputs it from an output stage, and is output from the output stage of the signal processing circuit. An output terminal that outputs the processed video signal to the outside, a pull-up resistor connected to the output terminal, and an input signal detection circuit that detects whether the video signal is input to the signal processing circuit A simulated output stage configured to output a current corresponding to a current output from the output stage of the signal processing circuit, and a connection current detection circuit that detects a value of the current output from the simulated output stage; A control circuit that turns on and off the signal processing circuit, and the control circuit detects that the input signal detection circuit detects that the video signal is not input to the signal processing circuit. And turning off the signal processing circuit and determining whether or not a video device is connected to the output terminal based on the voltage of the output terminal, and the input signal detection circuit is configured such that the video signal is the signal processing circuit. Whether or not a video device is connected to the output terminal based on the value of the current output from the simulated output stage detected by the connection current detection circuit. It is configured to determine.

  According to this configuration, it is determined whether or not a video signal is input to the signal processing circuit. If no video signal is input to the signal processing circuit, the signal output terminal is connected based on the voltage of the output terminal. It is determined whether or not a video device is connected, and when a video signal is input to the signal processing circuit, based on the value of the current output from the simulated output stage detected by the connection current detection circuit, Since it is determined whether or not the video equipment is connected to the signal output terminal, it is not necessary to monitor the terminal voltage of the termination resistor connected to the signal output terminal. Therefore, the connection between the semiconductor integrated circuit including the signal processing circuit and the video equipment can be detected without providing a terminal for detecting the connection between the semiconductor integrated circuit and the video equipment.

  The control circuit outputs an external on / off control signal for turning on / off an external circuit of the semiconductor integrated circuit based on a detection result of whether or not the video signal is input in the input signal detection circuit. It may be configured to.

  According to this configuration, it is possible to turn off the semiconductor integrated circuit related to the semiconductor integrated circuit. As a result, it is possible to operate for a long time by operating the set including the semiconductor integrated circuit with low power consumption. .

  The connection current detection circuit may be configured to detect a value of a current output from the simulated output stage in response to a horizontal synchronization signal of the video signal.

  According to this configuration, since the horizontal synchronization signal that is always included in the video signal is used, the value of the current output from the simulated output stage can be detected with a simple configuration.

  The connection current detection circuit may be configured to detect a value of a current output from the simulated output stage corresponding to a horizontal synchronization signal and a luminance signal of the video signal.

  According to this configuration, since the luminance signal is used in addition to the horizontal synchronization signal included in the video signal, it is possible to further improve the determination accuracy of whether or not the video equipment is connected to the signal output terminal.

  The output stage of the signal processing circuit includes a first high-potential side transistor in which one main terminal is connected to a first potential applying unit that applies a first potential, and a control terminal is connected to a previous video signal output terminal; One main terminal is connected to a second potential applying means for applying a second potential lower than the first potential, the other main terminal is connected to the other main terminal of the first high potential side transistor, and a control terminal is connected A first low potential side transistor connected to a previous video signal output terminal and configured to operate in a complementary manner with the first high potential side transistor, the other main main transistor of the first high potential side transistor The processed video signal is output from a connection point between the terminal and the other main terminal of the first low-potential side transistor, and one of the main terminals applies the first potential to the simulated output stage. The third potential application hand Connected to the second high potential side transistor whose control terminal is connected to the control terminal of the first high potential side transistor, and one main terminal is connected to the fourth potential applying means for applying the second potential, The other main terminal is connected to the other main terminal of the second high potential side transistor, the control terminal is connected to the control terminal of the first low potential side transistor, and is complementary to the second high potential side transistor. A second low-potential side transistor configured to operate, wherein the connection current detection circuit has a third high terminal connected to a fifth potential applying means having one main terminal for applying the first potential. A third low potential terminal is connected to the potential side transistor and a sixth potential applying means for applying the second potential, and the other main terminal is connected to the other main terminal of the third high potential side transistor. Potential side transistor And the third main terminal of the third high potential side transistor and the other main terminal of the third low potential side transistor are maintained at a predetermined potential to maintain a connection point (hereinafter referred to as a specific connection point). Biasing means for biasing the control terminal of the high potential side transistor and the control terminal of the third low potential side transistor, between one main terminal of the third high potential side transistor and the fifth potential applying means, and A connection current detection resistor interposed between at least one main terminal of the third low potential side transistor and the sixth potential applying means, wherein the specific connection point is the second high potential side It may be connected to a connection point between the other main terminal of the transistor and the other main terminal of the second low potential side transistor. Here, the potential applying means includes a GND terminal in addition to a positive power source and a negative power source.

  According to this configuration, the control terminals of the high-potential side transistor and the low-potential side transistor constituting the simulated output stage are connected to the control terminals of the high-potential side transistor and the low-potential side transistor constituting the output stage, and the simulation is performed. The connection point between the other main terminal of the second high-potential side transistor of the output stage and the other main terminal of the second low-potential side transistor is connected to a specific connection point of the connection current detection circuit 15 and has a predetermined potential. Since the predetermined potential is set to GND, a current corresponding to the current output from the output stage of the signal processing circuit to the video equipment is output from the simulated output stage to the connection current detection circuit. On the other hand, by monitoring the terminal voltage of the connection current detection resistor, the current output from the simulated output stage to the connection current detection circuit can be detected. Therefore, with this configuration, the current output from the output stage of the signal processing circuit to the video equipment can be indirectly detected.

  The second potential may be a GND potential, and the predetermined potential may be higher than the GND potential.

  According to this configuration, the negative power supply can be omitted.

  The first to third high-potential side transistors, the first to third low-potential side transistors, and the transistors constituting the bias means may be formed of MOS transistors.

  The first to third high-potential side transistors, the first to third low-potential side transistors, and the transistor constituting the bias means may be formed of bipolar transistors.

  The present invention is configured as described above, and has a connection detection function capable of detecting a connection between a semiconductor integrated circuit including a video signal processing circuit and a video device without providing a terminal for connection detection. The semiconductor integrated circuit can be provided.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit including a connection detection circuit according to the present invention. FIG. 2 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit of FIG.

  As shown in FIG. 1, the semiconductor integrated circuit 61 of the present embodiment includes a video signal input terminal 39 to which a video signal is input, a signal processing circuit 1 that processes the input video signal, and a signal processing circuit 1. A video signal output terminal 9 for outputting the processed video signal, a pull-up resistor 14 connected to the video signal output terminal 9, an input signal detection circuit 17 for detecting whether or not a video signal is input, and a signal A simulated output stage 80 configured to output a current corresponding to the current output from the output stage of the processing circuit 1, a connection current detection circuit 15 for detecting the value of the current output from the simulated output stage 80, And a control circuit 16.

  A video signal is input to the video signal input terminal 39 via the DC cut capacitor 2. Here, the signal processing circuit 1 is composed of, for example, an operational amplifier, and amplifies a video signal input via the video signal input terminal 39. A video device 32 is connected to the video signal output terminal 9 via a termination resistor 5 and a cable 13 as described later (see FIG. 2). Examples of the video equipment 32 include a TV and a DVD player. The pull-up resistor 14 has one terminal connected to the positive power source Vdd and the other terminal connected to the video signal output terminal 9. For example, the input signal detection circuit 17 determines whether or not a video signal is input based on whether or not the level of the video signal input via the video signal input terminal 39 is equal to or higher than a predetermined value (the video signal is a signal processing circuit). 1 is detected). The input signal detection circuit 17 inputs the detection result to the control circuit 16 as the input signal detection signal 101 (see FIG. 2). The configurations of the simulated output stage 80 and the connection current detection circuit 15 will be described in detail later.

  Based on the input signal detection signal 101, the control circuit 16 determines whether or not the input signal detection circuit 17 has detected that a video signal has been input to the signal processing circuit 1. When the input signal detection circuit 17 detects that the video signal is not input to the signal processing circuit 1, the signal processing circuit 1 is turned off and the video signal is output based on the voltage of the video signal output terminal 9. It is determined whether or not the video equipment 32 (see the figure) is connected to the output terminal 9. On the other hand, when the input signal detection circuit 17 detects that the video signal is input to the signal processing circuit 1, the current value output from the simulated output stage 80 detected by the connection current detection circuit 15 is set. Based on this, it is determined whether or not the video equipment 32 is connected to the video signal output terminal 9. The control circuit 16 is composed of, for example, a logic circuit, a CPU, a processor such as a comparator, and the like.

  Next, the configuration of the semiconductor integrated circuit 61 will be described in more detail with reference to FIG.

  As shown in FIG. 2, one end of a termination resistor 5 on the semiconductor integrated circuit side is connected to the video signal output terminal 9 of the semiconductor integrated circuit 61, and the other end of the termination resistor 5 is connected to a terminal (hereinafter referred to as a semiconductor integrated circuit side output). Terminal 11). One end of a cable (connector) 13 is connected to the semiconductor integrated circuit side output terminal 11, and the other end of the cable (connector) 13 is connected to an input terminal (hereinafter referred to as a video equipment side input terminal) 12 of the video equipment 32. Yes. The cable 13 is detachably connected to the semiconductor integrated circuit side output terminal 11 and the video equipment side input terminal 12. Accordingly, when the cable 13 is connected to the semiconductor integrated circuit side output terminal 11 and the video equipment side input terminal 12, the video equipment 32 is connected to the semiconductor integrated circuit 61, and the cable 13 is connected to the semiconductor integrated circuit side output terminal 11 and the video. When removed from the device-side input terminal 12, the video device 32 is disconnected from the semiconductor integrated circuit 61 (disconnected from the semiconductor integrated circuit 61). Hereinafter, connecting the cable 13 to the semiconductor integrated circuit side output terminal 11 and the video equipment side input terminal 12 is expressed as connecting the video equipment 32 to the semiconductor integrated circuit 61, and the cable 13 is connected to the semiconductor integrated circuit side. Removal from the output terminal 11 and the video equipment side input terminal 12 may be expressed as the video equipment 32 not being connected to the semiconductor integrated circuit 61.

  In the video equipment 32, one end of the video equipment side termination resistor 6 is connected to the video equipment side input terminal 12, and a main circuit such as an amplifier is connected via a DC cut capacitor 30. The other end of the termination resistor 6 is connected to GND. The termination resistor 5 and the termination resistor 6 have a general resistance value of 75Ω.

  Next, the configuration of the semiconductor integrated circuit 61 will be described in detail. First, the transistor terminals are defined. In the present specification and claims, a pair of terminals through which an operating current of a transistor enters and exits are referred to as “main terminals”. The operating current is a drain current or a source current in a field effect transistor (FET), and is a collector current or an emitter current in a bipolar transistor. Therefore, in the field effect transistor, the source or drain is the main terminal, and in the bipolar transistor, the emitter or collector is the main terminal. A terminal to which a control signal for controlling the operating current of the transistor is input is referred to as a “control terminal”. Therefore, in the field effect transistor, the gate is the control terminal, and in the bipolar transistor, the base is the control terminal. Note that there is generally no structural difference between a pair of main terminals of a transistor, and one main terminal functions as a source or an emitter, and the other main terminal functions as a drain or a collector depending on the state of use. Hereinafter, for convenience, one main terminal is referred to as a first main terminal, and the other main terminal is referred to as a second main terminal. In addition, the above names are used only for main transistors, and normal names are used for other transistors.

  Next, the power supply in the semiconductor integrated circuit 61 will be described. In the present embodiment, the semiconductor integrated circuit 61 includes a positive power source and a negative power source. In the present embodiment, since the power supply target of the positive power source and the negative power source is a field effect transistor, reference signs of Vdd and Vss are given to the positive power source and the negative power source, respectively. The positive power supply Vdd and the negative power supply Vss in the semiconductor integrated circuit 61 output voltages having the same absolute value and positive and negative polarities, respectively. Further, the ground reference terminal is denoted by GND. When the power supply target of the positive power source and the negative power source is a bipolar transistor (see the fifth embodiment), the positive power source and the negative power source are denoted by reference numerals Vcc and Vee, respectively.

  The signal processing circuit 1 is composed of a multistage amplifier circuit, and its output stage 1 'is shown in FIG. Here, the output stage 1 ′ includes a high-potential side transistor (hereinafter referred to as a high-potential side transistor (first high-potential side transistor)) 18 and a low-potential side transistor (hereinafter referred to as a low-potential side transistor) that operate complementarily. (First low potential side transistor)) 20. The high-potential side transistor 18 is composed of a P-type MOS field effect transistor (hereinafter referred to as a PMOS transistor), and its first main terminal (source) is connected to the positive power supply Vdd (first potential applying means). It is connected. The low-potential side transistor 20 is composed of an N-type MOS field effect transistor (hereinafter referred to as NMOS transistor) here, and its first main terminal (source) is connected to the negative power supply Vss (second potential applying means). The second main terminal (drain) is connected to the second main terminal (drain) of the high potential side transistor 18. A node (connection point) between the second main terminal of the high-potential side transistor 18 and the second main terminal of the low-potential side transistor constitutes the output unit 62 of the signal processing circuit 1 (output stage 1 ′). The video signal output terminal 9 is connected through a signal line 71. The signal line 71 is connected to the other terminal of the pull-up resistor 14 whose one terminal is connected to the positive power supply Vdd. That is, the pull-up resistor 14 is connected to the output unit 62 of the signal processing circuit 1 and the video signal output terminal 9 through the signal line 71. The output of the previous stage is input to the control terminal (gate) of the high potential side transistor 18 and the control terminal (gate) of the low potential side transistor 20. The output of the previous stage is a video signal amplified by the amplifier circuit up to the previous stage. Here, since the high-potential side transistor 18 and the low-potential side transistor 20 are composed of different channel type transistors, the output of the previous stage is directly input to the control terminals of both transistors. In the case where the transistor 18 and the low-potential side transistor are composed of the same channel type transistor, the output of the previous stage is inverted and input to the control terminal of one of the transistors. With such a configuration, when one of the high potential side transistor 18 and the low potential side transistor 20 is operating (ON), the other is not operating (OFF). That is, the high potential side transistor 18 and the low potential side transistor 20 are configured to operate in a complementary manner. Further, the high potential side transistor 18 and the low potential side transistor 20 are designed to have substantially the same characteristics except for the channel type. The stages other than the output stage 1 ′ of the signal processing circuit 1 are configured similarly to the output stage 1 ′.

  A simulated output stage 80 is connected to the output stage 1 '. The configuration of the simulated output stage 80 is the same as that of the output stage 1 '. That is, the simulated output stage 80 includes a high potential side transistor (second high potential side transistor) 19 and a low potential side transistor (second low potential side transistor) 21 that operate complementarily. The high potential side transistor 19 is composed of a PMOS transistor, and its first main terminal (source) is connected to the positive power supply Vdd (third potential applying means). The low-potential side transistor 20 is composed of an NMOS transistor, and its first main terminal (source) is connected to the negative power source Vss (fourth potential applying means), and its second main terminal (drain) is high. The potential side transistor 19 is connected to the second main terminal (drain). The high potential side transistor 18 and the low potential side transistor 20 are designed to have substantially the same characteristics except for the channel type. A node 63 between the second main terminal of the high potential side transistor 19 and the second main terminal of the low potential side transistor is connected to the connection current detection circuit. The output of the previous stage is input to the control terminal (gate) of the high potential side transistor 19 and the control terminal (gate) of the low potential side transistor 21. That is, the simulated output stage 80 and the output stage 1 ′ are connected to each other with the control terminals of a pair of transistors constituting each of them. In FIG. 2, the simulated output stage 80 is shown in the signal processing circuit 1 for the sake of convenience, but it goes without saying that the simulated output stage 80 is not included in the signal processing circuit.

  The connection current detection circuit 15 includes a high potential side transistor (third high potential side transistor) 26 connected in series between a positive power source Vdd (fifth potential applying unit) and a negative power source Vss (sixth potential applying unit). And a low potential side transistor (third low potential side transistor) 24. The high potential side transistor 26 is composed of an NMOS transistor, and its second main terminal (drain) is connected to the positive power supply Vdd via the connection current detection resistor 22. The low potential side transistor 24 is composed of a PMOS transistor, and its second main terminal (drain) is connected to the negative power source Vss, and its first main terminal (source) is the first potential of the high potential side transistor 26. Is connected to the main terminal (source). The high potential side transistor 26 and the low potential side transistor 24 are designed to have substantially the same characteristics except for the channel type. A node 64 between the first main terminal of the high potential side transistor 26 and the first main terminal of the low potential side transistor 24 is connected to the node 63 of the simulated output stage 80. As described below, the high-potential side transistor 26 and the low-potential side transistor 24 have the potentials of their control terminals (gates) so that the potential Vc of the node 64 becomes a predetermined potential (here, GND potential). It is controlled.

  The control terminal of the high potential side transistor 26 receives the potential Vb of the node 65 between the low potential side terminal of the current source 28 and the source of the PMOS transistor 27. The terminal on the high potential side of the current source 28 is connected to the positive power supply Vdd. The drain of the PMOS transistor 27 is connected to GND, and the gate is connected to GND. Therefore, the potential Vb of the node 65 is higher than GND that is determined according to the current of the current source 28. On the other hand, the potential Va of the node 66 between the high potential side terminal of the current source 29 and the source of the NMOS transistor 25 is input to the control terminal of the low potential side transistor 24. The terminal on the low power supply side of the current source 29 is connected to the negative power supply Vss. The drain of the NMOS transistor 25 is connected to the positive power supply Vdd, and the gate is connected to GND. Accordingly, the potential Va of the node 66 is lower than GND determined according to the current of the current source 29. Then, the potential of the node 64 becomes lower than the potential Vb of the node 65 and becomes higher than the potential Va of the node 66. Therefore, by appropriately setting the currents of the current source 28 and the current source 28, the potential of the node 64 The potential Vc can be set to the GND potential. In this embodiment, the potential of the node 64 is set to the GND potential in this way. The NMOS transistor 25, the PMOS transistor 27, the current source 28, and the current source 29 constitute bias means for the control terminal of the high potential side transistor 26 and the control terminal of the low potential side transistor 24.

  As described above, the input signal detection signal 101 is input to the control circuit 16. In addition, the voltage 102 of the video signal output terminal 9 (signal line 71) is input to the control circuit 16. Further, the terminal voltage 103 of the connection current detection resistor 22 is input to the control circuit 16. Since the terminal voltage of the connection current detection resistor 22 is proportional to the current flowing through the connection current detection resistor 22, the controller 16 detects the current flowing through the connection current detection resistor 22 based on the terminal voltage 103 of the connection current detection resistor 22. . Based on these inputs, the control circuit 16 determines whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61. This operation will be described in detail later.

  On the other hand, the control circuit 16 outputs an on / off control signal 105 to the signal processing circuit 1 and the connection current detection circuit 15 to turn on / off the signal processing circuit 1 and the connection current detection circuit 15. That is, in the output stage 1 ′ and the simulated output stage 80 of the signal processing circuit 1, the control terminals of the high-potential side transistor 18 and the high-potential side transistor 19 are connected to the positive power supply Vdd via the PMOS transistor 43. 20 and the control terminal of the low-potential side transistor 21 are connected to the negative power source Vss via the NMOS transistor 44. An on / off control signal is input to the gate of the NMOS transistor 44, and a signal obtained by inverting the on / off control signal by the inverter 37 is input to the gate of the PMOS transistor 43. Accordingly, when the on / off control signal 105 becomes low level, the PMOS transistor 43 and the NMOS transistor 44 are turned off, and the output stage 1 'and the simulated output stage 80 are set in an operating state (turned on). On the other hand, when the on / off control signal 105 becomes high level, the PMOS transistor 43 and the NMOS transistor 44 are turned on, and the potentials of the control terminals of the high potential side transistor 18 and the high potential side transistor 19 become the potential of the positive power supply Vdd. The potentials of the control terminals of the low potential side transistor 20 and the low potential side transistor 21 become the potential of the negative power supply Vss, and the high potential side transistor 18, the high potential side transistor 19, the low potential side transistor 20 and the low potential side transistor 21 are all turned off. To do. As a result, the output stage 1 'and the simulated output stage 80 are deactivated (turned off). When the output stage 1 'is turned off, the voltage at the video output terminal 9 is determined independently of the output stage 1'.

  In the connection current detection circuit 15, the control terminal of the high potential side transistor 26 is connected to the negative power supply Vss via the NMOS transistor 42, and the control terminal of the low potential side transistor 24 is connected to the positive power supply Vdd via the PMOS transistor 41. It is connected. An on / off control signal is input to the gate of the NMOS transistor 42, and a signal obtained by inverting the on / off control signal by the inverter 37 is input to the gate of the PMOS transistor 41. Accordingly, when the on / off control signal 105 becomes low level, the NMOS transistor 42 and the PMOS transistor 41 are turned off, and the high potential side transistor 26 and the low potential side transistor 24 are turned on. As a result, the connection current detection circuit 15 enters an operating state (turns on). On the other hand, when the on / off control signal 105 becomes low level, the NMOS transistor 42 and the PMOS transistor 41 are turned on, the potential of the control terminal of the high potential side transistor 26 becomes the potential of the negative power source Vss and the low potential side transistor 24 The potential of the control terminal becomes the potential of the positive power supply Vdd, and the high potential side transistor 26 and the low potential side transistor 24 are turned off. As a result, the connection current detection circuit 15 is deactivated (turned off).

  Next, the operation of the semiconductor integrated circuit 61 configured as described above will be described.

  FIG. 3 is a timing chart showing an operation mode of the semiconductor integrated circuit 61 of the present embodiment.

  As shown in FIG. 3, the semiconductor integrated circuit 61 has three operation modes, modes 1 to 3.

  Mode 1 is an operation mode when a video signal is input to the signal processing circuit 1 and the video equipment 32 is connected to the semiconductor integrated circuit 61.

  Mode 2 is an operation mode when a video signal is input to the signal processing circuit 1 and the video equipment 32 is not connected to the semiconductor integrated circuit 61.

  Mode 3 is an operation mode when no video signal is input to the signal processing circuit 1.

  First, mode 1 will be described.

  As shown in FIG. 3, the video signal includes a horizontal synchronizing signal 81 which is a negative voltage pulse and a luminance signal (grayscale signal) having a positive voltage value. The horizontal synchronization signal 81 is a signal that is always added to the video signal, and is necessary for synchronization with the video equipment 32.

  Referring to FIGS. 1 to 3, in this embodiment, input signal detection circuit 17 determines whether or not a video signal is input based on whether or not the level of the input video signal is equal to or less than a predetermined negative value. The predetermined negative value is set to a level at which the horizontal synchronizing signal 81 can be detected. Therefore, when a video signal is input to the signal processing circuit 1 and the input signal detection circuit 17, the input signal detection circuit 17 outputs an input detection signal 101 indicating that the video signal has been input (high level). To do. Then, the control circuit 16 outputs a high level on / off control signal 105. As a result, the signal processing circuit 1, the simulated output stage 80, and the connection current detection circuit 15 are turned on.

  Then, the signal processing circuit 1 amplifies (processes) the input video signal and outputs it from the output unit 62 of the output stage 1 ′. The video signal output from the output unit 62 is input to the video equipment 32 through the signal line 71, the video signal output terminal 9, the termination resistor 5, the semiconductor integrated circuit side output terminal 11, and the cable 13.

  Here, in a state where the signal processing circuit 1 is on, the voltage (potential) of the video signal output terminal 9 is equal to the potential of the output unit 62 of the signal processing circuit 1, and the potential of the output unit 62 is determined by the video equipment 32. Regardless of whether it is connected to the semiconductor integrated circuit 61, it varies depending on the input video signal. Therefore, when a video signal is input to the signal processing circuit 1, it is possible to accurately determine whether the video equipment 32 is connected to the semiconductor integrated circuit 61 based on the potential of the video output terminal 9. Can not. Therefore, in the present invention, when a video signal is input to the signal processing circuit 1, the current output from the output unit 62 of the signal processing circuit 1 is indirectly detected as described below, based on this. Whether the video equipment 32 is connected to the semiconductor integrated circuit 61 is determined.

  That is, when the video equipment 32 is connected to the semiconductor integrated circuit 61, a current is output from the output unit 62 of the output stage 1 ′ to the video equipment 32. In this case, when the video signal has a positive voltage value, the low potential side transistor 20 is turned off, and the drain current of the high potential side transistor 18 corresponding to the video signal is output from the positive power source Vdd to the high potential side transistor 18 and the output. It flows to the video equipment 32 via the unit 62. On the other hand, when the video signal has a negative voltage value, the high potential side transistor 18 is turned off, and the drain current of the low potential side transistor 18 corresponding to the video signal is output from the video equipment 32 to the output unit 62 and the low potential side transistor. 18 and then flows to the negative power source Vss.

  Here, the control terminals of the high potential side transistor 19 and the low potential side transistor 21 constituting the simulated output stage 80 are connected to the control terminals of the high potential side transistor 18 and the low potential side transistor 20 constituting the output stage 1 ′. Since the node 63 of the simulated output stage 80 is connected to the node 64 of the connection current detection circuit 15 and is maintained at the GND potential, the output from the node 63 of the simulation output stage 80 to the connection current detection circuit 15 is output. A current corresponding to the current output from the output unit 62 of the stage 1 ′ to the video equipment 32 is output. That is, when the video signal has a positive voltage value, for example, when a luminance signal is input, the low potential side transistor 21 is turned off, and a high potential corresponding to the drain current of the high potential side transistor 18 in the output stage 1 ′. The drain current of the side transistor 19 flows from the positive power supply Vdd to the node 64 of the connection detection circuit 15 through the high potential side transistor 19 and the node 63. In the connection detection circuit 15, the current flowing into the node 64 further flows through the low potential side transistor 24 to the negative power supply Vss. On the other hand, when the video signal has a negative voltage value, for example, when a horizontal synchronizing signal is input, the high-potential side transistor 19 is turned off and corresponds to the drain current of the low-potential side transistor 20 in the output stage 1 ′. The drain current of the low potential side transistor 21 flows from the positive power source Vdd to the node 64 through the connection current detection resistor 22 and the high potential side transistor 26 in the connection detection circuit 15, and this current further flows to the node 63 and the simulated output stage 1 ′. It flows to the negative power source Vss through the low potential side transistor 21.

  Then, the control circuit 16 detects the terminal voltage 103 of the connection current detection resistor 22, thereby monitoring the value of the current flowing through the connection current detection resistor 22 when the video signal has a negative voltage value.

  As described above, the current output from the output unit 62 of the signal processing circuit 1 is indirectly detected.

  In this state, when the video equipment 32 is disconnected from the semiconductor integrated circuit 61, the semiconductor integrated circuit 61 enters a mode 2 operation mode.

  When the video equipment 32 is disconnected from the semiconductor integrated circuit 61, the voltage between the control terminal and the first main terminal of the high potential side transistor 18 and the low potential side transistor 20 in the output stage 1 ′ (between the gate and the source in this embodiment). Voltage) decreases, and the current output from the output unit 62 decreases. Then, the current flowing through the connection current detection resistor 22 decreases. On the contrary, when the video equipment 32 is disconnected and connected to the semiconductor integrated circuit 61, between the control terminal of the high potential side transistor 18 and the low potential side transistor 20 and the first main terminal in the output stage 1 ′. The voltage increases, the current output from the output unit 62 increases, and as a result, the current flowing through the connection current detection resistor 22 increases. On the other hand, when the current flowing through the connection current detection resistor 22 detected through the terminal voltage 103 of the connection current detection resistor 22 is equal to or less than a predetermined current threshold value (negative current threshold value), the control circuit 16 sends a video device to the semiconductor integrated circuit 61. It is determined that the video device 32 is not connected, and if it exceeds a predetermined threshold, it is determined that the video equipment 32 is connected to the semiconductor integrated circuit 61. Therefore, it is possible to determine whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61 by appropriately setting the predetermined current threshold. This predetermined current threshold is determined by calculation, experiment, simulation, or the like. Instead of the predetermined current threshold, a predetermined voltage threshold (negative voltage threshold) may be set for the terminal voltage 103 of the connection current detection resistor 22.

  In this way, the current output from the output unit 62 of the signal processing circuit 1 is indirectly detected, and based on this, it is determined whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61.

  Then, when the video equipment 32 is disconnected from the semiconductor integrated circuit 61, the control circuit 16 discriminates this as described above and outputs a low level on / off control signal 105 (see FIG. 3). As a result, the signal processing circuit 1, the simulated output stage 80, and the connection current detection circuit 15 are turned off.

  Next, mode 3 will be described.

  As shown in FIG. 3, in mode 3, no video signal is input. Therefore, the input signal detection circuit 17 outputs the input detection signal 101 indicating that the video signal is not input (low level). Then, the control circuit 16 outputs a low level on / off control signal 105. As a result, the signal processing circuit 1, the simulated output stage 80, and the connection current detection circuit 15 are turned off. As described above, the control circuit 16 outputs the low-level on / off control signal 105 regardless of whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61.

By turning off the signal processing circuit 1 (exactly its output stage 1 ′), the voltage of the video output terminal 9 is determined independently of the output stage 1 ′ as described above. Here, when the video equipment 32 is connected to the semiconductor integrated circuit 61, the voltage (potential) of the video signal output terminal 9 is the voltage of the positive power supply Vdd, the pull-up resistor 14, the termination resistor 5, and the termination. The resistance is divided by the resistor 6. That is,
Voltage of video signal output terminal 9 = voltage of positive power supply Vdd × (resistance value of termination resistor 5 + resistance value of termination resistor 6) / (resistance value of pull-up resistor 14 + resistance value of termination resistor 5 + resistance of termination resistor 6) Resistance value)
It becomes.

  However, the resistance value (for example, several hundreds KΩ) of the pull-up resistor 14 is designed to be sufficiently larger than the total value (= 150Ω) of the resistance value of the termination resistor 5 and the resistance value of the termination resistor 6. The voltage of 9 is close to the GND potential.

  On the other hand, when the video equipment 32 is not connected to the semiconductor integrated circuit 61, the voltage of the video signal output terminal 9 is equal to the voltage of the positive power supply Vdd. Then, the control circuit 16 determines that the video device 32 is not connected to the semiconductor integrated circuit 61 when the voltage 102 of the video signal output terminal 9 is equal to or higher than a predetermined threshold value, and the semiconductor circuit when the voltage is lower than the predetermined threshold value. It is determined that the video equipment 32 is connected to the integrated circuit 61. Therefore, it is possible to determine whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61 by appropriately setting the predetermined threshold value. This predetermined threshold is determined by calculation, experiment, simulation, or the like.

  As described above, according to the semiconductor integrated circuit 61 of the present embodiment, it is determined whether or not a video signal is input to the signal processing circuit 1, and no video signal is input to the signal processing circuit 1. Based on the voltage of the video signal output terminal 9, it is determined whether or not the video equipment 32 is connected to the video signal output terminal 9, and when the video signal is input to the signal processing circuit 1, Since it is configured to determine whether or not the video equipment 32 is connected to the video signal output terminal 9 based on the value of the current output from the simulated output stage 80 detected by the connection current detection circuit 15. There is no need to monitor the terminal voltage of the termination resistor connected to the video signal output terminal 9. Therefore, the connection between the semiconductor integrated circuit 61 including the signal processing circuit 1 and the video equipment 32 can be detected without providing a terminal for detecting the connection between the semiconductor integrated circuit 61 and the video equipment 32.

  In the present embodiment, the video device 32 is connected to the video signal output terminal 9 by detecting the value of the current output from the simulated output stage 80 by the synchronization signal 81 that is always superimposed on the video signal. Therefore, it is possible to detect the value of the current output from the simulated output stage 80 with a simple configuration.

(Embodiment 2)
FIG. 4 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit according to the second embodiment of the present invention.

  The semiconductor integrated circuit 61 of the present embodiment is different from the semiconductor integrated circuit 61 of the first embodiment in the following points, and is otherwise the same as the semiconductor integrated circuit 61 of the first embodiment. Hereinafter, this difference will be described.

  As shown in FIG. 4, in the present embodiment, in the connection current detection circuit 15, a connection current detection resistor 23 is inserted between the low potential side transistor 24 and the negative power source Vss. A terminal voltage 104 is input to the control circuit 16. In the control circuit 16, a predetermined current threshold (positive current threshold) is set for the current flowing through the connection current detection resistor 23 detected through the terminal voltage 104 of the connection current detection resistor 23. When the current flowing through the connection current detection resistor 23 is equal to or less than the positive current threshold, or when the current flowing through the connection current detection resistor 22 is equal to or less than the negative current threshold, the control circuit 16 transmits a video device to the semiconductor integrated circuit 61. 32 is determined not to be connected. Otherwise, it is determined that the video equipment 32 is connected to the semiconductor integrated circuit 61. Therefore, it is possible to determine whether or not the video equipment 32 is connected to the semiconductor integrated circuit 61 by appropriately setting the positive current threshold. This positive current threshold is determined by calculation, experiment, simulation, or the like. Instead of this positive current threshold, a predetermined positive voltage threshold may be set for the terminal voltage 104 of the connection current detection resistor 23.

  According to the semiconductor integrated circuit 61 of the present embodiment configured as described above, the value of the current output from the simulated output stage 80 is detected by both the horizontal synchronizing signal 81 and the luminance signal 82 of the video signal. Thus, since it is determined whether or not the video equipment 32 is connected to the video signal output terminal 9, it is possible to improve the accuracy of the determination as compared with the first embodiment.

(Embodiment 3)
FIG. 5 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit according to the third embodiment of the present invention.

  The semiconductor integrated circuit 61 of the present embodiment is configured such that the control circuit 16 outputs an external on / off control signal 72 from the external control terminal 36 to the outside. The other points are the same as those of the semiconductor integrated circuit 61 of the second embodiment.

  According to the semiconductor integrated circuit 61 of this embodiment, for example, when a video signal is not input, or when a video signal is input but a video device is not connected, an external on / off control signal 72, the operation of the set control semiconductor integrated circuit device can be stopped. Therefore, mode control of the entire set including the semiconductor integrated circuit 61 is possible, and thus power saving can be achieved.

(Embodiment 4)
FIG. 6 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

  The semiconductor integrated circuit 61 of the present embodiment is different from the semiconductor integrated circuit 61 of the third embodiment in the following points, and is otherwise the same as the semiconductor integrated circuit 61 of the third embodiment. Hereinafter, this difference will be described.

  In the semiconductor integrated circuit 61 of the present embodiment, in the output stage 1 ′ of the signal processing circuit 1, the first main terminal of the low potential side transistor 20 is connected to GND. That is, a DC voltage (hereinafter, referred to as a predetermined DC voltage) having a sign corresponding to the absolute value of the negative voltage Vss in the third embodiment is superimposed on the video signal output from the output unit 62. Similarly, in the simulated output stage 80, the first main terminal of the low-potential side transistor 21 is connected to GND, and a predetermined DC voltage is superimposed on the output of the node 63.

  Correspondingly, in the connection current detection circuit 15, the second main terminal of the low potential side transistor 24 is connected to GND via the connection current detection resistor 23. Further, the gate of the PMOS transistor 27 is biased by a predetermined DC voltage by the bias power source Vp. The terminal on the low potential side of the current source 29 is connected to GND, and the gate of the NMOS transistor 25 is biased by a predetermined DC voltage by the bias power supply Vp. With this configuration, the potential Vc of the node 64 is maintained at a potential that is higher than the GND potential by a predetermined DC voltage. The source of the NMOS transistor 42 is also connected to GND. Even with this configuration, the potential of the node 64 is maintained at a potential higher than the GND potential by a predetermined DC voltage, so that the high potential side transistor 26 can be turned off by being turned on.

  In the semiconductor integrated circuit 61 of the present embodiment configured as described above, a DC voltage is superimposed on the video signal output from the video output terminal 9. However, other than this, the semiconductor integrated circuit 61 of the present embodiment operates in the same manner as the semiconductor integrated circuit 61 of the third embodiment.

  And according to the semiconductor integrated circuit 61 of this Embodiment, a negative power supply is omissible.

(Embodiment 5)
FIG. 7 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit according to the fifth embodiment of the present invention.

  As shown in FIG. 7, the semiconductor integrated circuit 61 of the present embodiment is similar to the semiconductor integrated circuit 61 of the third embodiment in that the high-potential side transistors 18, 19, and 26 made of MOS transistors are replaced with the high-potential side made of bipolar transistors. The transistors 51, 52 and 56 are replaced, the low potential transistors 20, 21, and 24 made of MOS transistors are replaced with the low potential transistors 53, 54, and 55 made of bipolar transistors, and the NMOS transistor 25 is replaced with an npn bipolar transistor 58. The PMOS transistor 27 is replaced with a pnp bipolar transistor 57. Accordingly, in FIG. 7, reference numerals Vcc and Vee are respectively attached to the positive power source and the negative power source to which the bipolar transistor is connected. As is well known, even if a MOS transistor in a circuit is replaced with a bipolar transistor, the circuit operates in the same manner. Therefore, the semiconductor integrated circuit 61 of the present embodiment operates in the same manner as the semiconductor integrated circuit 61 of the third embodiment.

  In the first to fourth embodiments, one positive power supply Vdd and one negative power supply Vss are provided, but a plurality of these may be provided.

  The semiconductor integrated circuit having a connection detection function of the present invention has a connection detection function capable of detecting a connection between a semiconductor integrated circuit including a video signal processing circuit and a video device without providing a terminal for connection detection. As a semiconductor integrated circuit, it is useful in applications such as battery-powered digital cameras, camcorders, mobile phones and the like.

1 is a block diagram showing a configuration of a semiconductor integrated circuit including a connection detection circuit according to the present invention. FIG. 2 is a circuit diagram showing a detailed configuration of the semiconductor integrated circuit of FIG. 1. 3 is a timing chart showing an operation mode of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the detailed structure of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the semiconductor integrated circuit which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the detailed structure of the semiconductor integrated circuit which concerns on Embodiment 4 of this invention. FIG. 10 is a circuit diagram showing a detailed configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention. It is a circuit diagram which shows the structure of the conventional semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal processing circuit 1 'Output stage 2,30 DC cut capacitor 5 Terminating resistor 6 Terminating resistor 9 Video signal output terminal 11 Integrated circuit side output terminal 12 Peripheral video equipment side input terminal 13 Cable 14 Pull-up resistor 15 Connection current detection circuit 16 control circuit 17 input signal detection circuit 18, 19, 51, 52 high potential side transistors 20, 21, 53, 54 low potential side transistors 22, 23 connection current detection resistors 24, 55 low potential side transistor 25 NMOS transistors 26, 56 High-side transistor 27 PMOS transistors 28 and 29 Current source 32 Video equipment 36 External control terminal 37 Inverter 39 Video signal input terminals 41 and 43 PMOS transistors 42 and 44 NMOS transistor 57 pnp bipolar transistor 58 npn bipolar transistor 6 Output unit 63 to 66 Node 71 Signal line 72 External on / off control signal 80 Simulated output stage 81 Horizontal synchronization signal 82 Luminance signal 101 Input detection signal 102 Video signal output terminal voltage 103 Connection current detection resistor terminal voltage 104 Connection current Detection resistor terminal voltage 105 ON / OFF control signal

Claims (8)

A signal processing circuit that processes the input video signal and outputs it from the output stage;
An output terminal for outputting a video signal after signal processing output from the output stage of the signal processing circuit to the outside;
A pull-up resistor connected to the output terminal;
An input signal detection circuit for detecting whether or not the video signal is input to the signal processing circuit;
A simulated output stage configured to output a current corresponding to a current output from the output stage of the signal processing circuit;
A connection current detection circuit for detecting a current value output from the simulated output stage;
A control circuit for turning on and off the signal processing circuit,
When the input signal detection circuit detects that the video signal is not input to the signal processing circuit, the control circuit turns off the signal processing circuit and based on the voltage of the output terminal, It is determined whether or not a video device is connected to the output terminal, and when the input signal detection circuit detects that the video signal is input to the signal processing circuit, a connection current detection circuit A semiconductor integrated circuit having a connection detection function configured to determine whether or not a video device is connected to the output terminal based on a detected current value output from the simulated output stage.   The control circuit outputs an external on / off control signal for turning on / off an external circuit of the semiconductor integrated circuit based on a detection result of whether or not the video signal is input in the input signal detection circuit. A semiconductor integrated circuit having a connection detecting function according to claim 1, wherein the semiconductor integrated circuit has a connection detecting function.   2. The semiconductor having a connection detection function according to claim 1, wherein the connection current detection circuit is configured to detect a value of a current output from the simulated output stage in response to a horizontal synchronization signal of the video signal. Integrated circuit.   The connection according to claim 3, wherein the connection current detection circuit is configured to detect a value of a current output from the simulated output stage corresponding to a horizontal synchronization signal and a luminance signal of the video signal. A semiconductor integrated circuit having a detection function. The output stage of the signal processing circuit includes a first high-potential side transistor in which one main terminal is connected to a first potential applying unit that applies a first potential, and a control terminal is connected to a previous video signal output terminal; One main terminal is connected to a second potential applying means for applying a second potential lower than the first potential, the other main terminal is connected to the other main terminal of the first high potential side transistor, and a control terminal is connected A first low potential side transistor connected to a previous video signal output terminal and configured to operate in a complementary manner with the first high potential side transistor, the other main main transistor of the first high potential side transistor A processed video signal is output from a connection point between the terminal and the other main terminal of the first low potential side transistor;
The simulated output stage includes a second high potential side transistor having one main terminal connected to a third potential applying means for applying the first potential and a control terminal connected to a control terminal of the first high potential side transistor. And one main terminal is connected to a fourth potential applying means for applying the second potential, the other main terminal is connected to the other main terminal of the second high potential side transistor, and a control terminal is connected to the first potential terminal. A second low potential side transistor connected to a control terminal of the low potential side transistor and configured to operate in a complementary manner with the second high potential side transistor;
The connection current detection circuit includes a third high-potential side transistor connected to a fifth potential applying unit, one main terminal applying the first potential, and a sixth main terminal applying the second potential to one main terminal. A third low potential side transistor connected to the potential applying means and having the other main terminal connected to the other main terminal of the third high potential side transistor; the other main terminal of the third high potential side transistor; Control of the control terminal of the third high potential side transistor and the control of the third low potential side transistor so as to maintain a connection point (hereinafter referred to as a specific connection point) with the other main terminal of the third low potential side transistor at a predetermined potential. Bias means for biasing the terminal, between one main terminal of the third high potential side transistor and the fifth potential applying means, and one main terminal of the third low potential side transistor and the sixth potential applying means A connection current detection resistor interposed between at least one of the first connection terminal and the specific connection point of the other main terminal of the second high potential side transistor and the other main terminal of the second low potential side transistor. The semiconductor integrated circuit which has a connection detection function of Claim 1 connected to the connection point with.   6. The semiconductor integrated circuit having a connection detection function according to claim 5, wherein the second potential is a GND potential, and the predetermined potential is higher than the GND potential.   6. The connection according to claim 5, wherein the first to third high-potential side transistors, the first to third low-potential side transistors, and the transistor that constitutes the bias unit are configured by MOS transistors. A semiconductor integrated circuit having a detection function.   6. The connection according to claim 5, wherein the first to third high-potential side transistors, the first to third low-potential side transistors, and the transistor that constitutes the bias unit are configured by bipolar transistors. A semiconductor integrated circuit having a detection function.

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