JP2010114249A - Semiconductor evaluation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor evaluation system for efficiently analyzing electrical characteristic variations of a semiconductor element included in a matrix array TEG. <P>SOLUTION: For example, a measurement system measures two or more types of matrix array TEGs included in each of a plurality of chips on a wafer, while changing their address one by one, and generates a measurement result file F21 for each chip. The matrix array TEG, further, includes two or more types of semiconductor element groups classified by address. A data processing computer receives the measurement result file F21, classifies it into a TEG folder F35, an element type folder F36 or the like, according to the name of the matrix array TEG and the measurement target address indicated in the file, and generates a measurement data file F38. The measurement data file F38 includes physical variables and the like, which are calculated based on a TEG structure definition file F42. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor evaluation system, and more particularly, to a technique effective when applied to a semiconductor evaluation system that processes measurement results of electrical characteristics of test semiconductor elements arranged in a matrix.

For example, for a single semiconductor element present in a plurality of chips arranged on a wafer, the electrical characteristic measurement results are stored, databased, and physical variables extracted from the measurement results, extracted physical variables Software is known that calculates the statistic. An example of such software is an electrical property evaluation system shown in Non-Patent Document 1.
“FabMeister-TG (Electrical Characteristics Evaluation System)”, [online], [searched on August 19, 2008], Internet <URL: http: // www. mizuho-ir. co. jp / science / fabmeisterg / index. html>

  In recent years, with the progress of miniaturization of semiconductor elements, variations in electrical characteristics due to natural phenomena, such as variations in the number of impurity ions contained in the elements, which have exactly the same design, have become a problem. There is a growing need to evaluate. For this reason, a large number of semiconductor elements having the same specifications are arranged in a matrix in each of a plurality of chips arranged on the wafer, and the electrical characteristics of these semiconductor elements are measured to evaluate variation in the electrical characteristics. It has been broken. A test element group (hereinafter referred to as TEG) in which a large number of semiconductor elements having the same specifications are arranged in this way is referred to as a matrix arrangement TEG (see FIG. 1).

  However, for example, conventional software represented by the electrical characteristic evaluation system of Non-Patent Document 1 cannot handle the measurement result of the matrix arrangement TEG having an arbitrary structure. For this reason, in order to analyze the measurement result of the matrix type arrangement TEG, calculation is performed individually for each type of the matrix type arrangement TEG and the types of semiconductor elements included therein using general statistical calculation software, etc. It took a lot of effort to analyze the measurement results.

  Accordingly, one of the objects of the present invention is to provide a semiconductor evaluation system capable of efficiently analyzing variations in electrical characteristics of semiconductor elements included in the matrix arrangement TEG. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  In the computer system constituting the semiconductor evaluation system according to the present embodiment, the chip arrangement information on the wafer surface, the matrix size of the matrix arrangement TEG, and what specifications in which position in the matrix arrangement TEG are previously set. Information necessary for calculating a physical variable and its statistic from the measurement result, such as whether a semiconductor element is arranged, is stored. In addition, the file describing the measurement results by the measurement apparatus also describes the type of the measured TEG, the bias and temperature at the time of measurement, and the address indicating the position of the measured semiconductor element in the matrix arrangement TEG. Keep it. This measurement result file is automatically generated by the measurement device after the measurement is completed, and is placed at a specific position in the storage device of the computer system via a network or the like. The computer system constantly monitors this position during operation, and every time a measurement result file is input, it calculates physical variables such as semiconductor device threshold values from the measurement result file, and averages or standard deviations of these variables. The statistic is calculated. Furthermore, the computer system manages these calculation results in a database, and allows these calculation results to be searched later using the type of semiconductor element, measurement conditions, and the like as search conditions. The computer system can display the search result on the screen on the spot or output it as a data file.

  As described above, the measurement result of the matrix arrangement TEG having an arbitrary structure, the physical variables indicating the characteristics of the semiconductor element calculated from the measurement result, and the statistics such as the average value and the standard deviation are automatically calculated. By using a system that stores and stores a database so that it can be searched later, it becomes possible to efficiently analyze variations in electrical characteristics of semiconductor elements.

  Of the inventions disclosed in this application, the effects obtained by the representative embodiments will be briefly described. It becomes possible to efficiently analyze the variation in electrical characteristics of the semiconductor elements included in the matrix arrangement TEG.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<Overall configuration of semiconductor evaluation system>
FIG. 2 is a block diagram showing an example of the configuration of the semiconductor evaluation system according to the first embodiment of the present invention. The semiconductor evaluation system shown in FIG. 2 includes a measurement system 30, a data processing computer 40, and a client server 50 that are connected to each other via a network 60. The measurement system 30 includes a wafer prober 10 and a measurement apparatus 20 that is electrically connected thereto. The measuring device 20 is connected to a data processing computer 40 via a network. The data processing computer 40 includes a hard disk 41, in which data processing software, measurement results received from the measurement system 30 via the network 60, physical variables derived from the measurement results, and measurement results are included. And statistical processing results of physical variables. The client server 50 can access the data processing computer 40 via the network 60, thereby obtaining various necessary information. Here, one client server 50 is connected to the network 60, but a plurality of client servers 50 may of course be connected.

<Configuration of wafer to be measured>
FIG. 3 is a plan view showing a configuration example of a semiconductor wafer to be measured in the semiconductor evaluation system of FIG. FIG. 1 is a schematic diagram showing a more detailed configuration example of the matrix arrangement TEG in FIG. As shown in FIG. 3, there are a plurality of semiconductor chips (appropriately abbreviated as chips) CP each having the same configuration inside a semiconductor wafer (appropriately abbreviated as wafer) WF. The sub-blocks are divided into a plurality (9 in this case) of sub-blocks SB11-13, SB21-23, and SB31-33 having different configurations. Furthermore, a plurality (here, four) of matrix type arrangements TEG (TEG_ARY_A to TEG_ARY_D) having different configurations are provided in each sub-block SB.

  In one matrix type arrangement TEG (TEG_ARY), as shown in FIG. 1, plural types (here, three types) of semiconductor element groups SEG_A to SEG_C are provided, and each of the semiconductor element groups SEG has the same type. The plurality of semiconductor elements SE. Each semiconductor group is classified by element size, for example. In this case, for example, the element size of the semiconductor element SE of SEG_A is different from the element size of the semiconductor element SE of SEG_B. The matrix type arrangement TEG (TEG_ARY) of FIG. 1 includes a row decoder DEC_R and a column decoder DEC_C. The measurement system 30 performs measurement while sequentially switching the semiconductor elements SE to be measured in the TEG_ARY by transmitting the element address designation signals to the TEG_ARY while sequentially switching them.

<Folder structure in the hard disk 41>
FIG. 4 is an explanatory diagram showing a folder structure example of the hard disk 41 in the data processing computer 40 in the semiconductor evaluation system of FIG. In FIG. 4, a data processing program is stored in a program storage folder F10. The measurement result file F21 from the measurement system 30 of FIG. 1 is temporarily input to the data input folder F20. In the database folder F30, the measurement data in the measurement result file F21 and the results of calculating physical quantities derived from the measurement data and statistics thereof are stored as a database. The condition folder F40 stores various files that describe conditions necessary for measurement data processing and search.

  Below the database folder F30, a lot folder F31, a group folder F32, a wafer folder F33, a sub-block folder F34, a TEG folder F35, an element type folder F36, and a measurement condition folder F37 are arranged in a tree structure. Further, a measurement data file F38 in which measurement data and physical variables calculated therefrom are recorded is arranged under the measurement condition folder F37. Here, for example, in the configuration example of FIGS. 1 and 3, nine sub-block folders 1 to 9 (F34) are created in the wafer folder 1 (F33) of FIG. Four TEG folders 1 to 4 (F35) are created in one sub-block folder 1 (F34). Further, three element type folders 1 to 3 (F36) are created in one TEG folder 1 (F35), and one element type folder 1 (F36) is included therein. , Measurement condition folders 1, 2,... (F37) corresponding to the number of different measurement conditions are created. Then, measurement data files 1 to 32 (F38) corresponding to the number of chips in the wafer (here, 32) are created in one measurement condition folder 1 (F37). Further, under the condition folder F40, a chip arrangement definition file F41, a TEG structure definition file F42, and a measurement condition file F43 are arranged.

<Structure in each file>
5A and 5B are explanatory diagrams showing an example of the structure in the measurement result file F21 in FIG. For example, when the semiconductor element SE to be evaluated is a field effect transistor (MOSFET), the measurement result file F21 is one for each element such as a threshold value (threshold voltage). There are a case where a value is returned and a case where a plurality of values are returned for each element like the Ids-Vgs characteristic, but both cases can be dealt with. FIG. 5A shows a case where the Ids-Vgs characteristic of the MOSFET is measured, and FIG. 5B shows a case where the threshold value of the MOSFET is measured. 5A and 5B, the lot number, group number, wafer number, chip number (chip coordinates), sub-block name, matrix type arrangement TEG name, measurement conditions, measurement date and time, and wafer size are described in the file. . Subsequently, the address (X, Y) indicating the position of the semiconductor element in the matrix arrangement TEG and the measurement data of the semiconductor element are output in parallel. Here, the group number is a number for identifying measurements when repeated measurement is performed under the same measurement conditions.

  FIG. 6 is an explanatory diagram showing a structural example in the chip arrangement definition file F41 in FIG. The chip arrangement definition file F41 describes the chip arrangement within the wafer WF plane. Here, for the chip placement method for an 8-inch wafer and the chip placement method for a 12-inch wafer, the range of chip coordinates and the chip coordinates that are invalid in the range are defined. By using this chip arrangement definition file F41, for example, when statistical processing is performed on the measurement result of each matrix type arrangement TEG included in the wafer WF as will be described later, the result is an image of the entire wafer WF. Can be visualized and displayed. Thereby, it is possible to easily determine the deviation of the characteristic distribution in the wafer WF plane.

  FIG. 7 is an explanatory diagram showing a structural example in the TEG structure definition file F42 in FIG. In the TEG structure definition file F42, the name of the sub-block in which each matrix type arrangement TEG is arranged, the name of the matrix type arrangement TEG, the type of the matrix type arrangement TEG (NMOS, PMOS, resistance element, capacitance element, etc.), matrix type A range of positions (addresses) for each type of semiconductor element (semiconductor element group SEG in FIG. 1) in the arrangement TEG is defined. In addition, conditions for calculating physical variables are defined, and comments for identifying the types of semiconductor elements are described. When the semiconductor element is a MOSFET, for example, a gate voltage when reading a determination current when calculating a constant current method threshold that is a physical variable indicating element characteristics, and an on-state current that is also a physical variable indicating element characteristics Is described.

  The data processing computer 40 receives the measurement result file F21 generated for each chip as shown in FIGS. 5A and 5B, and the lot number, group number, wafer number, sub-block name, matrix described therein Recognizing the mold arrangement TEG name, the lot folder F31 to the TEG folder F35 in FIG. 4 are classified. Next, the address (X, Y) of the matrix type arrangement TEG to be measured described in the measurement result file F21 is recognized, and the semiconductor elements in the matrix type arrangement TEG are referred to by referring to the TEG structure definition file F42 in FIG. Type (semiconductor element group SEG) is discriminated and classified into the element type folder F36 of FIG. Further, classification into the measurement condition folder F37 is performed based on the measurement conditions described in the measurement result file F21, and the measurement data in the measurement result file F21 is stored in the measurement data file in the corresponding measurement condition folder F37. Generate and store as F38. When generating the measurement data file F38, the TEG structure definition file F42 is referred to as necessary to calculate physical variables.

  FIG. 8 is an explanatory diagram showing a structural example in the measurement condition file F43 in FIG. The voltage applied to the semiconductor element during measurement and the temperature during measurement are described. After the measurement result file F21 is input to the data input folder F20, the measurement condition file F43 is used when the contents of the measurement result file F21 are classified and stored in the database folder F30 as described above. It is automatically created by extracting various measurement conditions described in the file F21. The measurement condition file F43 is provided so that a search for each measurement condition can be performed after making the database.

<Outline of data processing computer functions>
The data processing computer 40 reads measurement data from the measurement result file F21. The measurement data itself may be a physical variable indicating the characteristics of the semiconductor element, or the physical variable indicating the characteristics of the semiconductor element may be calculated from the measurement data. The statistic of the physical variable thus obtained is calculated. Here, the physical variable includes, for example, a constant current method threshold value, an extrapolation method threshold value, and an on-state current value if the semiconductor element to be evaluated is a MOSFET. Other examples include a resistance value when the semiconductor element is a resistance element, a capacitance value when the semiconductor element is a capacitance element, and an oscillation frequency when the semiconductor element is a ring oscillator. These data are stored in a database so that they can be searched based on search conditions such as group number, lot number, chip number, TEG name, element type name, element address, and measurement conditions.

<Description of detailed operation of semiconductor evaluation system>
FIG. 9 is a flowchart showing an example of the operation of the semiconductor evaluation system of FIG.

<< Measurement data input and calculation process >>
First, the measurement apparatus 20 performs a predetermined measurement on the wafer WF, and transfers the measurement result for each semiconductor chip CP to the data processing computer 40 as a measurement result file F21. The data processing computer 40 downloads the measurement result file F21 onto the hard disk 41 (S11), and moves it to the data input folder F20 (S12). While the data processing computer 40 is running, the data input folder F20 is constantly monitored by the matrix arrangement TEG measurement data processing program in the program storage folder F10, and the measurement data file F21 is input to the data input folder F20. As soon as this is done, extraction of physical variables and calculation of statistics of these physical variables are started. Then, physical variables of each semiconductor element SE are extracted based on the TEG name and element address described in the measurement result file F21 and the TEG structure definition file F42, and the semiconductor element type (semiconductor element group SEG) in the chip is extracted. ) Statistics such as the average value and standard deviation of the physical variables are calculated (S13). Here, for example, when the physical variable to be extracted is the extrapolation threshold value of the MOSFET, the calculation method can be changed between the linear region and the saturation region. If the physical variable itself is described as the measurement result, the physical variable calculation operation is skipped.

  Further, the data processing computer 40 sorts the physical variables obtained for each semiconductor element type in order of magnitude, and creates a cumulative frequency distribution graph (S14). Next, these measurement data (the values of the physical variables obtained in S13 and S14 and their statistics, the sorting result in order of magnitude, and the cumulative frequency distribution graph) are measured as described with reference to FIG. Are classified into folders (lot folder F31 to measurement condition folder F37) and stored as a measurement data file F38 (S15). Further, statistics such as an average value and a standard deviation for each wafer are calculated for physical variables of the same type of semiconductor elements (same semiconductor element group SEG) among the semiconductor elements SE in the wafer WF plane (S16). . This process may be performed by referring to the measurement data files F38 corresponding to the number of semiconductor chips to be included in one measurement condition folder F37 in FIG. Further, sorting is performed in order of physical variables in units of wafer WF, and a cumulative frequency distribution graph is created (S17). The obtained statistical quantity in the wafer WF plane is also stored as one of the measurement data files F38 (S18).

<< Search for measurement data >>
The user uses the data processing computer 40 or the client server 50 to input search conditions such as a group number, lot number, chip number, TEG name, semiconductor element type name, and measurement bias condition (S19). Based on the search condition, the data processing computer 40 outputs the measurement results of the semiconductor elements stored in the hard disk 41, the physical variables calculated therefrom, the statistics thereof, the sorting results, and the cumulative frequency distribution graph (S20). ). The measurement result for each semiconductor element and the physical variable calculated from the measurement result can be output together with the address indicating the arrangement position of the semiconductor element. The search result output method can be displayed on the screen of the data processing computer 40 or the client server 50, or can be written to a data file.

<Main Effects of Semiconductor Evaluation System of First Embodiment>
When the semiconductor evaluation system according to the first embodiment is used, a physical variable of a semiconductor element is calculated from the measurement result of electric characteristics of a plurality of semiconductor elements included in a matrix arrangement TEG having an arbitrary structure, and this average is calculated. Statistics, such as values and standard deviation, and sorting in order of size can be calculated automatically. As a result, it is possible to efficiently analyze the variation in electrical characteristics of the semiconductor elements included in the matrix arrangement TEG, thereby shortening the analysis time and facilitating the analysis.

(Embodiment 2)
In addition to the functions of the first embodiment, the semiconductor evaluation system of the second embodiment determines whether a physical variable calculated from the measurement result of a semiconductor element is an abnormal value based on statistical test theory. It is characterized by having the function to do. Hereinafter, description will be made focusing on differences from the first embodiment.

<Folder structure in the hard disk 41>
FIG. 10 is an explanatory diagram showing a folder structure example of the hard disk 41 in the data processing computer 40 of FIG. 2 in the semiconductor evaluation system according to the second embodiment of the present invention. As shown in FIG. 10, the test condition file F44 is arranged under the condition folder F40 among the folders in the hard disk 41.

<Structure in test condition file F44>
FIG. 11 is an explanatory diagram showing a structural example in the test condition file F44 in FIG. In the verification condition file F44 of FIG. 11, determination conditions used for chip level verification and wafer level verification for each element number (ie, corresponding to the type of semiconductor element (semiconductor element group SEG)) included in each matrix type arrangement TEG. Is described. As judgment conditions, the significance level at the time of chip level verification, the significance level at the time of wafer level verification, and a condition for determining whether or not to reject a chip when there are a large number of semiconductor elements to be rejected by the chip level verification in the chip ( Nrjc).

<Description of detailed operation of semiconductor evaluation system>
FIG. 12 is a flowchart showing an example of the operation of the semiconductor evaluation system according to the second embodiment of the present invention. The data processing computer 40 in FIG. 2 first performs a test at the chip level. This test is hereinafter referred to as a chip level test. As shown in FIG. 9, among the physical variables sorted in order of size for each semiconductor element type in the chip, whether or not the maximum value and the minimum value are abnormal values is determined based on statistical test theory. (S101). For example, if the semiconductor element is a MOSFET and the measurement data is Ids-Vgs measurement, a constant current method threshold value, an extrapolation method threshold value, or an on-state current is used as the physical variable used for determination. When only the threshold value or on-state current is directly measured and output by the measurement system, the value may be used for determination. As the test theory, for example, there is a so-called Grubbs-Smirnov rejection test method. The significance level value used for the chip level test is read from the test condition file F44.

  Here, if both the maximum value and the minimum value are not rejected, it is assumed that there is no abnormal element in the target chip, and the chip level test is terminated (S102). When it is determined that the maximum value or the minimum value is an abnormal value, the value is rejected, and a flag is set for the corresponding semiconductor element item in the measurement data file F38 (S103). As a result, when the measurement result is output, a flag indicating the test result can be output at the same time, so that the address of the semiconductor element in the matrix arrangement TEG can be immediately determined. Except for the physical variables rejected previously, the maximum and minimum values are selected again and the test is performed (S104). S101 to S104 are repeated, and the chip level test is performed until there are no more abnormal values. The number N of measurement values rejected at this time is recorded in the measurement data file F38 and becomes one of the judgment criteria in the next wafer level test. At the stage where the chip level test is completed, the statistic of the physical variable for each type of semiconductor element in each chip is calculated again using only the data of the element that has not been rejected, and the statistic after the test is stored in the measurement data file F38. Record (S105).

  Next, a wafer level test is performed based on the statistics of each chip and the number N of rejected measurement values. If N is greater than or equal to the determination value Nrjc described in the test condition file F44 for a certain chip, the chip is rejected as being abnormal (S106). In addition, the test is performed using a test theory such as the Grabs-Smirnov Rejection Test with the average value and standard deviation of each chip as one physical variable. Similar to the chip level test, first, the maximum and minimum values of physical variables are tested (S107). At this time, as the significance level used for the test, the value described in the test condition file is used. If there is no abnormal value, the test is terminated (S108). If there is an abnormal value, the corresponding chip is flagged and recorded in the measurement data file F38 so that it can be known which chip has been rejected when the measurement result is retrieved and output (S109). The abnormal value is removed, and the maximum / minimum value is selected again and the test is performed (S110). The test is repeated until there are no abnormal chips by repeating S107 to S110. Finally, the statistic is recalculated by excluding chips rejected in the wafer unit test (S111).

<Main effects of the semiconductor evaluation system according to the second embodiment>
When the semiconductor evaluation system of the second embodiment is used, in addition to the effects described in the first embodiment, the measurement abnormal value can be automatically determined, which is necessary for the analysis of the variation in the electrical characteristics of the semiconductor element. Freed from work to remove measurement abnormal values. In addition, by describing the test conditions in the test condition file, it is possible to automatically test a plurality of types of semiconductor elements according to arbitrary determination conditions that can be set for each semiconductor element.

(Embodiment 3)
In addition to the functions of the second embodiment, the semiconductor evaluation system according to the third embodiment automatically records measurement results and semiconductor elements that are frequently referred to in the automatic report definition file. It is characterized by the ability to output related physical variables. Hereinafter, the description will be made focusing on differences from the second embodiment.

<Folder structure in the hard disk 41>
FIG. 13 is an explanatory diagram showing a folder structure example of the hard disk 41 in the data processing computer 40 of FIG. 2 in the semiconductor evaluation system according to the third embodiment of the present invention. As shown in FIG. 13, among the folders in the hard disk 41, an automatic report definition file F45 is arranged under the condition folder F40.

<Structure in automatic report definition file F45>
FIG. 14 is an explanatory diagram showing a structural example in the automatic report definition file F45 in FIG. In the automatic report definition file F45 of FIG. 14, the serial number, sub-block name, matrix type arrangement TEG for specifying the semiconductor element for which the measurement result, the physical variable calculated therefrom, and the statistic are to be output automatically are included. The name and type, element number, and measurement bias number are described. The names and types of sub-block names, matrix type arrangement TEGs, element numbers, and measurement bias numbers correspond to the classifications of sub-block folder F34, TEG folder F35, element type folder F36, and measurement condition folder F37 in FIG. 13, respectively. It is.

<Description of detailed operation of semiconductor evaluation system>
FIG. 15 is a flowchart showing an example of the operation of the semiconductor evaluation system according to the third embodiment of the present invention. The data processing computer 40 in FIG. 2 first reads the automatic report definition file F45, and automatically determines the type of semiconductor element that outputs the result (S201). Next, the chip level average value, standard deviation, cumulative frequency distribution, wafer level average value, standard deviation, cumulative frequency distribution, etc. of the physical variables are output to the file for the semiconductor element read in S201 (S202). .

<Main effects of the semiconductor evaluation system according to the third embodiment>
By using the semiconductor evaluation system of the third embodiment, in addition to the effects described in the second embodiment, it is possible to automatically output measurement results of semiconductor elements that are frequently output and physical variables calculated therefrom. Thus, the labor required for data retrieval is reduced.

(Embodiment 4)
The semiconductor evaluation system of the fourth embodiment is characterized in that in addition to the functions of the third embodiment, the semiconductor evaluation system has a function of calculating physical variables other than the threshold value and the on-current in the MOSFET. Here, physical variables such as subthreshold coefficient (S value), transconductance (gm), drain-inductive barrier-lowering (DIBL), substrate bias constant (γ), and forward / reverse difference (F−R difference) It has a calculation function. At this time, it is possible to specify conditions such as how many measurement data are used and which measurement bias data is used. Hereinafter, the description will be made focusing on differences from the third embodiment.

<Folder structure in the hard disk 41>
FIG. 16 is an explanatory diagram showing a folder structure example of the hard disk 41 in the data processing computer 40 of FIG. 2 in the semiconductor evaluation system according to the fourth embodiment of the present invention. As shown in FIG. 16, among the folders in the hard disk 41, a physical variable calculation condition file F46 is arranged under the condition folder F40.

<Structure in physical variable calculation condition file F46>
FIG. 17 is an explanatory diagram showing a structural example in the physical variable calculation condition file F46 in FIG. For example, when calculating the S value, gm, and extrapolation method threshold value using measurement data, it is necessary to obtain the slope by linear fitting of the measurement data. You need to decide what to do. For this reason, the physical variable calculation condition file F46 of FIG. 17 describes the number of measurement points used when calculating these physical quantities. Based on this score, each physical quantity is calculated from the measurement data.

<Condition specification from data processing computer or client server>
On the other hand, in order to calculate DIBL, γ, and FR difference, it is necessary to select the measurement results based on two types of measurement bias conditions. Here, the user inputs this measurement bias condition from the data processing computer 40 or the client server 50.

<Description of detailed operation of semiconductor evaluation system>
FIG. 18 is a flowchart showing an example of the operation of the semiconductor evaluation system according to the fourth embodiment of the present invention. Here, an operation example when calculating the S value, gm, and extrapolation method threshold value will be described. The data processing computer 40 of FIG. 2 first reads the physical variable calculation condition file F46 and determines how many measurement points are used when calculating the S value, gm, and extrapolation method threshold value (S300). . The measurement data for the number of points read here is cited from the measurement data file F38, and the S value, gm, and extrapolation method threshold value are calculated (S310). Then, the calculation result is output to an output device such as a screen of the data processing computer 40 or the client server 50 (S320).

  FIG. 19 is a flowchart showing another example of the operation in the semiconductor evaluation system according to Embodiment 4 of the present invention. Here, an operation example when calculating DIBL, γ, and FR difference will be described. First, the user uses the data processing computer 40 or the client server 50 to specify two types of bias sets used to calculate DIBL, γ, and FR differences (S330). The data processing computer 40 in FIG. 2 reads measurement data corresponding to the two types of bias sets from the measurement data file F38, and calculates DIBL, γ, and FR differences (S340). Then, the calculation result is output to an output device such as a screen of the data processing computer 40 or the client server 50 (S350).

<Main Effects of Semiconductor Evaluation System of Fourth Embodiment>
By using the semiconductor evaluation system of the fourth embodiment, in addition to the effects described in the third embodiment, it becomes possible to automatically calculate physical variables that are often used for MOSFET analysis, and to analyze the electrical characteristic variation of the MOSFET. Can reduce labor. In addition, it becomes possible to specify a combination of the number of measurement points and measurement bias conditions used for the calculation of the physical variable, and it is possible to calculate the physical variable under conditions according to an arbitrary request by the user.

(Embodiment 5)
The semiconductor evaluation system of the fifth embodiment is characterized in that in addition to the functions of the fourth embodiment, a function for displaying the correlation between physical variables of semiconductor elements is provided. The folder structure in the hard disk 41 used in this semiconductor evaluation system is the same as in FIG.

<Description of detailed operation of semiconductor evaluation system>
FIG. 20 is a flowchart showing an example of the operation of the semiconductor evaluation system according to the fifth embodiment of the present invention. First, a user inputs two physical variable types (physical variable A and physical variable B) whose correlation is to be displayed from the data processing computer 40 or the client server 50 (S400). For the physical variable A and the physical variable B, the data processing computer 40 obtains the calculation result based on the measurement data stored in the measurement data file F38 or the calculation result stored in the measurement data file F38. Acquired by reading. Using this acquired data, the data processing computer 40 uses a plurality of semiconductors in the matrix arrangement TEG with the physical variable A for the one semiconductor element in the matrix arrangement TEG as the horizontal axis and the physical variable B as the vertical axis. The data for the elements are plotted on one graph (S410). Then, the created graph is output to an output device such as a screen of the data processing computer 40 or the client server 50 (S420).

<Main effects of the semiconductor evaluation system according to the fifth embodiment>
By using the semiconductor evaluation system of the fifth embodiment, in addition to the effects described in the fourth embodiment, it is possible to automatically output the correlation between physical parameters of the semiconductor element, which is often used for analysis of the semiconductor element. Thus, the labor required for analysis can be reduced.

(Embodiment 6)
The semiconductor evaluation system of the sixth embodiment is characterized in that in addition to the functions of the fifth embodiment, the semiconductor evaluation system has a function of separating the electrical characteristic variation of the semiconductor element into a random component and a systematic component. The electrical characteristic variation is generally classified into a random component and a systematic component (for example, refer to the reference “IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING”, VOL.17, NO.2, May 2004, p.155-165). . Since the method for reducing the variation in electrical characteristics differs from component to component, it is important to separate these components in analyzing the variation in electrical properties. The folder structure in the hard disk 41 used in this semiconductor evaluation system is the same as in FIG.

<Description of detailed operation of semiconductor evaluation system>
As a method of performing component separation, for example, a method using a fourth-order polynomial described in the above-mentioned reference, a method of dividing the matrix type arrangement TEG into small matrices, or a physical variable between adjacent addresses There are three methods for calculating the difference. First, an operation example when performing component separation using a method using a fourth-order polynomial will be described with reference to FIG.

In FIG. 21, first, for example, a user or the like uses the data processing computer 40 or the client server 50 to select a wafer, a chip, a matrix arrangement TEG type, a semiconductor element type, and a measurement condition for which component separation is to be performed. (S500). Similarly, the user or the like selects a physical variable for component separation (S510). As a result, the data processing computer 40 fits the selected physical variable M with the fourth-order polynomial expressed by the equation (1), with the X address and Y address in the matrix arrangement TEG as X and Y, respectively, and the coefficient a _{0 to} a ₁₄ are obtained (S520).

_{M = a 0 + a 1 x} + a 2 y + a 3 x 2 + a 4 xy + a 5 y 2 + a 6 x 3 + a 7 x 2 y + a 8 xy 2 + a 9 y 3 + a 10 x 4 + a 11 x 3 y + a 12 x 2 y 2 + a 13 xy ³ + a ₁₄ y ⁴ (1)
Here, at each address, the data processing computer 40 substitutes X, Y and the previously obtained values of a _{0 to} a ₁₄ into the formula (1), and uses the values obtained thereby as systematic components of physical variables. Calculate as Also, a random component is calculated by subtracting the systematic component from the physical variable at each address (S530). Then, statistics such as systematic components, random components, median values, and standard deviations of each address are output to the screen of the data processing computer 40 or the client server 50 (S540).

  Next, an operation example when performing component separation using a method of dividing into small scale matrices will be described with reference to FIG. In FIG. 22, first, for example, a user or the like uses the data processing computer 40 or the client server 50 to select a wafer, a chip, a type of matrix arrangement TEG, a type of semiconductor element, and a measurement condition for which component separation is to be performed. (S600). Similarly, the user or the like selects a physical variable for component separation (S610). Next, the data processing computer 40 designates a matrix size smaller than the size of the matrix type arrangement TEG, and divides the matrix type arrangement TEG into small matrices of the designated scale. Subsequently, the data processing computer 40 calculates an average value for each of the divided small matrices, and sets the average value as a systematic component in the small matrix (S620). Next, a random component is obtained by subtracting the systematic component of the submatrix to which the address belongs from the physical variable of each address (S630). Then, statistics such as the systematic component, random component, average value, and standard deviation of each address are output to the screen of the data processing computer 40 or the client server 50 (S640).

  Next, an operation example in which component separation is performed using a method of calculating a physical variable difference between adjacent addresses will be described with reference to FIG. 23, first, for example, a user or the like uses the data processing computer 40 or the client server 50 to select a wafer, a chip, a type of matrix arrangement TEG, a type of semiconductor element, and a measurement condition for which component separation is to be performed. (S700). Similarly, the user or the like selects a physical variable for component separation (S710). Next, the data processing computer 40 calculates a physical variable amount difference ΔM_pair between adjacent addresses. Further, the standard deviation of ΔM_pair is calculated, and a value obtained by multiplying it by (1 / √2) is set as σM_random (S720). This value corresponds to a random component of the variation of the physical variable M. Further, assuming that the standard deviation of the physical variable M itself is σM, the systematic component σM_systematic of the variation of the physical variable M is obtained by Expression (2) (S730). Then, σM_systematic and σM_random are output to the screen of the data processing computer 40 or the client server 50 (S740).

σM_systematic = √ (σM ² −σM_random ² ) (2)
<Main Effects of Semiconductor Evaluation System of Sixth Embodiment>
When the semiconductor evaluation system of the sixth embodiment is used, in addition to the effects described in the fifth embodiment, it becomes possible to automatically separate the electrical characteristic variation of the semiconductor element into a random component and a systematic component, which is necessary for the analysis. Labor can be reduced.

(Embodiment 7)
In addition to the functions of the sixth embodiment, the semiconductor evaluation system of the seventh embodiment uses the measurement results or physical variables calculated from the measurement results to perform measurement on the matrix arrangement TEG. A feature is that it has a function of verifying whether a signal voltage for designating an address has been correctly applied.

<Configuration in measurement system 30>
FIG. 24 is a schematic diagram showing a configuration example in the measurement system 30 in the semiconductor evaluation system according to the seventh embodiment of the present invention. In the measurement system 30 shown in FIG. 24, a wafer (not shown) is installed in the wafer prober 10, and a matrix arrangement TEG (TEG_ARY) is formed on the wafer WF. Normally, a plurality of TEG_ARYs are formed on the wafer WF, but one of them is shown here representatively. On each TEG_ARY, an address designation signal input pad PD_ADD is formed.

For example, if the matrix size of the TEG_ARY in the X direction and the Y direction is 2 ^{(N + 1)} × 2 ^{(N + 1)} , N + 1 pads from X ₀ to X _N for addressing in the X direction are used for addressing in the Y direction. from Y ₀ to _{Y N} N + 1 pieces of pads are formed. When representing the X and Y addresses in binary, if tens of ^{2 M} X address is 1, the voltage VDD (1V to 5V), if positions of the ^{2 M} is 0, 0V to putt _{X M} Apply. Similarly, when the 2 ^M place of the Y address is 1, the voltage VDD (1 V to 5 V) is applied to the pad Y _M when the 2 ^M place is 0. Based on the input signal, the decoder provided in the TEG_ARY selects an element to be measured.

  The address designation signal input pad PD_ADD is electrically connected by a probe 210 provided in the probe card 200. Further, the probe card 200 is electrically connected by a pogo pin 310 provided in the test head 300. The test head 300 is electrically connected to the control device 330 through the coaxial cable 320. The addressing signal output from the control device 330 is input to the TEG_ARY decoder via the coaxial cable 320, the test head 300, the pogo pin 310, the probe card 200, the probe 210, and the addressing signal input pad PD_ADD.

<Folder structure in the hard disk 41>
FIG. 25 is an explanatory diagram showing a folder structure example of the hard disk 41 in the data processing computer 40 of FIG. 2 in the semiconductor evaluation system according to the seventh embodiment of the present invention. As shown in FIG. 25, among the folders in the hard disk 41, a connection inspection condition file F47 is arranged under the condition folder F40.

<Structure in connection inspection condition file F47>
FIG. 26 is an explanatory diagram showing a structural example in the connection inspection condition file F47 in FIG. In the connection inspection condition file F47 shown in FIG. 26, a difference determination probability D [%] and a maximum determination number Jmax for determining whether there is a difference between physical variables are described.

<Description of detailed operation of semiconductor evaluation system>
FIG. 27 is a flowchart showing an example of the operation of the semiconductor evaluation system according to the seventh embodiment of the present invention. In this operation example, it is verified that the addressing signal is correctly applied to the measurement target element. Here as an example, but to verify whether the addressing signal to the pad X _N is applied correctly, it can be verified in the same manner other pads. In FIG. 27, first, the data processing computer 40 compares the physical variable at the address (X, Y) = (0, 0) with the physical variable at the address (X, Y) = (2 ^N , 0). It is verified whether there is a difference (S800). Here, “there is a difference” indicates that the relative error [%] between physical variables is larger than the difference determination probability D [%] described in the connection inspection condition file F47. If there is a difference, it is determined that there was no abnormality in the signal input to the pad X _N.

On the other hand, if there is no difference, the physical variable at address (X, Y) = (0, 1) is compared with the physical variable at address (X, Y) = (2 ^N , 1) (S810). If there is a difference here, it is determined that there was no abnormality in the signal input to the pad X _N. If there is no difference, the physical variable at the address (X, Y) = (0, 2) is compared with the physical variable at the address (X, Y) = (2 ^N , 2) (S820). If there is a difference here, it is determined that there was no abnormality in the signal input to the pad X _N. If there is no difference, S820 is repeated until the Y address reaches Jmax while increasing the Y address to be compared one by one. When the Y address becomes Jmax, the physical variable at the address (X, Y) = (0, Jmax) is compared with the physical variable at the address (X, Y) = (2 ^N , Jmax) (S830). if there is a difference, it is determined that there was no abnormality in the signal input to the pad X _N. Also it determined that if there was no difference, it is possible that there is an abnormality in the signal input to the pad X _N.

<Main Effects of Semiconductor Evaluation System of Embodiment 7>
When the semiconductor evaluation system of the seventh embodiment is used, in addition to the effects described in the sixth embodiment, the connection state of the signal line can be verified based on the measured value, and the load for separately testing the connection state is reduced. The

  The main functions of the semiconductor evaluation system described in the first to seventh embodiments are summarized as follows.

  First, the semiconductor evaluation system according to the present embodiment stores a large amount of measurement data of a plurality of types of matrix arrangement TEGs of arbitrary scales, and further calculates physical variables indicating element characteristics from the measurement data. Further, it has a function of calculating statistics such as the average value and standard deviation and storing these calculation results quickly and easily. Secondly, it has a function of searching the measurement result, the physical variable calculated from the measurement result, and the calculation result of the statistic thereof based on the element type, the address representing the element position, and the measurement condition. Thirdly, it has a function of determining a measurement abnormal value by giving a determination condition in advance.

  Fourth, by specifying the type of semiconductor element and the measurement conditions, the average value, standard deviation, and cumulative frequency distribution of the physical variables indicating the characteristics of the semiconductor elements in the matrix arrangement TEG for each chip and for each wafer can be obtained. It has a function to output automatically. Fifth, it has a function of changing a method for calculating a physical variable indicating the characteristics of a semiconductor element according to designation. Sixth, it has a function of displaying the correlation between physical variables representing the characteristics of semiconductor elements for each chip and for each wafer. Seventh, it has a function of separating the characteristic variation of the semiconductor element characteristics into a systematic component and a random component. Eighth, using the measurement result of the semiconductor element characteristics or the physical variable calculated from the measurement result, the signal voltage for specifying the address of the element to be measured on the matrix type arrangement TEG in the measurement system is correctly applied. A function to verify whether or not

  As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The semiconductor evaluation system according to the present embodiment is particularly useful when applied to a computer system and computer software for processing measurement data for a semiconductor device including a matrix arrangement TEG.

FIG. 4 is a schematic diagram illustrating a more detailed configuration example of a matrix-type arrangement TEG in FIG. 3. In the semiconductor evaluation system by Embodiment 1 of this invention, it is a block diagram which shows an example of the structure. 3 is a plan view showing a configuration example of a semiconductor wafer to be measured in the semiconductor evaluation system of FIG. FIG. 3 is an explanatory diagram showing an example of a folder structure of a hard disk in the data processing computer in the semiconductor evaluation system of FIG. 2. It is explanatory drawing which shows the structural example in the measurement result file in FIG. It is explanatory drawing which shows the other structural example in the measurement result file in FIG. FIG. 5 is an explanatory diagram showing a structure example in a chip arrangement definition file in FIG. 4. It is explanatory drawing which shows the structural example in the TEG structure definition file in FIG. It is explanatory drawing which shows the structural example in the measurement condition file in FIG. FIG. 3 is a flowchart showing an example of the operation in the semiconductor evaluation system of FIG. 2. FIG. 5 is an explanatory diagram showing an example of a folder structure of a hard disk in the data processing computer of FIG. 2 in the semiconductor evaluation system according to the second embodiment of the present invention. It is explanatory drawing which shows the structural example in the test condition file in FIG. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 2 of this invention. In the semiconductor evaluation system by Embodiment 3 of this invention, it is explanatory drawing which shows the folder structural example of the hard disk in the computer for data processing of FIG. It is explanatory drawing which shows the structural example in the automatic report definition file in FIG. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 3 of this invention. In the semiconductor evaluation system by Embodiment 4 of this invention, it is explanatory drawing which shows the folder structure example of the hard disk in the computer for data processing of FIG. It is explanatory drawing which shows the structural example in the physical variable calculation condition file in FIG. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 4 of this invention. It is a flowchart figure which shows an example of another operation | movement in the semiconductor evaluation system by Embodiment 4 of this invention. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 5 of this invention. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 6 of this invention. It is a flowchart figure which shows an example of an operation | movement different from FIG. It is a flowchart figure which shows an example of an operation | movement different from FIG. In the semiconductor evaluation system by Embodiment 7 of this invention, it is the schematic which shows the structural example in the measurement system. In the semiconductor evaluation system by Embodiment 7 of this invention, it is explanatory drawing which shows the folder structure example of the hard disk in the computer for data processing of FIG. It is explanatory drawing which shows the structural example in the connection test | inspection condition file in FIG. It is a flowchart figure which shows an example of the operation | movement in the semiconductor evaluation system by Embodiment 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wafer prober 20 Measuring apparatus 200 Probe card 210 Probe 30 Measuring system 300 Test head 310 Pogo pin 320 Coaxial cable 330 Controller 40 Data processing computer 41 Hard disk 50 Client server 60 Network CP chip DEC_C Column decoder DEC_R Row decoder PD_ADD, X _{0 to} X _N , Y _{0 to} Y _N Addressing signal input pad SB Sub block SE Semiconductor element SEG Semiconductor element group TEG_ARY Matrix type arrangement TEG
WF wafer

Claims (5)

A semiconductor evaluation system for processing measurement data for a plurality of types of matrix-type arrangement TEG included in each of a plurality of semiconductor chips formed in a semiconductor wafer, realized by a computer system,
Each of the plurality of types of matrix-type arrangements TEG includes a plurality of types of semiconductor element groups sorted by address ranges,
Each of the plurality of types of semiconductor element groups is composed of a plurality of semiconductor elements of the same type arranged in a matrix,
Each of the plurality of semiconductor elements is configured to be a measurement target by inputting an address to the matrix arrangement TEG to which the semiconductor element belongs,
The measurement data includes an identifier for identifying the types of the plurality of semiconductor chips and the plurality of types of matrix-type arrangement TEG, the address, and the measurement result of the semiconductor element corresponding to the address,
The computer system includes:
Conditions required for calculating physical variables representing electrical characteristics for a plurality of semiconductor elements included in each of the plurality of types of semiconductor element groups and the correspondence relationship between the addresses and the plurality of types of semiconductor element groups And a first process for preliminarily storing a definition file in which
Referring to the identifier in the definition file and the measurement data, a second process for classifying and storing the measurement data for each type of the matrix arrangement TEG or for each of the plurality of types of semiconductor element groups;
Referring to the definition file, the physical variable is calculated from the measurement results of each of the plurality of semiconductor elements included in the measurement data, and the average value or standard of the physical variable is calculated for each of the plurality of types of semiconductor element groups. A semiconductor evaluation system that performs a third process of calculating a statistic such as a deviation and storing the calculation result. The semiconductor evaluation system according to claim 1,
The computer system further performs a fourth process of calculating a statistic of the physical variable for each of the semiconductor wafers and storing the calculation result. The semiconductor evaluation system according to claim 1,
The computer system further sorts the target physical variables when calculating the statistics for each of the plurality of types of semiconductor element groups, and checks whether there is an abnormality with respect to the maximum value or the minimum value. The semiconductor evaluation system is characterized in that if there is an abnormality, the corresponding physical variable is excluded and the statistic is calculated again. The semiconductor evaluation system according to claim 1,
The computer system further executes a fifth process of calculating a systematic component and a random component of the calculation result from the calculation result of the physical variable for each of the plurality of types of semiconductor element groups. system. The semiconductor evaluation system according to claim 1,
Each of the plural types of matrix type arrangement TEG includes an X address pad composed of a plurality of bits and a Y address pad composed of a plurality of bits.
The address includes an X address applied to the X address pad and a Y address applied to the Y address pad.
The computer system refers to each measurement result or physical variable when one of the X address or the Y address is fixed and the other is changed, and based on the difference in the measurement result or physical variable. A semiconductor evaluation system for executing a sixth process for determining whether or not the X address or the Y address is correctly applied to the X address pad or the Y address pad.

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