JP2010113544A - Timer value generation device and timer value generation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timer value generation device and a timer value generation method, allowing detection of abnormality of a timer value generated by use of two or more timers. <P>SOLUTION: The timer value generation device has: a first timer having a first timer value wherein a signal of a prescribed period is counted by one of subtraction and addition; a second timer having a second timer value wherein a frequency at which a counted number exceeds a representation range of the first timer value is counted; and a generation part generating a third timer value wherein a range wider than the representation range of the first timer value is counted based on the first timer value and the second timer value. The timer value generation device also has a detection part detecting the abnormality of the third timer value when deciding that a difference between the precedingly read first timer value and the first timer value newly read after reading the second timer value is not a difference occurring by the subtraction or the addition. Thereby, the abnormality occurring by generating the third timer value can be detected based on the first timer value before the first timer value exceeds the representation range, and the second timer value after the excess. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a timer value generating apparatus and a timer value generating method using two or more timers.

  2. Description of the Related Art In recent years, vehicles include a plurality of control devices (ECU: Electronic Control) such as an engine control device that controls ignition timing of an engine mounted on the vehicle, a body control device that controls opening and closing of a door, and an audio control device that controls audio. Control Unit) is installed. The plurality of control devices perform control processing in synchronization with each other by communicating with each other via a connected network. Here, in order for these control devices to acquire control timing or communication timing with high accuracy by executing control processing or communication processing, it is necessary to acquire an accurate timer value representing the timer time.

  However, if the frequency division ratio of the timer providing the timer value is reduced, the control device can surely obtain a highly accurate timer value, but only a narrow range of timer values can be obtained directly. Further, it is not practical to extend the range of timer values that can be provided by the timer indefinitely from the current situation where the demand for cost reduction is severe. For this reason, there is known a timer that can provide a timer value in a wider range than individual timers by using a first timer that provides a lower bit of a timer value representing a timer time and a second timer that provides an upper bit. (For example, refer to Patent Document 1).

JP 2006-155493 A

  By the way, the timer described in Patent Document 1 combines the value of the first timer that provides the lower bit and the value of the second timer that provides the upper bit by executing software processing to obtain a timer value that represents the timer time. Is generated. The first timer outputs a predetermined signal to the second timer when an overflow occurs, and the second timer receives the predetermined signal and updates the value.

  For this reason, as shown in FIG. 6, when there is an overflow of the first timer and an update of the second timer from the time when the first timer is read to the time when the second timer is read, The value of the first timer before overflowing and the value of the second timer after overflowing are combined. Therefore, the above timer has a problem that it generates a timer value indicating an abnormal time at a specific timing.

  Accordingly, an object of the present invention is to provide a timer value generation device and a timer value generation method capable of detecting an abnormality in a timer value generated using two or more timers.

  The timer value generation device according to the present invention includes a first timer having a first timer value for counting a signal input at a predetermined cycle by performing either one of a subtraction process or an addition process, and the counted number is Based on a second timer having a second timer value for counting the number of times the first timer value expression range has been exceeded, a first timer value read from the first timer, and a second timer value read from the second timer And a generation unit that generates a third timer value that counts a range wider than the expression range of the first timer value, the first timer counts the expression range of the first timer value by the counted number. If it exceeds, an initialization process is performed to change the first timer value to a predetermined value, and the generation unit reads the second timer value from the second timer after reading the first timer value from the first timer. , 1st timer value When the difference between the first timer value read again after reading the second timer value and the first timer value read earlier is not the difference caused by the subtraction process or addition process performed by the first timer And a detecting unit for detecting an abnormality of the third timer value generated by the generating unit.

  In the above configuration, the generation unit generates the third timer value based on the first timer value read again and the second timer value read again when the detection unit detects an abnormality. Can be adopted.

  In the above configuration, the first timer and the second timer may be configured by hardware circuits, and the generation unit may be configured to be realized by software processing.

  In the above configuration, the detection unit may employ a configuration for detecting an abnormality of the third timer value generated by the generation unit when the difference exceeds a predetermined value.

  The timer value generation method according to the present invention includes a first generation step of generating a first timer value for counting a signal input at a predetermined cycle by performing either one of a subtraction process or an addition process, A second generation step of generating a second timer value for counting the number of times that the number exceeds the expression range of the first timer value, a first timer value read from the first timer, and a second timer value read from the second timer And a third generation step of generating a third timer value for counting a wider range than the expression range of the first timer value based on the first generation step, wherein the first generation step includes If the expression range of one timer value is exceeded, an initialization process is performed to change the first timer value to a predetermined value, and the second generation step reads the first timer value from the first timer, Second A difference between the first timer value read again after reading the first timer value and the second timer value and the first timer value read earlier is a subtraction process performed by the first timer. Alternatively, it is characterized by further comprising a detection step of detecting an abnormality of the third timer value generated in the third generation step when it is determined that the difference is not caused by the addition process.

  According to the configuration of claim 1, when the difference between the previously read first timer value and the read first timer value is not due to counting in the expression range of the first timer value, the first timer value It is possible to detect an abnormality caused by generating the third timer value based on the first timer value before exceeding the expression range and the second timer value after exceeding.

  According to the configuration of the second aspect, since the third timer value is generated based on the first timer value and the second timer value read after the first timer value exceeds the expression range, the third timer value is accurately determined. Can be generated.

  According to the configuration of the third aspect, the timing at which the number of oscillations exceeds the expression range of the first timer value, the timing at which the second timer value counts the expression range exceeding, and the generation unit include the first timer value and the second timer. The third timer value can be accurately generated based on the first timer value and the second timer value without synchronizing with the timing of reading the value.

  According to the configuration of the fourth aspect, whether or not the difference is due to counting of the number of oscillations based on whether or not the difference between the first timer value read previously and the first timer value read again exceeds a predetermined value. Therefore, the abnormality of the third timer value can be detected with high accuracy.

  According to the configuration of the fifth aspect, when the difference between the first timer value read earlier and the first timer value read again is not due to counting in the expression range of the first timer value, the first timer value It is possible to detect an abnormality caused by generating the third timer value based on the first timer value before exceeding the expression range and the second timer value after exceeding.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a configuration diagram showing an embodiment of a control system including a control device equipped with a timer value generation device of the present invention.

A control system 1 shown in FIG. 1 is mounted on a vehicle. A vehicle is comprised by motor vehicles, such as a passenger car, a bus, and a truck, for example. In this embodiment, the description will be made assuming that the vehicle is composed of an automobile. However, the present invention is not limited to this, and is not limited to this. Motor vehicles such as motorbikes, light vehicles, trolley buses, tanks and armored vehicles, and railways An embodiment composed of a vehicle can be adopted.
In the present embodiment, the case where the control system 1 is mounted on a vehicle will be described, but the present invention is not limited to this. For example, the control system 1 can adopt a configuration mounted on a spacecraft such as a ship, an aircraft, and an artificial satellite, a space probe, and a space station. Furthermore, the control system 1 can employ a configuration that is used without being mounted on a vehicle or a ship.

  The control system 1 includes ECUs (Electronic Control Units) 100 to 700 that are control devices. The ECUs 100 to 700 are communicably connected to each other via a bus BC such as a CAN (Controller Area Network) bus. In the present embodiment, the ECUs 100 to 700 are described as performing communication using the CAN protocol, but the present invention is not limited to this. For example, the ECUs 100 to 700 can employ a configuration in which communication is performed using a LIN (Local Interconnect Network) protocol.

  ECUs 100 to 700 are control devices that control the behavior of the vehicle. ECUs 100 to 700 are a fuel injection control device (EFI-ECU), an airbag ECU, a meter ECU, a body ECU, an eco-run ECU, a security ECU, and other ECUs. The EFI-ECU 100 controls the behavior of the vehicle by controlling the ignition timing of the ignition device (ignition) of the engine provided in the vehicle. The airbag ECU 200 controls an ignition device (that is, a squib) that ignites and burns a gas generating agent that generates a gas for deploying the airbag.

  Meter ECU 300 controls display of a meter provided in the vehicle. The body ECU 400 controls, for example, a body system device such as a door. The eco-run ECU 500 controls the vehicle to travel with good fuel efficiency (that is, economy) or environmentally friendly (that is, ecology). The security ECU 600 controls equipment mounted on the vehicle in order to ensure the safety of the vehicle and vehicle occupants. As a specific example, the security ECU 600 controls an audio output device such as a speaker so as to issue an alarm when an intrusion to the vehicle is detected.

In addition, the ECU 700 controls devices other than the devices that the ECUs 100 to 600 control. In the present embodiment, the other ECU 700 is described as controlling (that is, power management) the discharging and charging of the storage battery 10 mounted on the vehicle, but is not limited thereto.
In the present embodiment, the timer value generation device of the present invention will be described as being mounted on the ECU 700. However, the present invention is not limited to this, and a configuration mounted on ECUs 100 to 600 can be adopted. Therefore, the configuration of ECUs 100 to 700 is substantially the same, and therefore the configuration of other ECU 700 will be described below.

Here, with reference to FIG. 2, the configuration of the other ECU 700 will be described. FIG. 2 is a hardware configuration diagram illustrating another configuration example of the ECU 700.
The other ECU 700 shown in FIG. 2 is connected to various sensors, ignition switches, various actuators, the storage battery 10 and the CAN bus BC mounted on the vehicle.

Here, before describing the other ECU 700, the storage battery 10 and the like connected to the other ECU 700 will be described.
The storage battery 10 is composed of a general battery such as a lead storage battery, for example. The storage battery 10 supplies power to various devices mounted on the vehicle including the ECU 700. In the present embodiment, the storage battery 10 has been described as being constituted by a general type battery such as a lead storage battery, but is not limited thereto. For example, the storage battery 10 can be configured to be a liquid circulation type battery such as a redox flow battery, a mechanical charge type battery such as an aluminum / air battery, and a high temperature operation type battery such as a sodium / sulfur battery.

  The ignition switch is generally a switch that opens an electric circuit through which a signal for starting an ignition device (that is, an ignition) of an engine passes by rotation of an engine key. The various sensors, for example, output signals representing information used for controlling discharge or charging performed by the storage battery 10 such as the temperature near the storage battery 10, the current flowing out from the storage battery 10, and the engine speed to the ECU 700. The various actuators operate devices related to discharging and charging of the storage battery 10 according to other signals output from the ECU 700, for example.

Next, the configuration of the other ECU 700 will be described. In addition, the ECU 700 includes a power supply IC 710 (Integrated Circuit), a signal shaping level conversion unit 720, a transmission circuit 730, an output circuit 740, and a microcomputer 750.
The power supply IC 710 is connected to the storage battery 10, the microcomputer 750, and the ignition switch. The power supply IC 710 has a power generation function and a monitoring function. The power supply generation function is a function of generating a power supply that supplies power used by the microcomputer 750 using power supplied from the storage battery 10 based on a signal acquired from the ignition switch. The monitoring function is a function for outputting a reset signal for instructing the microcomputer 750 to restart based on a watch dog clock WDC (Watch Dog Clock) output from the microcomputer 750.

  The signal shaping level conversion unit 720 is connected to various sensors and the microcomputer 750. The signal shaping level conversion unit 720 forms signals output from various sensors and converts the formed signals to a level suitable for the processing of the microcomputer 750. Thereafter, the signal shaping level conversion unit 720 outputs the converted signal to the microcomputer 750. Specifically, the signal shaping level conversion unit 720 performs input of a digital signal obtained by performing A / D (Analog / Digital) conversion on a signal output from various sensors, pulse input, or port input.

  The oscillation circuit 730 is configured by, for example, a feedback oscillation circuit or a relaxation oscillation circuit. The feedback oscillation circuit can employ a configuration such as a solid oscillator oscillation circuit, a CR oscillation circuit, or an LC anti-coupling oscillation circuit. Furthermore, the solid oscillator oscillation circuit may employ a configuration that is a circuit using, for example, a crystal oscillator or a ceramic oscillator. The oscillation circuit 730 outputs an electrical signal having a predetermined frequency that determines the shortest time that can be measured by the timer of the present invention to the microcomputer 750.

The output circuit 740 is configured by a hardware circuit. The output circuit 740 is connected to the microcomputer 750, the CAN bus BC, and various actuators. The output circuit 740 outputs data to be output to various actuators by outputting a port output, serial output, PWM (Pulse Width Modulation) output signal to the various actuators when the microcomputer 750 executes control processing for controlling the discharging or charging of the storage battery 10. Is transmitted from the other ECUs 100 to 600 via the CAN bus BC.
The microcomputer 750 is connected to the power supply IC 710, the signal shaping level conversion unit 720, the oscillation circuit 730, and the output circuit. The microcomputer 750 is a timer value generation device of the present invention.

Here, the configuration of the microcomputer 750 will be described with reference to FIG. FIG. 3 is a hardware configuration diagram illustrating a configuration example of the microcomputer 750.
A microcomputer 750 shown in FIG. 3 is a 16-bit microcomputer. The microcomputer 750 includes a frequency divider 751, a first timer 752a, a second timer 752b, and a software processing unit 753.
The frequency divider 751 is connected to the oscillation circuit 730 and the first timer 752a. The frequency divider 751 converts the electrical signal having a predetermined frequency acquired from the oscillation circuit 730 into a signal having a lower frequency. Thereafter, the frequency divider 751 outputs the converted frequency signal to the first timer 752a.

  The first timer 752a includes a 16-bit free-run timer register and a peripheral circuit that changes the value of the timer register. The first timer 752a is connected to the frequency divider 751, the second timer 752b, and the software processing unit 753. The first timer 752a provides the software processing unit 753 with data used for the lower bits of 32-bit data representing the time notified by the software processing unit 753 described later. The time notified by the software processing unit 753 is hereinafter simply referred to as timer time. The 32-bit data representing the timer time is hereinafter simply referred to as 32-bit time data. Further, the data used for the lower bits of the 32-bit time data is hereinafter simply referred to as lower 16-bit time data.

Specifically, the first timer 752a decreases the value of the timer register from the value “0xFFFF” to “0x0000” in increments of the value “0x0001” in the cycle “LSB: 125 ns” when the frequency divider 751 outputs the electric signal. Let Here, when an underflow occurs (that is, in the “LSB: 192 ms” cycle), the first timer 752a outputs a signal reporting the occurrence of a carry to the second timer 752b.
In the present embodiment, the first timer 752a is described as counting the number of oscillations of the signal output from the frequency divider 751 by subtraction processing and storing the counted value in the timer register. However, the present invention is not limited to this. Instead, it is possible to employ a configuration in which the number of oscillations is counted by addition processing.

  The second timer 752b has a configuration similar to that of the first timer 752a. The second timer 752b is connected to the first timer 752a and the software processing unit 753. The second timer 752b provides data used for the upper bits (hereinafter simply referred to as upper 16-bit time data) to the software processing unit 753. Specifically, when the second timer 752b receives a signal reporting the occurrence of a carry event from the first timer 752a, the second timer 752b changes the value of the timer register from the value “0xFFFF” to “0x0000”. Decrease in increments.

In this embodiment, the second timer 752b indicates the number of times that the number of oscillations of the signal output from the frequency divider 751 exceeds the expression range of the timer register of the first timer first timer 752a (that is, the number of underflows). Although description will be made assuming that counting is performed by the subtraction process and the counted value is stored in the timer register, the present invention is not limited to this, and a configuration in which the excess number is counted by the addition process can be employed.
The lower 16-bit time data value is referred to as a first timer value, the upper 16-bit time data value is referred to as a second timer value, and the 32-bit time data value is referred to as a third timer value.
In this embodiment, the first timer value and the second timer value are 16-bit data values, and the third timer value is a 32-bit data value. However, the present invention is not limited to this. The three timer value may be a data value composed of the number of bits that can count the number of oscillations in a wider range than the first timer value expression range based on the first timer value and the second timer value.

The software processing unit 753 is connected to the first timer 752a, the second timer 752b, the power supply IC 710, the signal shaping level conversion unit 720, and the output circuit 740. The software processing unit 753 performs software processing described later using data acquired from the first timer 752a and the like.
Here, an example of a hardware configuration used for the software processing unit 753 to execute software processing will be described. The software processing unit 753 includes an execution unit 753a, a RAM 752b (Random Access Memory), a ROM 753c (Read-Only Memory), an input microcomputer peripheral resource 753d, and an output microcomputer peripheral resource 753e. The microcomputer peripheral resource for output 753e from the execution unit 753a constituting the software processing unit 753 is connected so as to be able to exchange data via a bus.

  The software processing unit 753 is executed by the execution unit 753a. The execution unit 753a is configured by, for example, a CPU (Central Processing Unit). The execution unit 753a first reads a program stored in the RAM 752b or the ROM 753c. Next, the execution unit 753a performs operations on various sensor values input by an input microcomputer peripheral resource 753d described later in accordance with a software process execution procedure represented by the read program. Thereafter, the execution unit 753a writes the calculation result in the RAM 752b and outputs it to the output microcomputer peripheral resource 753e as necessary. The execution unit 753a restarts upon receiving a reset signal input by the input microcomputer peripheral resource 753d.

  The RAM 752b (Random Access Memory) includes a volatile memory such as a DRAM (Dynamic Random Access Memory) or SRAM (Static RAM) and a non-volatile memory such as an NVRAM (Non Volatile RAM). The ROM 753c (Read-Only Memory) includes a read-only memory such as an EPROM (Erasable Programmable Read-Only Memory) or an EEPROM (Electrically Erasable Programmable Read-Only Memory). The input microcomputer peripheral resource 753d and the output microcomputer peripheral resource 753e are composed of registers and peripheral circuits that manage register values. The input microcomputer peripheral resource 753d inputs various sensor values input by the signal shaping level conversion unit 720 and a reset signal output by the power supply IC 710 to the execution unit 753a. Further, the output microcomputer peripheral resource 753e outputs a signal output from the execution unit 753a to the output circuit 740 or the power supply IC 710.

Next, the configuration of the software processing unit 753 will be described based on functions with reference to FIG. FIG. 4 is a functional block diagram illustrating a configuration example of the software processing unit 753.
The software processing unit 753 shown in FIG. 4 includes an alarm time unit 753f, a watchdog operation unit 753g, a control unit 753h, an output unit 753i, and an input unit 753j. The reporting time unit 753f is connected to the first timer 752a, the second timer 752b, the watch dog operation unit 753g, and the control unit 753h. The reporting time unit 753f notifies the timer time represented by the third timer value, which is 32-bit time data, by executing the reporting process.

  Here, before explaining the reporting process executed by the reporting unit 753f constituting the timer value generating apparatus of the present invention, the reporting process executed by the known reporting unit 953f will be described with reference to FIG. To do. FIG. 5A is a flowchart showing an example of a time information process executed by a known time information unit 953f. The well-known time information unit 953f notifies the time based on data provided by a 32-bit timer 952 mounted on a 32-bit microcomputer that is a well-known timer value generation device.

  First, the reporting unit 953f reads the timer value of the 32-bit free-run timer register managed by the 32-bit timer 952 (step S01). Next, the reporting unit 953f bit-inverts the read timer value to acquire the timer time (step S02). That is, the register value starts from “0xFFFF FFFF”. Thereafter, the reporting unit 953f notifies (discloses) the timer time to the units corresponding to the control unit 753h and the watchdog operation unit 753g shown in FIG. 4 (step S03). Thereafter, the reporting unit 953f ends the execution of the reporting process.

  Next, a description will be given of a reporting process executed by the conventional reporting unit 853f in comparison with a reporting process executed by the known reporting unit 953f. FIG. 5B is a flowchart showing an example of the time information processing executed by the conventional time information unit 853f. Note that the microcomputer provided with the conventional report time unit 853f is a 16-bit microcomputer, similar to the microcomputer 750 of the present invention. Therefore, the time information processing performed by the conventional time information unit 853f is different from the time information processing performed by the known time information unit 953f in the following steps S11 to S13.

  First, the reporting unit 853f reads the first timer value (that is, the lower 16-bit time data) of the 16-bit free-run timer register managed by the first timer 852a, which is a 16-bit timer (step S11). . Next, the reporting unit 853f reads the second timer value (that is, the upper 16-bit time data) of the 16-bit free-run timer register managed by the second timer 852b, which is a 16-bit timer (step S12). Note that the configurations of the first timer 852a and the second timer 852b are the same as the configurations of the first timer 952a and the second timer 952b, and thus the description thereof is omitted.

  Thereafter, the reporting unit 953f combines the 32-bit time data with the upper 16 bits of the 32-bit time data as the upper 16-bit time data and the lower 16 bits as the lower 16-bit time data (step S13). That is, the reporting unit 953f generates the third timer value based on the first timer value and the second timer value. Thereafter, the reporting unit 853f executes the processing of step S14 and step S15 on the combined 32-bit data (step S14 and step S15). Thereafter, the report time unit 853f ends the execution of the report time process. Note that the processing in step S14 and step S15 is the same as the processing in step S02 and step S03, and therefore description thereof is omitted.

Next, with reference to FIG. 6, the problem of the conventional time information processing caused by the difference from the known time information processing will be outlined. FIG. 6 is a diagram illustrating an example of a problem of the time information processing performed by the conventional time information unit 853f.
FIG. 6A is a diagram illustrating a transition of the first timer value of the free-run timer register managed by the first timer 852a. In FIG. 6A, the horizontal axis represents time, and the vertical axis represents lower 16-bit data values represented by the free-run timer register. As shown in FIG. 6A, before time t01, the value of the lower 16-bit data takes the maximum value “0xFFFFFF” that can be expressed by 16 bits. Next, when the frequency divider 751 outputs a signal at time t01, the value of the lower 16-bit data is changed to a value lower by “0x0001” by the first timer 852a that has received the signal. Thereafter, the lower 16-bit data value is subtracted every time the frequency divider 751 outputs a signal until it becomes “0x0001”. Next, when the frequency divider 751 outputs a signal at time t10, since the lower 16-bit data of the value “0x0001” exceeds the value expression range, the first timer 852a performs initialization processing, and the maximum The value is initialized to “0xFFFFFF”. At time t10, the first timer 852a that has received the signal from the frequency divider 751 generates an underflow and also sends a signal reporting the occurrence of a carry (that is, exceeding the expression range) to the second timer 852b. Output.

  FIG. 6B is a diagram illustrating the transition of the second timer value of the free-run timer register managed by the second timer 852b. In FIG. 6B, the horizontal axis represents time, and the vertical axis represents the value of upper 16-bit data represented by the free-run timer register. As shown in FIG. 6B, the value of the upper 16-bit data takes the maximum value “0xFFFFFF” that can be expressed by 16 bits before time t10. Next, when the first timer 852a outputs a signal reporting the occurrence of a carry at time t10, the value of the upper 16-bit data is changed to a value lower by “0x0001” by the second timer 852b that has received the signal. The Thereafter, the value of the upper 16-bit data is similarly subtracted until it becomes “0x0001”.

  FIG. 6C is a diagram illustrating a transition of the timer time (that is, the third timer value after inversion) notified by the timekeeping unit 753f configuring the software processing unit 853. In FIG. 6C, the horizontal axis represents time, and the vertical axis represents timer time. As shown in FIG. 6C, the 32-bit time data indicating the timer time is data obtained by combining the lower 16-bit data and the upper 16-bit data at each time. Therefore, when the frequency divider 751 outputs a signal to the first timer 852a, in principle, the value of the 32-bit time data after output must be increased by the value “0x0000 0001” from the value before the signal is output.

  However, since the reporting unit 853f sequentially processes step S11 and step S12 referred to in FIG. 5, the first timer 852b is read after reading the first timer 852a in step S11. An overflow of 852a and an update of the second timer 852b may occur. At this specific timing, the value of the first timer 852a before overflow and the value of the second timer 852b after overflow are combined. Therefore, since the reporting time unit 853f generates an abnormal timer time at this specific timing, there is a problem that the time cannot be provided with high accuracy.

  Specifically, when the reporting unit 853f reads the first timer 852a immediately before the time t10 and reads the second timer 852b immediately after the time t10, the first timer 852a before the overflow has occurred. The timer value “0x0001” and the second timer value “0xFFFE” of the second timer 852b after overflowing are combined. Therefore, there is a problem that the reporting unit 853f generates an abnormal value “0x0001 FFFE” instead of the normal third timer value “0x0000 FFFE”.

Next, with reference to FIG. 7, in order to solve the problem of the prior art, the time information processing executed by the time information unit 753f constituting the microcomputer 750 which is the timer value generation device of the present invention will be outlined. FIG. 7 is a diagram for illustrating an example of the time information processing executed by the time information unit 753f. 7A to 7C are substantially the same as FIGS. 6A to 6C, and detailed description thereof will be omitted.
First, the reporting unit 753f reads the first timer value from the first timer 952a. Next, the reporting unit 753f reads the second timer value from the second timer 952b. Thereafter, the reporting unit 753f reads the first timer value again.

  Here, since the first timer 952a subtracts the first timer value and counts the number of oscillations, the first timer value read for the first time is the first timer value read for the second time unless a carry occurs. Greater than the value. Therefore, by determining whether or not the first timer value read for the first time is smaller than the first timer value read for the second time, the timekeeping unit 753f reads the first timer 952a and then reads the second timer value. It can be determined whether or not a carry has occurred before reading 952b.

  According to this configuration, when the difference between the first timer value read out earlier and the first timer value read out again is not due to counting in the expression range of the first timer value, the first timer value is expressed in the expression range. An abnormality caused by generating the third timer value based on the first timer value before exceeding and the second timer value after exceeding can be detected.

  In addition, since the first timer 952a subtracts the first timer value based on the oscillation of the signal generated by a predetermined peripheral, the first timer value read first time and the second time read unless a carry occurs. The difference from the first timer value is a value lower than the predetermined value. Therefore, even if it is determined whether or not the calculated difference exceeds a predetermined value, the reporting unit 753f determines whether or not a carry has occurred before reading the second timer 952b after reading the first timer 952a. Can be judged.

  According to this configuration, it is determined whether or not the difference is due to counting of the number of oscillations based on whether or not the difference between the previously read first timer value and the again read first timer value exceeds a predetermined value. Therefore, the abnormality of the third timer value can be detected with high accuracy.

Next, the configuration of the reporting unit 753f will be described with reference to FIG. 8 before describing the reporting process executed by the reporting unit 753f. FIG. 8 is a functional block diagram illustrating a configuration example of the reporting unit 753f.
The reporting unit 753f includes a reading unit 753k, a detection unit 7531, a generation unit 753m, a reversing unit 753n, and a disclosure unit 753o. The reading unit 753k is connected to the first timer 752a, the second timer 752b, and the detection unit 7531. The reading unit 753k is realized by the execution unit 753a executing the reading process. The reading unit 753k reads the first timer value and the second timer value from the first timer 752a and the second timer 752b, and outputs the read values to the detection unit 7531.

  The detection unit 7531 is connected to the reading unit 753k and the generation unit 753m. The detection unit 753l is realized by the execution unit 753a executing the detection process. First, the detecting unit 7531 calculates the difference between the first timer value read again after reading the first timer value and the second timer value read by the reading unit 753k, and the first timer value read first. Next, the detection unit 7531 determines whether or not the calculated difference is a difference caused by the subtraction process or addition process performed by the first timer 752a and determines that the difference is not a difference caused by the subtraction process or addition process. In this case, the abnormality of the third timer value generated by the generation unit 753m described later is detected. If no abnormality is detected, the detection unit 7531 outputs the first timer value and the second timer value acquired from the reading unit 753k to the generation unit 753m. In addition, when detecting an abnormality, the detection unit 7531 controls the reading unit 753k to read the first timer value and the second timer value again, and then transmits the value acquired from the reading unit 753k to the generation unit 753m. Output. As shown in FIG. 7, the detection unit 7531l determines whether the first timer value read at the first time is smaller than the first timer value read at the second time, or the first timer read at the first time. An abnormality is detected based on whether or not the difference between the value and the first timer value read for the second time is lower than a predetermined value.

The generation unit 753m is connected to the detection unit 753l and the inversion unit 753n. The generation unit 753m is realized by the execution unit 753a executing the generation process. The detection unit 7531 generates a third timer value based on the first timer value and the second timer value acquired from the detection unit 7531, and outputs the generated value to the inversion unit 753n.
The inversion unit 753n is connected to the generation unit 753m and the disclosure unit 753o. The inversion unit 753n is realized by the execution unit 753a executing the inversion process. The inversion unit 753n inverts the third timer value acquired from the generation unit 753m to generate a timer time. The inversion unit 753n outputs the generated timer time to the disclosure unit 753o.
The disclosure unit 753o is connected to the inversion unit 753n, the watchdog operation unit 753g, and the control unit 753h. The disclosure unit 753o is realized by the execution unit 753a executing the disclosure process. The disclosure unit 753o discloses (notifies) the timer time acquired from the reversing unit 753n to the watch dog operation unit 753g and the control unit 753h.

  Next, with reference to FIG. 9, the reporting process executed by the reporting unit 753f will be described. FIG. 9 is a flowchart showing an example of a time information process executed by the time information unit 753f. The reporting unit 753f executes the reporting process when the watchdog operation unit 753g and the control unit 753h request notification of time.

  First, the reporting unit 753f executes an interrupt prohibition process that prohibits interrupt execution of other software processes (step S21). This is because the processing of steps S22 to S28 described later is continuously performed without delay. Next, the reporting unit 753f substitutes the first timer value read from the first timer 752a for the variable 11 (step S22). Thereafter, the reporting unit 753f substitutes the second timer value read from the second timer 752b for the variable 2 (step S23). Next, the reporting unit 753f substitutes the first timer value read again from the first timer 752a for the variable 12 (step S24).

  Thereafter, the reporting unit 753f determines whether or not the value of the variable 11 is smaller than the value of the variable 12 (step S25). The reporting unit 753f may determine whether or not the difference between the value of the variable 11 and the value of the variable 12 exceeds a predetermined value. That is, the reporting unit 753f determines whether or not an underflow has occurred in the first timer 752a. The reporting unit 753f executes the process of step S26 when determining that an underflow has occurred, and executes the process of step S29 otherwise.

  In step S25, when it is determined that the underflow has occurred, the reporting unit 753f detects that the third timer value generated from the first timer value and the second timer value that have already been acquired becomes abnormal. (Step S26). Next, the reporting unit 753f substitutes the second timer value after underflow read again from the second timer 752b for the variable 2 (step S27). Next, the reporting unit 753f substitutes again the first timer value after the underflow for the variable 12 (step S28).

  According to this configuration, since the third timer value is generated based on the first timer value and the second timer value read after the first timer value exceeds the expression range, the third timer value can be generated with high accuracy.

  In step S25, when the reporting unit 753f determines that no underflow has occurred, or after executing step S28, it executes a prohibition canceling process for canceling prohibition of interrupt execution (step S29). Thereafter, the reporting unit 753f combines the 16-bit lower data representing the first timer value stored in the variable 12 and the 16-bit higher data representing the second timer value stored in the variable 2 to obtain the third timer value. Is generated (step S30). Next, the reporting unit 753f executes the processing of Step S31 and Step S32 (Step S31 and Step S32). Thereafter, the reporting unit 753f ends the execution of the reporting process. Note that the processing in step S31 and step S32 is the same as the processing in step S14 and step S15 in FIG.

  According to this configuration, the timing at which the number of oscillations exceeds the expression range of the first timer value, the timing at which the second timer value counts the expression range exceeding, and the generation unit 753m determine the first timer value and the second timer value. The third timer value can be accurately generated based on the first timer value and the second timer value without synchronizing with the read timing.

  Note that the processes in steps S22, S23, S24, S27, and S28 correspond to a read process that realizes the read unit 753k, the processes in steps S25 and S26 correspond to a detection process that realizes the detection unit 7531, and the process in step S30. The process corresponds to a generation process that realizes the generation unit 753m, the process in step S31 corresponds to an inversion process that realizes the inversion part 753n, and the process in step S32 corresponds to a disclosure process that realizes the disclosure unit 753o.

Here, returning to FIG. 4, the configuration of the software processing unit 753 will be described.
The watchdog operation unit 753g is connected to the reporting unit 753f and the output unit 753i. The watchdog operation unit 753g executes an operation process, and performs a watchdog operation (that is, output of the watchdog clock WDC) to the power supply IC 710 via the output unit 753i based on the time notified by the reporting unit 753f. Do.
The control unit 753h is connected to the reporting unit 753f, the output unit 753i, and the input unit 753j. The control unit 753h executes the control process, thereby obtaining data or signals for controlling the storage or discharge of the storage battery 10 based on the time notified by the reporting unit 753f and the values of various sensors input by the input unit 753j. Output to the output unit 753i.

The output unit 753i includes, for example, an output microcomputer peripheral resource 753e. The output unit 753 i is connected to the power supply IC 710 and the output circuit 740. The output unit 753i outputs the pulse signal WDC output from the watchdog operation unit 753g to the power supply IC 710. Further, the output unit 753i outputs a signal or data output from the control unit 753h to the output circuit 740 through port output, serial output, or PWM output.
The input unit 753j is composed of, for example, an input microcomputer peripheral resource 753d. The input unit 753j is connected to the control unit 753h and the signal shaping level conversion unit 720. The input unit 753j inputs the values of various sensors to which the signal shaping level conversion unit 720 inputs pulses and the like to the control unit 753h.

In this embodiment, the microcomputer 750 corresponds to a timer value generating device. The timer value generation method according to the present invention can be implemented using the microcomputer 750.
Furthermore, in the present embodiment, the step in which the first timer 752a performs the process of subtracting or adding the first timer value corresponds to the first generation step, and the process of subtracting or adding the second timer value in the second timer 752b. The step to be executed corresponds to the second generation step, and the step in which the execution unit 753a executes the generation process corresponds to the third generation step.

  A program representing processing executed by the software processing unit 753 included in the microcomputer 750 can be provided by being stored and distributed in a magnetic disk, optical disk, semiconductor memory, or other recording medium, or distributed via a network.

  Moreover, a part or all of the functions realized by the microcomputer 750 executing software processing can be realized using a hardware circuit. Conversely, part or all of the functions realized by the microcomputer 750 using the hardware circuit can be realized by executing software processing.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed.

It is a block diagram which shows one Embodiment of the control system comprised with the control apparatus incorporating the timer value generation apparatus of this invention. It is a hardware block diagram showing the other structural example of ECU. It is a hardware block diagram showing the example of 1 structure of a microcomputer. It is a functional block diagram showing the example of 1 composition of a software processing part. It is a flowchart showing an example of the time information processing which the conventional time information part performs. It is a figure showing an example of the problem of the time information processing which the conventional time information part performs. It is a figure for giving an outline about an example of the time information processing which an information time part performs. It is a functional block diagram showing an example of 1 composition of an information time part. It is a flowchart showing an example of the time information process which a time information part performs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control system 10 ... Storage battery
100-700 ... ECU 710 ... Power supply IC
720 ... Signal shaping level conversion unit 730 ... Oscillation circuit
740 ... Output circuit 750 ... Microcomputer (timer value generator)
751 ... Frequency divider 752a ... First timer ...
752b ... second timer 753 ... software processing section
753a ... execution unit 753b ... RAM
753c ... ROM 753d ... Peripheral resource for input
753e ... Peripheral resource for output 753f ... Reporting time
753g ... watchdog operation part 753h ... control part
753i ... Output unit 753j ... Input unit
753k ... Reading unit 753l ... Detecting unit
753m ... generating unit 753n ... reversing unit
753o ... notification unit 852a ... 16 bit timer 852b ... 16 bit timer 853 ... software processing unit
853e ... Reporting time part 952 ... 32-bit timer
953 ... Software processing section BC ... CAN bus

Claims (5)

A first timer having a first timer value that counts a signal input at a predetermined period by performing one of subtraction processing or addition processing, and the counted number represents an expression range of the first timer value. Based on the second timer having a second timer value for counting the number of times exceeded, the first timer value read from the first timer, and the second timer value read from the second timer, the first timer value A timer value generation device comprising: a generation unit that generates a third timer value that counts a range wider than the expression range of
The first timer performs an initialization process to change the first timer value to a predetermined value when the counted number exceeds an expression range of the first timer value,
The generation unit reads the second timer value from the second timer after reading the first timer value from the first timer,
The difference between the first timer value read again after reading the first timer value and the second timer value and the first timer value read earlier is the subtraction process or the addition performed by the first timer. A timer value generation device further comprising a detection unit that detects an abnormality of a third timer value generated by the generation unit when it is determined that the difference is not caused by processing.   The said generation part produces | generates a said 3rd timer value based on the 1st timer value read again and the 2nd timer value read again, when the said detection part detects abnormality. 1. The timer value generation device according to 1. The first timer and the second timer are composed of hardware circuits,
The timer value generation device according to claim 1, wherein the generation unit is realized by software processing.   4. The timer value generation device according to claim 1, wherein the detection unit detects an abnormality of a third timer value generated by the generation unit when the difference exceeds a predetermined value. 5. . A first generation step of generating a first timer value for counting a signal input in a predetermined cycle by performing either one of a subtraction process or an addition process; and the counted number is an expression of the first timer value Based on a second generation step of generating a second timer value for counting the number of times the range has been exceeded, a first timer value read from the first timer, and a second timer value read from the second timer, A timer value generation method comprising: a third generation step of generating a third timer value for counting a range wider than the expression range of the first timer value;
The first generation step performs an initialization process to change the first timer value to a predetermined value when the counted number exceeds the expression range of the first timer value,
The second generation step reads the second timer value from the second timer after reading the first timer value from the first timer,
The difference between the first timer value read again after reading the first timer value and the second timer value and the first timer value read earlier is the subtraction process or the addition performed by the first timer. A timer value generation method, further comprising a detection step of detecting an abnormality of the third timer value generated in the third generation step when it is determined that the difference is not caused by the processing.

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