JP2010109214A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can comparatively easily control a work function of a gate electrode formed of metal even if heat treatment is performed after the formation of the gate electrode. <P>SOLUTION: Impurities are injected into a metal film 3 for gate electrodes formed in a pFET region Rp after forming a gate insulating film 2 and the metal film 3 for gate electrodes one by one on a semiconductor substrate 1 of an nFET region Rn and pFET region Rp. By this, since the composition of the metal film 3 for gate electrodes formed in the pFET region Rp can be changed, the work function of the gate electrode of the pFET region Rp formed by the metal film 3 for gate electrodes can be changed. Therefore, the gate electrodes having different work functions can be formed easily in the nFET region Rn and the pFET region Rp. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a complementary metal insulator semiconductor (abbreviation: CMIS) transistor.

  The CMIS transistor uses, for example, a high dielectric insulating film (hereinafter referred to as a “high-k film”) having a higher dielectric constant than the conventionally used silicon oxide film and silicon nitride film as the gate insulating film. The gate electrode has a high-k / metal gate structure using a metal electrode.

  In a CMIS transistor having a high-k / metal gate structure, gate electrodes having different work functions are used for an n-channel nMIS transistor and a p-channel pMIS transistor. In order to control the work function of the gate electrode, a dual metal gate structure using the work function of the metal itself (for example, see Non-Patent Document 1) or a capping technique (for example, see Non-Patent Document 2) is used. Yes.

  In the CMIS transistor having a dual metal gate structure, the work function of the gate electrode is adjusted by changing the material of the gate electrode itself between the nMIS transistor and the pMIS transistor and forming the gate electrode with different metals. In capping technology, for example, a metal film to be a gate electrode is formed on a capping layer containing lanthanum (La) or aluminum (Al), and La or Al is diffused in the metal film to adjust the work function of the gate electrode. To do.

  In the manufacturing flow of the CMIS transistor having the dual metal gate structure, after forming the gate insulating film, first, the n-type metal for the nMIS transistor is formed over both the n region where the nMIS transistor is formed and the p region where the pMIS transistor is formed. Alternatively, a p-type metal for a pMIS transistor is formed. Of the deposited n-type metal or p-type metal, the metal in the p region or the n region is removed, and a metal having a conductivity type different from the metal previously deposited thereon, specifically, the p-type metal or n A mold metal is formed to form gate electrodes in the n region and the p region, respectively.

  Since the removal and deposition of the metal film are repeated in this way, the manufacturing flow is complicated by the method of separating the metals themselves as in the dual metal gate structure, and it is difficult to manufacture the CMIS transistor. Since the work function of the gate electrode depends on the metal film and the high-k film constituting the gate electrode, the minimum threshold Vth of the nMIS transistor and the pMIS transistor is uniquely determined by the material of the metal film and the high-k film. It will be decided. Further, even when gate electrodes having different work functions are produced with nMIS transistors and pMIS transistors, the work functions may not be sufficiently close to the band edge, and it is difficult to obtain a desired threshold value Vth.

  When using the capping technique, photoengraving is not possible directly on the capping layer. Therefore, after the capping layer and the metal film are formed, the c-layer and the metal film in the p region or the n region are removed at the same time. It is necessary to form a new capping layer and a metal film.

  Thus, since the manufacturing flow is complicated, it is difficult to manufacture a CMIS transistor. Further, the threshold value Vth of the transistor is determined by the type and thickness of the capping layer. However, as described above, it is necessary to form the metal film again in the manufacturing flow, so that the lowest threshold value of the nMIS transistor and the pMIS transistor is eventually obtained. Vth is uniquely determined.

  As described above, the conventional technique has a problem that the manufacturing flow becomes complicated because of a difference in work function. In the conventional technique, even if a gate electrode having different work functions is produced for the nMIS transistor and the pMIS transistor, the work function is not sufficiently close to the band edge, and the work function of the gate electrode is located at a place other than the band edge. In many cases, there is a problem that the threshold Vth is uniquely determined to be a relatively high value.

  Prior arts for adjusting the work function of the gate electrode are disclosed in Patent Documents 1 to 3. In Patent Document 1, in order to optimize the threshold value of a PMOS transistor and an NMOS transistor using titanium nitride (TiN) as a gate electrode, nitrogen is ion-implanted into the TiN electrode layer and the work function is changed to optimize the threshold value. Is disclosed.

  Patent Document 2 discloses, as a conventional technique, that nitrogen is implanted into a metal gate electrode such as TiN, and that indium (In) is implanted into the metal gate electrode. In addition, Patent Document 2 discloses antimony (Sb), boron (B), phosphorus (P), carbon (C), and the like as other elements implanted into the metal gate electrode.

  Patent Document 3 discloses that a work function of a metal gate electrode is adjusted by ion-implanting a metal such as In or nitrogen into a metal gate electrode made of TiN or the like of a PMOS transistor.

JP 2001-203276 A JP 2002-299610 A JP 2002-118175 A T. Hayashi et.al, IEDM Tech. Dig., (2006) p.247. V. Narayanan et.al, VLSI Tech. Symp., (2006) p.224.

  The prior art disclosed in Patent Document 1 relates to a transistor using a silicon nitride film as a gate insulating film. Patent Document 1 does not disclose a CMIS transistor having a high-k / metal gate structure using a high-k film as a gate insulating film. In the CMIS transistor having a high-k / metal gate structure, A method for controlling the work function is not disclosed.

  The prior art disclosed in Patent Documents 2 and 3 relates to a transistor in which a gate electrode is formed by a damascene gate process. The damascene gate process is a method in which a dummy gate is made, and after removing the dummy gate, a gate electrode is formed by embedding a metal material to be a gate electrode. The gate electrode is formed by activating an impurity added to a semiconductor. This is a kind of gate-last process formed after heat treatment for conversion.

  In the gate last process, there is no heat treatment step after embedding a metal material to be a gate electrode, so that the work function of the gate electrode can be controlled relatively easily depending on the type of the metal material to be embedded.

  On the other hand, in the gate first process in which the gate electrode is formed before the heat treatment, the heat function is performed after the gate electrode is formed. Therefore, the work function of the gate electrode is easily changed by this heat treatment, and the work function of the gate electrode is controlled. It is difficult.

  Patent Documents 2 and 3 do not disclose a method for controlling the work function of the gate electrode in the gate-first process.

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which the work function of a metal gate electrode can be controlled relatively easily even when heat treatment is performed after the gate electrode is formed.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a first conductivity type semiconductor element and a second conductivity type semiconductor element having different conductivity types are provided side by side, wherein the first conductivity type semiconductor element is provided. A gate insulating film made of a hafnium-based material containing hafnium (Hf) is formed on a semiconductor substrate having a first conductive type element region where the second conductive type semiconductor element is formed and a second conductive type element region where the second conductive type semiconductor element is formed. Forming a metal film for a gate electrode made of a metal material on the gate insulating film formed in the first conductive type element region and the second conductive type element region; and forming the second conductive type And a step of injecting impurities into the metal film for the gate electrode formed in the mold element region.

  According to the method for manufacturing a semiconductor device of the present invention, a gate insulating film made of a hafnium-based material containing hafnium (Hf) is formed on a semiconductor substrate having a first conductivity type element region and a second conductivity type element region. A gate electrode metal film is formed on the gate insulating film. Of the formed metal film for gate electrode, impurities are implanted into the metal film for gate electrode in the second conductivity type element region. Thereby, the composition of the metal film for the gate electrode formed in the second conductivity type element region can be changed, so that the work function of the gate electrode in the second conductivity type element region formed by the metal film for gate electrode is changed. Can be changed. Therefore, gate electrodes having different work functions can be easily formed in the first conductivity type element region and the second conductivity type element region. Further, the threshold value of the second conductive type semiconductor element can be easily adjusted by changing the composition of the metal film for the gate electrode formed in the second conductive type element region. The type semiconductor element and the second conductivity type semiconductor element can be easily formed.

  Hereinafter, a plurality of modes for carrying out the present invention will be described. In each embodiment, portions corresponding to the matters described in the preceding embodiment are denoted by the same reference numerals, and redundant description may be omitted. When only a part of the configuration is described, the other parts of the configuration are the same as those in the embodiment described above.

<First Embodiment>
1 to 4 are cross-sectional views showing the states of the respective manufacturing steps in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. The semiconductor device of this embodiment is a semiconductor device having a complementary metal insulator semiconductor (Complementary Metal Insulator Semiconductor; abbreviation: CMIS) structure, specifically a CMIS transistor. More specifically, the CMIS transistor is a CMIS field effect transistor (abbreviation: FET). In the CMISFET, an n-type MIS transistor that is an n-channel MIS transistor and a p-type MIS transistor that is a p-channel MIS transistor are arranged in parallel. The n-type MIS transistor is more specifically an nMISFET (hereinafter sometimes referred to as “nFET”), and the p-type MIS transistor is more specifically a pMISFET (hereinafter sometimes referred to as “pFET”). Thus, the nMISFET and the pMISFET having different conductivity types are arranged in parallel in the CMISFET. The nMISFET corresponds to a first conductivity type semiconductor element, and the pMISFET corresponds to a second conductivity type semiconductor element.

  FIG. 1 is a cross-sectional view showing a state where the formation of the gate electrode metal film 3 has been completed. First, in accordance with a conventional CMIS manufacturing flow, a p-well, an n-well and an element isolation film (not shown) extending from the surface of the semiconductor substrate 1 toward the inside of the semiconductor substrate 1 are sequentially formed. The semiconductor substrate 1 is realized by a silicon (Si) substrate. The element isolation film includes an nMISFET region (hereinafter sometimes referred to as an “nFET region”) Rn in which an nMISFET that is a first conductivity type device region is formed, and a pMISFET region (hereinafter referred to as a “pFET region”) that is a second conductivity type device region. It is an insulating film that separates Rp, and is interposed between a p-well formed in the nFET region Rn and an n-well formed in the pFET region Rp. As described above, the semiconductor substrate 1 has the nFET region Rn and the pFET region Rp.

  After the formation of the p-well, the n-well and the element isolation film, as shown in FIG. 1, over the entire surface of the semiconductor substrate 1 in the nFET region Rn and the pFET region Rp, in this embodiment, over the semiconductor substrate 1. A gate insulating film 2 made of an insulating material is formed. The gate insulating film 2 is realized by a high-k film made of a high-k material that is a high dielectric constant material. In the present embodiment, for example, hafnium silicon oxynitride (HfSiON) is formed as the gate insulating film 2. The insulating material constituting the gate insulating film 2 is not limited to HfSiON, but hafnium-based materials containing hafnium (Hf), specifically, hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), and hafnium silicon nitride. Examples thereof include high dielectric constant materials such as (HfSiN), that is, high-k materials.

  Next, as shown in FIG. 1, on the gate insulating film 2 formed in the nFET region Rn and the pFET region Rp, in this embodiment, over the entire surface of the gate insulating film 2 by sputtering or the like. An electrode metal film 3 is formed. The gate electrode metal film 3 is made of a conductive material. If the film thickness t1 of the gate electrode metal film 3 is too thin, it becomes difficult to control the film thickness of the gate electrode metal film 3, and if it is too thick, the diffusion of the ion implantation material described later becomes insufficient. In the embodiment, the value is selected within the range of 15 nm or more and 20 nm or less. In the present embodiment, titanium nitride (TiN) is used as the conductive material constituting the gate electrode metal film 3.

  FIG. 2 is a cross-sectional view showing a state where the formation of the n-side resist mask 4 in the nFET region Rn has been completed. After the formation of the gate electrode metal film 3, a resist is applied over the entire surface of the gate electrode metal film 3, and then photolithography is performed, so that as shown in FIG. Then, the resist in the region where the work function is to be changed, specifically, the pFET region Rp is removed so that the resist does not remain in the region where the work function is desired to be changed. As a result, the remaining region of the gate electrode metal film 3 excluding the region where the work function is desired to be changed, specifically, the entire upper surface of the portion of the upper surface of the gate electrode metal film 3 belonging to the nFET region Rn. The n-side resist mask 4 is formed. The film thickness t2 of the n-side resist mask 4 is an impurity which will be described later in consideration of the film thickness t1 of the gate electrode metal film 3 and the film thickness t3 of the gate electrode metal film 3 after etch back shown in FIG. Is selected so that a portion in which no impurity is implanted remains in the gate electrode metal film 3 in the nFET region Rn.

  After that, in a state where the n-side resist mask 4 is formed, in other words, in a state where the gate electrode metal film 3 in the nFET region Rn is covered with the n-side resist mask 4, from the side where the n-side resist mask 4 is formed. Impurities are implanted over the entire surface, that is, over the nFET region Rn and the pFET region Rp, specifically, ions are implanted. As a result, impurities are implanted into the gate electrode metal film 3 formed in the pFET region Rp. Since the gate electrode metal film 3 in the nFET region Rn is covered with the n-side resist mask 4, impurities are not implanted, or impurities are implanted only into a part on the side in contact with the n-side resist mask 4.

In the present embodiment, the impurity which is an ion implantation type is nitrogen molecules (N ₂ ), silicon (Si), or germanium (Ge). The amount of ion implantation when implanting impurities is, for example, 4 × 10 ¹⁵ / cm ² . One type of impurity may be used alone, or two or more types may be used in combination.

FIG. 3 is a cross-sectional view showing a state in which the removal of part of the gate electrode metal film 3 in the nFET region Rn and the n-side resist mask 4 has been completed. FIG. 4 is a cross-sectional view showing a state in which the removal of the p-side resist mask 5 in the pFET region Rp has been completed. By implanting impurities into the gate electrode metal film 3 in the pFET region Rp by the above-described ion implantation, as shown in FIG. 3, in the pFET region Rp, impurities are introduced into the gate electrode metal film 3, and in this embodiment, N ₂ , Si or Ge is implanted to form an impurity-implanted metal film 6.

  After the formation of the impurity-implanted metal film 6, the n-side resist mask 4 in the nFET region Rn shown in FIG. Thereafter, a resist is applied again over the entire surface of the gate electrode metal film 3 in the nFET region Rn and the impurity-implanted metal film 6 in the pFET region Rp. Then, by performing photoengraving, as shown in FIG. 3, the resist in the nFET region Rn is removed while leaving the resist in the pFET region Rp. Thus, a p-side resist mask 5 is formed on the impurity-implanted metal film 6 in the pFET region Rp.

  Thereafter, as shown in FIG. 3, by etching in a state where the p-side resist mask 5 is formed, in other words, in a state where the impurity-implanted metal film 6 in the pFET region Rp is covered with the p-side resist mask 5, The gate electrode metal film 3 is etched back over the entire nFET region Rn, and a part of the gate electrode metal film 3 is removed in the thickness direction. When a part of the gate electrode metal film 3 is removed by etch back, the film thickness t3 of the gate electrode metal film 3 in the nFET region Rn after the etch back is set to 1 nm or more and 4 nm or less. Thereafter, the p-side resist mask 5 in the pFET region Rp is stripped with a resist stripping solution or the like. As a result, as shown in FIG. 4, in the nFET region Rn, the gate electrode metal film 3 into which no impurity is implanted is formed on the gate insulating film 2, and in the pFET region Rp, on the gate insulating film 2, The impurity-implanted metal film 6 into which impurities have been implanted is formed.

  After the p-side resist mask 5 is stripped, although not shown, a process for forming each gate electrode of the nMISFET and the pMISFET is performed by a dry etching method or the like. Specifically, in the nFET region Rp, the gate electrode metal film 3 to be a gate electrode and the gate insulating film 2 below the gate electrode are etched so that the gate electrode portion and the gate insulating film 2 below the gate electrode remain. In the pFET region Rp, the impurity-implanted metal film 6 to be a gate electrode and the gate insulating film 2 therebelow are etched.

After the etching for forming the gate electrode, a known CMISFET formation process flow is sequentially performed to form an nMISFET and a pMISFET, thereby forming a CMISFET. Specifically, for example, silicon dioxide (SiO _{2) is} formed on both side walls of the gate electrode metal film 3 and the gate insulating film 2 in the nFET region Rn and on both side walls of the impurity-implanted metal film 6 and the gate insulating film 2 in the pFET region Rp. ) Is formed. Thereafter, after implanting impurities into the semiconductor substrate 1 by ion implantation or the like, heat treatment is performed to diffuse the impurities, thereby forming a source region and a drain region to obtain a CMISFET.

  FIG. 5 is a graph showing an effective work function when impurities are ion-implanted into the gate electrode metal film 3. In FIG. 5, the horizontal axis indicates the injection type, and the vertical axis indicates the effective work function (eV). Here, the “effective work function of the gate electrode” is the work function of the gate electrode at the interface with the gate insulating film, and is distinguished from the original “work function” of the material constituting the gate electrode. The effective work function (abbreviation: EWF) of the gate electrode is a flat value obtained from the CV characteristic of the MIS type capacitor shown in FIG. 6 to be described later in the obtained nMISFET and pMISFET, that is, the gate capacitance-gate voltage characteristic. It is obtained from the band voltage.

Impurities that are implantation species of ion implantation in this embodiment are nitrogen molecules (N ₂ ), silicon (Si), and germanium (Ge). The graph of FIG. 5 also shows the case without ion implantation in order to compare the case where impurities are implanted with the case where impurities are not implanted. In the present embodiment, the ion implantation amount when each impurity is ion implanted is 4 × 10 ¹⁵ / cm ² . In the EWF shown in FIG. 5, a TiN film having a film thickness of 15 nm is formed as a gate electrode metal film 3 on the HfSiON film which is the gate insulating film 2, and each of the implanted species is 4 × in the TiN film. This is the value when 10 ¹⁵ / cm ^{2 is} injected.

As shown in FIG. 5, the EWF without ion implantation is 4.84 (eV), and the EWF when the implantation species is nitrogen molecule (N ₂ ) is 4.87 (eV). The EWF when the seed is silicon (Si) is 4.54 (eV), and the EWF when the seed is germanium (Ge) is 4.42 (eV).

From this, it is understood that the work function can be changed by implanting impurities into the metal film 3 for gate electrode. Specifically, it can be seen that by injecting N ₂ into the gate electrode metal film 3, the work function is increased and the threshold Vth is lowered toward the band edge on the p-channel side. It can also be seen that by injecting Si or Ge into the gate electrode metal film 3, the work function decreases and the threshold value Vth increases.

FIG. 6 is a graph showing the relationship between the gate voltage and the gate capacitance when impurities are ion-implanted into the gate electrode metal film 3. In FIG. 6, the horizontal axis indicates the gate voltage (V), and the vertical axis indicates the gate capacitance (F). The graph of FIG. 6 also shows the case without ion implantation in order to compare the case where impurities are implanted and the case where impurities are not implanted. In FIG. 6, the symbol “◯” indicates the case without ion implantation, the symbol “◇” indicates that the implantation species is nitrogen (N ₂ ), and the symbol “Δ” indicates that the implantation species is germanium (Ge). The case where the implantation type is silicon (Si) is indicated by the symbol “□”. The gate capacitance-gate voltage characteristics (CV characteristics) shown in FIG. 6 are obtained by forming a 15 nm-thick TiN film as the gate electrode metal film 3 on the HfSiON film, which is the gate insulating film 2, and forming the TiN film on the TiN film. On the other hand, the present invention relates to a MIS type capacitor when each implantation type is implanted at 4 × 10 ¹⁵ / cm ² , and this MIS type capacitor corresponds to a p-type MIS on an n-type semiconductor substrate.

As shown in FIG. 6, it can be seen that the CV curve is shifted by implanting impurities into the gate electrode metal film 3. This is because the work function is shifted by the impurity implantation as shown in FIG. Specifically, it is understood that when N ₂ is implanted into the gate electrode metal film 3, the CV curve shifts in a direction in which the threshold value Vth decreases. It can also be seen that when Si or Ge is implanted into the gate electrode metal film 3, the CV curve shifts in the direction in which the threshold value Vth increases. By injecting impurities into the gate electrode metal film 3 in this way, the work function can be changed and the threshold value Vth can be changed.

  As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the gate insulating film 2 is formed on the semiconductor substrate 1 in the nFET region Rn and the pFET region Rp, and the gate electrode metal is formed on the gate insulating film 2. A film 3 is formed. Of the formed gate electrode metal film 3, impurities are implanted into the gate electrode metal film 3 formed in the pFET region Rp, and an impurity-implanted metal film 6 is formed. As a result, the composition of the gate electrode metal film 3 formed in the pFET region Rp can be changed. Therefore, the gate electrode of the pFET region Rp formed of the gate electrode metal film 3, that is, the impurity-implanted metal film 6. The work function can be changed. Therefore, gate electrodes having different work functions can be easily formed in the nFET region Rn and the pFET region Rp.

  Further, the threshold value Vth of the pMISFET can be easily adjusted by changing the composition of the gate electrode metal film 3 formed in the pFET region Rp. The threshold value Vth of the nMISFET can be easily adjusted, for example, by adjusting the film thickness of the gate electrode metal film 3 serving as the gate electrode. Therefore, an nMISFET and a pMISFET having a desired threshold value Vth can be easily formed.

  In the present embodiment, since the insulating material constituting the gate insulating film 2 is a hafnium-based material containing hafnium (Hf), the aforementioned impurities are implanted into the gate electrode metal film 3 on the gate insulating film 2. Thus, a desired threshold value Vth can be realized.

  In particular, in the present embodiment, after the ion implantation, as shown in FIG. 3, the gate electrode metal film 3 in the nFET region Rn is etched back by etching back the gate electrode metal film 3 formed in the nFET region Rn. The film thickness can be made suitable for the desired threshold value Vth. Therefore, an nMISFET having a desired threshold Vth can be realized.

  According to this embodiment, in the step of implanting impurities, the impurities are implanted by ion implantation. Thus, impurities can be easily implanted into the gate electrode metal film 3, so that the composition of the gate electrode metal film 3 can be easily changed and the work function of the gate electrode can be changed. Therefore, an nMISFET and a pMISFET having a desired threshold value Vth can be formed.

  In the present embodiment, since the metal material constituting the gate electrode metal film 3 is titanium nitride (TiN), the work function can be changed by injecting the aforementioned impurities, and a desired threshold value can be obtained. Vth can be realized.

In this embodiment, the impurity implanted into the gate electrode metal film 3 is nitrogen molecules (N ₂ ), germanium (Ge), or silicon (Si). As shown in FIGS. 5 and 6 described above, by injecting N ₂ into the gate electrode metal film 3 in the pFET region Rp in which the pMISFET is formed, the work function can be increased and the threshold value Vth can be lowered. Further, by injecting Ge or Si into the gate electrode metal film 3 in the pFET region Rp, the work function can be reduced and Vth can be increased. Ge and Si may be used alone or in combination.

  In the semiconductor device manufacturing method shown in FIGS. 1 to 4 described above, a case where a semiconductor device is manufactured by performing ion implantation prior to etch back of the gate electrode metal film 3 formed in the nFET region Rn will be described. However, the present invention is not limited to this method. For example, the semiconductor device may be manufactured by executing the etch back of the gate electrode metal film 3 formed in the nFET region Rn before the ion implantation. That is, the semiconductor device may be manufactured through manufacturing steps shown in FIGS. 7 and 8 below.

  FIG. 7 is a cross-sectional view showing a state where the formation of the p-side resist mask 7 in the pFET region Rp and the removal of a part of the gate electrode metal film 3 in the nFET region Rn are completed. As shown in FIG. 1, after the gate insulating film 2 and the gate electrode metal film 3 are sequentially formed on the semiconductor substrate 1, a resist is applied over the entire surface of the gate electrode metal film 3, and thereafter By performing photolithography, the resist in the nFET region Rn is removed. Thus, the p-side resist mask 7 is formed on the entire upper surface of the gate electrode metal film 3 on the portion belonging to the pFET region Rp.

  Thereafter, as shown in FIG. 7, in a state where the p-side resist mask 7 is formed, in other words, in a state where the gate electrode metal film 3 in the pFET region Rp is covered with the p-side resist mask 7, The gate electrode metal film 3 is etched back over the entire portion to remove a part of the gate electrode metal film 3 in the thickness direction. When a part of the gate electrode metal film 3 is removed by etch back, the film thickness t3 of the gate electrode metal film 3 in the nFET region Rn after the etch back is set to 1 nm or more and 4 nm or less.

  FIG. 8 is a cross-sectional view showing a state where the removal of the p-side resist mask 7 in the pFET region Rp and the formation of the n-side resist mask 8 in the nFET region Rn are completed. After the etch back is completed, the p-side resist mask 7 in the pFET region Rp is stripped with a resist stripping solution or the like, and a resist is applied again over the entire surface of the nFET region Rn and the gate electrode metal film 3 in the pFET region Rp. . Then, by performing photoengraving, as shown in FIG. 8, the resist in the region of the gate electrode metal film 3 where the work function is to be changed, specifically, the pFET region Rp is removed. As a result, the remaining region of the gate electrode metal film 3 excluding the region where the work function is desired to be changed, specifically, the entire upper surface of the portion of the upper surface of the gate electrode metal film 3 belonging to the nFET region Rn. The n-side resist mask 8 is formed. The film thickness t4 of the n-side resist mask 8 is selected to be equal to or greater than the film thickness t1 of the gate electrode metal film 3 in the pFET region Rp. This prevents impurities from being implanted into the gate electrode metal film 3 in the nFET region Rn when the impurity is implanted into the gate electrode metal film 3 in the pFET region Rp.

After that, in a state where the n-side resist mask 8 is formed, in other words, in a state where the metal film 3 for the gate electrode in the nFET region Rn is covered with the n-side resist mask 8, from the side where the n-side resist mask 8 is formed. Impurity ions N ₂ , Si, or Ge are ion-implanted over the entire surface, that is, over the nFET region Rn and the pFET region Rp, for example, with an ion implantation amount of 4 × 10 ¹⁵ / cm ² . Thus, impurities are implanted only into the gate electrode metal film 3 in the pFET region Rp in the gate electrode metal film 3. By injecting impurities into the gate electrode metal film 3 in the pFET region Rp by ion implantation, as shown in FIG. 4 described above, in the pFET region Rp, impurities are added to the gate electrode metal film 3, and in this embodiment, N ₂ , Si or Ge is implanted to form an impurity-implanted metal film 6.

  After the formation of the impurity-implanted metal film 6, as shown in FIG. 4, the n-side resist mask 8 in the nFET region Rn is stripped with a resist stripping solution or the like. As a result, as shown in FIG. 4 described above, in the nFET region Rn, the gate electrode metal film 3 into which no impurity is implanted is formed on the gate insulating film 2, and in the pFET region Rp, on the gate insulating film 2 Then, an impurity-implanted metal film 6 into which impurities are implanted is formed. Thereafter, in the same manner as in the case of manufacturing through the manufacturing steps shown in FIGS. 1 to 4, after forming a gate electrode, a known CMISFET formation process flow is sequentially performed to obtain a CMISFET.

  As described above, even if the etch-back of the gate electrode metal film 3 formed in the nFET region Rn is performed earlier than the ion implantation, the nFET region Rn is formed as shown in FIGS. A semiconductor device having the same configuration as that in the case where ion implantation is performed prior to the etching back of the formed gate electrode metal film 3 can be manufactured.

  In addition, the etch back enables the gate electrode metal film 3 formed in the nFET region Rn to have a thickness suitable for the desired threshold value Vth, thereby realizing an nMISFET having the desired threshold value Vth. can do. Therefore, an nMISFET and a pMISFET having a desired threshold value Vth can be realized.

<Second Embodiment>
9 to 12 are cross-sectional views showing the states of the respective manufacturing steps in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. Also in the present embodiment, a CMISFET is manufactured as a semiconductor device, as in the first embodiment. FIG. 9 is a cross-sectional view showing a state in which the formation of the gate electrode metal film 3 has been completed. FIG. 10 is a cross-sectional view showing a state where the formation of the n-side resist mask 4 in the nFET region Rn has been completed.

  Also in the present embodiment, first, similarly to the first embodiment described above, after forming a p-well, an n-well and an element isolation film (not shown), a p-well, an n-well and an n-well are formed on the semiconductor substrate 1. A gate insulating film 2 and a gate electrode metal film 3 are sequentially formed over the entire surface from the surface side where the element isolation film is formed. Thereafter, a resist is applied over the entire surface of the gate electrode metal film 3. Then, by performing photoengraving, as shown in FIG. 10, the resist in the pFET region Rp, which is a region where the work function is to be changed, in the gate electrode metal film 3 is removed. Thus, as in the first embodiment, the nFET region in the upper surface of the gate electrode metal film 3, which is the remaining region of the gate electrode metal film 3 excluding the region where the work function is to be changed. An n-side resist mask 4 is formed over the entire surface belonging to Rn.

  Thereafter, in a state where the n-side resist mask 4 is formed, in other words, in a state where the gate electrode metal film 3 in the nFET region Rn is covered with the n-side resist mask 4, the same as in the first embodiment described above. Based on the implantation conditions, the same impurity as in the first embodiment is ion-implanted over the entire surface from the side where the n-side resist mask 4 is formed, that is, over the nFET region Rn and the pFET region Rp. Thereby, impurities are implanted into the gate electrode metal film 3 in the pFET region Rp. Since the gate electrode metal film 3 in the nFET region Rn is covered with the n-side resist mask 4, impurities are not implanted, or impurities are implanted only into a part on the side in contact with the n-side resist mask 4.

FIG. 11 is a cross-sectional view showing a state where the removal of the gate electrode metal film 3 and the n-side resist mask 4 in the nFET region Rn has been completed. FIG. 12 is a cross-sectional view showing a state in which the formation of another gate electrode metal film 11 on the gate insulating film 2 in the nFET region Rn and the impurity-implanted metal film 6 in the pFET region Rp is completed. By implanting impurities into the gate electrode metal film 3 in the pFET region Rp by the above-described ion implantation, as shown in FIG. 11, in the pFET region Rp, impurities are introduced into the gate electrode metal film 3, and in this embodiment, N ₂ , Si or Ge is implanted to form the impurity-implanted metal layer 6.

  After the formation of the impurity-implanted metal film 6, the n-side resist mask 4 in the nFET region Rn shown in FIG. 10 is stripped with a resist stripping solution or the like. Thereafter, a resist is applied over the entire surface of the gate electrode metal film 3 in the nFET region Rn and the impurity-implanted metal film 6 in the pFET region Rp. Then, by performing photoengraving, as shown in FIG. 11, the resist in the nFET region Rn is removed while leaving the resist in the pFET region Rp. Thus, a p-side resist mask 5 is formed on the impurity-implanted metal film 6 in the pFET region Rp.

  After the formation of the p-side resist mask 5, in this embodiment, as shown in FIG. 11, the p-side resist mask 5 is formed, that is, the impurity-implanted metal film 6 in the pFET region Rp is replaced with the p-side resist mask. In the state covered with 5, the gate electrode metal film 3 is etched over the entire nFET region Rn, and the gate electrode metal film 3 formed in the nFET region Rn is removed over the entire thickness direction. As a result, the nFET region Rn is exposed to the gate insulating film 2. Thereafter, the p-side resist mask 5 in the pFET region Rp is stripped with a resist stripping solution or the like.

  Next, as shown in FIG. 12, on the gate insulating film 2 formed in the nFET region Rn and the impurity-implanted metal film 6 formed in the pFET region Rp, the surface of the gate insulating film 2 in the nFET region Rn and the pFET Another gate electrode metal film 11 is deposited so as to cover the entire surface of the impurity-implanted metal film 6 in the region Rp. The other gate electrode metal film 11 is made of a conductive material like the gate electrode metal film 3. TiN is used as a conductive material constituting another gate electrode metal film 11 in the present embodiment. The other gate electrode metal film 11 is deposited on the gate insulating film 2 in the nFET region Rn and the impurity-implanted metal film 6 in the pFET region Rp so that the film thickness t11 is 1 nm or more and 4 nm or less.

  After the formation of the other metal film 11 for gate electrode, the CMISFET is obtained by sequentially forming a known CMISFET forming process flow after forming the gate electrode in the same manner as in the first embodiment.

  Also in the present embodiment, as in the first embodiment described above, impurities are implanted into the gate electrode metal film 3 formed in the pFET region Rp in the gate electrode metal film 3. Since the impurity-implanted metal film 6 is formed, the same effect as in the first embodiment is achieved. Specifically, since the work function of the gate electrode can be changed by changing the composition of the gate electrode metal film 3 formed in the pFET region Rp, different work functions are provided for the nFET region Rn and the pFET region Rp. Can be easily formed. Further, since the threshold Vth of the pMISFET can be easily adjusted, it is possible to easily form an nMISFET and a pMISFET having a desired threshold Vth.

  In particular, in the present embodiment, after ion implantation, as shown in FIG. 11, the gate electrode metal film 3 formed in the nFET region Rn is removed and then formed in the nFET region Rn as shown in FIG. Another gate electrode metal film 11 is formed on the gate insulating film 2 and on the impurity-implanted metal film 6 which is the gate electrode metal film 3 formed in the pFET region Rp. As a result, another gate electrode metal film 11 having a thickness suitable for the desired threshold value Vth can be formed in the nFET region Rn. Therefore, since an nMISFET having a desired threshold Vth can be realized, an nMISFET and a pMISFET having a desired threshold Vth can be realized.

  In the semiconductor device manufacturing method shown in FIGS. 9 to 12 described above, the case where the semiconductor device is manufactured by performing ion implantation prior to the etching of the gate electrode metal film 3 has been described. For example, the gate electrode metal film 3 may be etched before the ion implantation to manufacture the semiconductor device. That is, the semiconductor device may be manufactured through manufacturing steps shown in FIGS.

  FIG. 13 is a cross-sectional view showing a state in which the formation of the p-side resist mask 7 in the pFET region Rp and the removal of the gate electrode metal film 3 in the nFET region Rn are completed. FIG. 14 is a cross-sectional view showing a state in which the formation of another gate electrode metal film 11 on the gate insulating film 2 in the nFET region Rn and the gate electrode metal film 3 in the pFET region Rp is completed. FIG. 15 is a cross-sectional view showing a state when ions are implanted into the gate electrode metal film 3 and the other gate electrode metal film 11 in the pFET region Rp with the n-side resist mask 12 formed in the nFET region Rn. is there.

  As shown in FIG. 9, after the gate insulating film 2 and the gate electrode metal film 3 are sequentially formed on the semiconductor substrate 1, a resist is applied over the entire surface of the gate electrode metal film 3, and thereafter By performing photolithography, the resist in the nFET region Rn is removed. As a result, the p-side resist mask 7 is formed on the entire upper surface of the gate electrode metal film 3 on the portion belonging to the pFET region Rp.

  Thereafter, as shown in FIG. 13, in a state where the p-side resist mask 7 is formed, in other words, in a state where the gate electrode metal film 3 in the pFET region Rp is covered with the p-side resist mask 7, Etching is performed over the entire surface, and the gate electrode metal film 3 formed in the nFET region Rn is removed over the entire thickness direction. As a result, the nFET region Rn is exposed to the gate insulating film 2. Thereafter, the p-side resist mask 7 in the pFET region Rp is stripped with a resist stripping solution or the like.

  Next, as shown in FIG. 14, on the gate insulating film 2 formed in the nFET region Rn and on the gate electrode metal film 3 formed in the pFET region Rp, the surface of the gate insulating film 2 in the nFET region Rn and Another gate electrode metal film 11 is deposited so as to cover the entire surface of the gate electrode metal film 3 in the pFET region Rp. The other gate electrode metal film 11 is deposited on the gate insulating film 2 in the nFET region Rn and the gate electrode metal film 3 in the pFET region Rp so that the film thickness t11 is 1 nm or more and 4 nm or less.

  Next, after the resist is applied over the entire surface of the other gate electrode metal film 11 in the nFET region Rn and the pFET region Rp, the remaining metal film for the gate electrode is obtained by performing photolithography as shown in FIG. The resist covering the gate electrode metal film 3 in the pFET region Rp 3 is removed. As a result, the n-side resist mask 12 is formed on the entire surface of the remaining portion excluding the portion covering the side surface of the gate electrode metal film 3 among the portions belonging to the nFET region Rn of the other gate electrode metal film 11. To do. The film thickness t12 of the n-side resist mask 12 is equal to or greater than the value (t1 + t11) obtained by adding the film thickness t1 of the gate electrode metal film 3 remaining in the pFET region Rp and the film thickness t11 of the other gate electrode metal film 11. The value of is chosen. As a result, when the impurity is implanted into the gate electrode metal film 3 in the pFET region Rp, the impurity can be prevented from being implanted into the other gate electrode metal film 11 in the nFET region Rn.

Thereafter, the n-side resist mask 12 is formed in a state where the n-side resist mask 12 is formed, in other words, in a state where the other gate electrode metal film 11 in the nFET region Rn is covered with the n-side resist mask 12. Impurity N ₂ , Si, or Ge is ion-implanted over the entire surface from the side, that is, over the nFET region Rn and the pFET region Rp with an ion implantation amount of, for example, 4 × 10 ¹⁵ / cm ² . As a result, impurities are implanted into the gate electrode metal film 3 remaining in the pFET region Rp. As a result of this implantation, as shown in FIG. 12 described above, in the pFET region Rp, an impurity, specifically, N ₂ , Si or Ge is implanted into the gate electrode metal film 3 to form an impurity-implanted metal film 6. The In the present embodiment, the remaining gate electrode metal film 11 formed in the remaining part of the pFET region Rp other than the part covered with the n-side resist mask 12 among the other gate electrode metal films 11 is also applied. Impurities are implanted to form an impurity-implanted metal film.

  After the formation of the impurity-implanted metal film 6, the n-side resist mask 12 in the nFET region Rn is stripped with a resist stripping solution or the like. Thus, as shown in FIG. 12 described above, in the nFET region Rn, another gate electrode metal film 11 into which no impurity is implanted is formed on the gate insulating film 2, and in the pFET region Rp, the gate insulating film An impurity-implanted metal film 6 into which impurities are implanted is formed on 2, and another impurity-implanted metal film in which impurities are implanted into another gate electrode metal film 11 is formed on this impurity-implanted metal film 6. It becomes a state. Thereafter, in the same manner as in the first embodiment described above, after forming a gate electrode, a known CMISFET formation process flow is sequentially performed to obtain a CMISFET.

  Even if the etching of the gate electrode metal film 3 is performed prior to the ion implantation as described above, the ion implantation is performed prior to the etching of the gate electrode metal film 3 as shown in FIGS. Thus, a semiconductor device having the same configuration as that in the case of executing the method can be manufactured.

  Also, by this etching, after removing the gate electrode metal film 3 formed in the nFET region Rn and before ion implantation, as shown in FIG. 14, on the gate insulating film 2 formed in the nFET region Rn and the pFET Another gate electrode metal film 11 is formed on the gate electrode metal film 3 formed in the region Rp. As a result, another gate electrode metal film 11 having a thickness suitable for the desired threshold value Vth can be formed in the nFET region Rn. Therefore, since an nMISFET having a desired threshold Vth can be realized, an nMISFET and a pMISFET having a desired threshold Vth can be realized.

<Third Embodiment>
16 to 21 are cross-sectional views showing the states of the respective manufacturing steps in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. Also in the present embodiment, a CMISFET is manufactured as a semiconductor device, as in the first embodiment. FIG. 16 is a cross-sectional view showing a state where the formation of the gate electrode metal film 21 is completed.

  Also in the present embodiment, first, similarly to the first embodiment described above, after forming a p-well, an n-well and an element isolation film (not shown), a p-well, an n-well and an n-well are formed on the semiconductor substrate 1. The gate insulating film 2 and the gate electrode metal film 21 are sequentially formed over the entire surface from the surface side where the element isolation film is formed. In the present embodiment, the film thickness t21 of the gate electrode metal film 21 is smaller than the film thickness t1 of the gate electrode metal film 3 formed in the first embodiment, specifically, 1 nm or more and 4 nm. Selected below.

  FIG. 17 is a cross-sectional view showing a state where the formation of the hard mask 22 is completed. In the present embodiment, after the gate electrode metal film 21 is formed, a hard mask material is deposited over the entire surface of the gate electrode metal film 21. Thereafter, as shown in FIG. 17, the hard mask material in the pFET region Rp, which is the region whose work function is to be changed, is removed by etching as shown in FIG. As a result, on the entire upper surface of the gate electrode metal film 21, which is the remaining area of the gate electrode metal film 21 excluding the region where the work function is to be changed, on the entire surface belonging to the nFET region Rn. A mask 22 is formed.

  Examples of the material of the hard mask 22 include silicon oxide (SiOx) and silicon nitride (SiNx). The film thickness t22 of the hard mask 22 is selected to be equal to or greater than the film thickness t21 of the gate electrode metal film 21. This prevents impurities from being implanted into the gate electrode metal film 21 in the nFET region Rn when the impurity is implanted into the gate electrode metal film 21 in the pFET region Rp.

  FIG. 18 is a cross-sectional view showing a state where the formation of another gate electrode metal film 23 on the hard mask 22 in the nFET region Rn and the gate electrode metal film 21 in the pFET region Rp is completed. After the hard mask 22 is formed, on the hard mask 22 in the nFET region Rn and on the gate electrode metal film 21 in the pFET region Rp, the surface of the hard mask 22 in the nFET region Rn and the metal film 21 for the gate electrode in the pFET region Rp. Another gate electrode metal film 23 is deposited so as to cover the entire surface of the gate electrode. The other gate electrode metal film 23 is made of a conductive material like the gate electrode metal film 21. TiN is used as a conductive material constituting another gate electrode metal film 23 in the present embodiment. The film thickness t23 of the other gate electrode metal film 23 takes into consideration the film thickness t21 of the gate electrode metal film 21 and the film thickness t21 of the gate electrode metal film 21 and the film of the other gate electrode metal film 23. A value t24 (= t21 + t23) obtained by adding the thickness t23 is selected to be 15 nm or more and 20 nm or less.

  FIG. 19 is a cross-sectional view showing a state in which ions are implanted into another gate electrode metal film 23 and gate electrode metal film 21 in the pFET region Rp. After the formation of the other gate electrode metal film 23, the entire surface from the side where the other gate electrode metal film 23 is formed, that is, the nFET region, based on the implantation conditions similar to those of the first embodiment. Impurities are implanted over the Rn and pFET region Rp, specifically, ions are implanted. As a result, impurities are implanted into the other gate electrode metal film 23 of the nFET region Rn and the pFET region Rp and the gate electrode metal film 21 of the pFET region Rp. Since the gate electrode metal film 3 in the nFET region Rn is covered with the hard mask 22, no impurity is implanted.

  FIG. 20 is a cross-sectional view showing a state in which the removal of the other gate electrode metal film 23 in the nFET region Rn has been completed. By the above-described ion implantation, as shown in FIG. 19, in the pFET region Rp, impurities are implanted into the gate electrode metal film 21 to form an impurity implanted metal film 25, and other gate electrode metal films 23 are formed. Impurities are implanted to form another impurity-implanted metal film 26.

  After ion implantation, a resist is applied over the entire surface of the other gate electrode metal film 23 in the nFET region Rn and the other impurity-implanted metal film 26 in the pFET region Rp, and photolithography is performed to obtain FIG. As shown, the resist in the nFET region Rn is removed leaving the resist in the pFET region Rp, and a p-side resist mask 24 is formed on the other impurity-implanted metal film 26 in the pFET region Rp.

  Thereafter, in a state where the p-side resist mask 24 is formed, in other words, in a state where the other impurity-implanted metal film 26 of the pFET region Rp is covered with the p-side resist mask 24, another gate is formed over the entire nFET region Rn. The electrode metal film 23 is etched and removed over the entire thickness direction. As a result, the nFET region Rn is exposed to the hard mask 22.

  FIG. 21 is a cross-sectional view showing a state where the removal of the hard mask 22 is completed. After removing the other gate electrode metal film 23 in the nFET region Rn, the hard mask 22 in the nFET region Rn is removed by etching with the p-side resist mask 24 formed. As a result, the nFET region Rn is exposed to the gate electrode metal film 21.

  Thereafter, the p-side resist mask 24 in the pFET region Rp is stripped with a resist stripping solution or the like. As a result, as shown in FIG. 21, in the nFET region Rn, the gate electrode metal film 21 in which no impurity is implanted is formed on the gate insulating film 2, and in the pFET region Rp, on the gate insulating film 2, The impurity-implanted metal film 25 and other impurity-implanted metal film 26 into which impurities have been implanted are sequentially formed.

  After the p-side resist mask 24 is peeled off, a gate electrode is formed and then a known CMISFET formation process flow is sequentially performed in the same manner as in the first embodiment to obtain a CMISFET.

  As described above, according to the present embodiment, as in the first embodiment described above, impurities are implanted into the gate electrode metal film 21 in the pFET region Rp in the gate electrode metal film 21. An impurity-implanted metal film 25 is formed, and another impurity-implanted metal film 26 into which impurities are implanted is formed on the impurity-implanted metal film 25, so that the same effect as in the first embodiment is achieved. The Specifically, the composition of the gate electrode metal film 21 and the other gate electrode metal film 23 formed in the pFET region Rp can be changed to change the work function of the gate electrode, so that the nFET region Rn and A gate electrode having a different work function can be easily formed in the pFET region Rp. Further, since the threshold Vth of the pMISFET can be easily adjusted, it is possible to easily form an nMISFET and a pMISFET having a desired threshold Vth.

  In the semiconductor device manufacturing method shown in FIGS. 16 to 21 described above, the case where the semiconductor device is manufactured by performing ion implantation prior to the removal of the other gate electrode metal film 23 in the nFET region Rn has been described. However, the present invention is not limited to this method. For example, the semiconductor device may be manufactured by removing the gate electrode metal film 23 other than the nFET region Rn before the ion implantation. That is, the semiconductor device may be manufactured through the manufacturing steps shown in FIGS.

  FIG. 22 is a cross-sectional view showing a state in which the removal of the other gate electrode metal film 23 in the nFET region Rn has been completed. When the semiconductor device is manufactured through the manufacturing steps shown in FIGS. 22 to 23, after the other gate electrode metal film 23 is formed as shown in FIG. 18, the other gate electrode metal film 23 is formed on the other gate electrode metal film 23. The resist is applied over the entire surface, that is, over the nFET region Rn and the pFET region Rp. Thereafter, by performing photoengraving, as shown in FIG. 22, the resist of the nFET region Rn is removed while leaving the resist of the pFET region Rp, and the pFET region Rp is formed on the other metal film 23 for the gate electrode. A side resist mask 27 is formed.

  Thereafter, in a state where the p-side resist mask 27 is formed, in other words, in a state where the other gate electrode metal film 23 in the pFET region Rp is covered with the p-side resist mask 27, The gate electrode metal film 23 is etched and removed over the entire thickness direction. As a result, the nFET region Rn is exposed to the hard mask 22.

  FIG. 23 is a cross-sectional view showing a state when ions are implanted into another gate electrode metal film 23 and gate electrode metal film 21 in the pFET region Rp. After removal of the other gate electrode metal film 23 in the nFET region Rn, the hard mask 22 in the nFET region Rn is removed by etching while the p-side resist mask 27 is formed. As a result, the nFET region Rn is exposed to the gate electrode metal film 21.

  After removal of the hard mask 22, the p-side resist mask 27 in the pFET region Rp is stripped with a resist stripping solution or the like. Thereafter, a resist is applied again over the entire surface of the gate electrode metal film 21 in the nFET region Rn and the other gate electrode metal film 23 in the pFET region Rp. Then, by performing photoengraving, as shown in FIG. 23, the resist in the pFET region Rp is removed while leaving the resist in the nFET region Rn. Thus, an n-side resist mask 28 is formed on the gate electrode metal film 21 in the nFET region Rn. The thickness dimension t25 of the n-side resist mask 28 is selected to be equal to or greater than a value t24 (= t21 + t23) obtained by adding the film thickness t21 of the gate electrode metal film 21 and the film thickness t23 of the other gate electrode metal film 23. . As a result, when impurities are implanted into the gate electrode metal film 21 and the other gate electrode metal film 23 in the pFET region Rp, the impurities are implanted into the gate electrode metal film 21 in the nFET region Rn. Can be prevented.

After that, in a state where the n-side resist mask 28 is formed, in other words, in a state where the gate electrode metal film 21 in the nFET region Rn is covered with the n-side resist mask 28, from the side where the n-side resist mask 28 is formed. Impurity ions N ₂ , Si, or Ge are ion-implanted over the entire surface, that is, over the nFET region Rn and the pFET region Rp, for example, with an ion implantation amount of 4 × 10 ¹⁵ / cm ² . As a result, impurities are implanted into the gate electrode metal film 21 and the other gate electrode metal film 23 in the pFET region Rp, and as shown in FIG. 21 described above, the impurity implanted metal film 25 and the other impurity implanted metal film 26. Is formed. Since the gate electrode metal film 21 in the nFET region Rn is covered with the n-side resist mask 28, no impurity is implanted.

  After the ion implantation, the n-side resist mask 28 in the nFET region Rn is stripped with a resist stripping solution or the like. As a result, as shown in FIG. 21 described above, in the nFET region Rn, the gate electrode metal film 21 in which no impurity is implanted is formed on the gate insulating film 2, and in the pFET region Rp, on the gate insulating film 2 Then, the impurity-implanted metal film 25 and the other impurity-implanted metal film 26 into which impurities are implanted are sequentially formed. Thereafter, in the same manner as in the first embodiment described above, after forming a gate electrode, a known CMISFET formation process flow is sequentially performed to obtain a CMISFET.

  As described above, even if the gate electrode metal film 23 in the nFET region Rn is removed before the ion implantation, the other gate electrode in the nFET region Rn as shown in FIGS. A semiconductor device having the same configuration as that when ion implantation is performed prior to the removal of the metal film 23 can be manufactured.

  In each of the above-described embodiments, the gate electrode is formed based on a gate-first process in which heat treatment is performed after the formation of the gate electrode. However, according to each of the above-described embodiments, in the gate-first process, metal is used. The work function of the formed gate electrode can be controlled relatively easily.

It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention. It is a graph which shows an effective work function when an impurity is ion-implanted into the metal film 3 for gate electrodes. It is a graph which shows the relationship between the gate voltage when ion-implanting an impurity to the metal film 3 for gate electrodes. It is sectional drawing which shows the state of the stage which completed formation of the p side resist mask 7 to pFET area | region Rp, and removal of a part of metal film 3 for gate electrodes of nFET area | region Rn. It is sectional drawing which shows the state of the stage which removal of the p side resist mask 7 of pFET area | region Rp, and formation of the n side resist mask 8 to nFET area | region Rn was complete | finished. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention. It is sectional drawing which shows the state of the stage which completed formation of the p side resist mask 7 to pFET area | region Rp, and removal of the metal film 3 for gate electrodes of nFET area | region Rn. It is sectional drawing which shows the state in the stage where formation of the other metal film 11 for gate electrodes on the gate insulating film 2 of nFET area | region Rn and the metal film 3 for gate electrodes of pFET area | region Rp was complete | finished. It is sectional drawing which shows a mode when ion implantation is carried out to the metal film 3 for gate electrodes of the pFET area | region Rp, and the other metal film 11 for gate electrodes in the state which formed the n side resist mask 12 in the nFET area | region Rn. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of each manufacturing process in the manufacturing method of the semiconductor device which is the 3rd Embodiment of this invention. It is sectional drawing which shows the state of the stage which removal of the metal film 23 for other gate electrodes of nFET area | region Rn was complete | finished. It is sectional drawing which shows a mode when ion-implanting into the metal film 23 for gate electrodes and the metal film 21 for gate electrodes of the pFET area | region Rp.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Gate insulating film, 3,21 Metal film for gate electrodes, 4, 8, 12, 28 n side resist mask, 5, 7, 24, 27 p side resist mask, 6,25 impurity implantation metal film, 11, 23 Other gate electrode metal films, 22 hard masks, 26 other impurity-implanted metal films.

Claims (11)

A method of manufacturing a semiconductor device in which a first conductivity type semiconductor element and a second conductivity type semiconductor element having different conductivity types are provided side by side,
(A) Hafnium (Hf) is deposited on a semiconductor substrate having a first conductivity type element region in which the first conductivity type semiconductor element is formed and a second conductivity type element region in which the second conductivity type semiconductor element is formed. Forming a gate insulating film made of a hafnium-based material,
(B) forming a gate electrode metal film made of a metal material on the gate insulating film formed in the first conductivity type element region and the second conductivity type element region;
(C) Injecting impurities into the gate electrode metal film formed in the second conductivity type element region.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the impurity is implanted by ion implantation.   The method for manufacturing a semiconductor device according to claim 1, wherein the metal material constituting the metal film for the gate electrode is titanium nitride (TiN). The second conductive semiconductor element is a p-channel MIS transistor,
The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is a nitrogen molecule (N ₂ ). The method of manufacturing a semiconductor device according to claim 4, wherein a work function of the p-channel MIS transistor is increased by injecting nitrogen molecules (N ₂ ) into the gate electrode metal film. The second conductivity type semiconductor element is a p-channel type MIS transistor,
The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is at least one of germanium (Ge) and silicon (Si).   7. The semiconductor device according to claim 6, wherein a work function of the p-channel MIS transistor is reduced by injecting at least one of germanium (Ge) and silicon (Si) into the gate electrode metal film. Manufacturing method. After the step (c),
3. The method of manufacturing a semiconductor device according to claim 1, further comprising: (d) a step of etching back the gate electrode metal film formed in the first conductivity type element region. After the step (b) and before the step (c),
3. The method of manufacturing a semiconductor device according to claim 1, further comprising: (e) a step of etching back the gate electrode metal film formed in the first conductivity type element region. After the step (c),
(F) removing the gate electrode metal film formed in the first conductivity type element region;
(G) forming another gate electrode metal film on the gate insulating film formed in the first conductivity type element region and the gate electrode metal film formed in the second conductivity type element region; The method of manufacturing a semiconductor device according to claim 1, further comprising: After the step (b) and before the step (c),
(H) removing the gate electrode metal film formed in the first conductivity type element region;
(I) forming another gate electrode metal film on the gate insulating film formed in the first conductivity type element region and the gate electrode metal film formed in the second conductivity type element region; Further comprising
3. The process according to claim 1, wherein in the step (c), an impurity is implanted into the gate electrode metal film and the other gate electrode metal film formed in the second conductivity type element region. Semiconductor device manufacturing method.

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