JP2010104176A - Circuit and method for controlling step-up/down dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit and a method for controlling a step-up/down DC-DC converter, which reduces temporary drop of an output voltage VOUT of the step-up/down DC-DC converter by correcting a detection resistance in switching an operation mode in the step-up/down DC-DC converter. <P>SOLUTION: A voltage value applied to both ends of the detection resistance can be lowered by lowering a resistance value of the detection resistance when switching the operation mode. After switching the operation mode, a control part controls the voltage value applied to both ends of the detection circuit, to the value in a previous state. Large peak currents flows and reduction in the output voltage due to switching of the operation mode can be improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a step-up / step-down DC-DC converter control circuit and a step-up / step-down DC-DC converter control method, and more particularly to a step-up / step-down DC-DC converter control circuit and a step-up / step-down DC / DC converter control circuit that suppress fluctuations in output voltage that occur during mode switching. The present invention relates to a pressure DC-DC converter control method.

  The DC-DC converter is a compact, lightweight, and highly efficient DC power source that uses a semiconductor switching element, and is widely used in electronic devices and the like. In recent years, demands for small size, lightweight, and high efficiency are increasing. The basic principle of the DC-DC converter is to maintain the direct current output voltage at a constant level by turning on / off the switching element at a high frequency and variably controlling the duty ratio of the on time and the off time. In addition, the DC-DC converter includes a step-down type capable of obtaining an output voltage lower than the input voltage, a step-up type capable of obtaining an output voltage higher than the input voltage, and a step-up / step-down type capable of obtaining a constant output voltage independent of the input voltage. is there.

  FIG. 1 shows a step-up / step-down DC-DC converter. In the step-up / step-down DC-DC converter shown in FIG. 1, a state in which energy is stored in the choke coil from the input side (hereinafter “state A”) and a state in which energy is discharged from the choke coil to the output side (hereinafter “state B”). And are repeated alternately.

  Further, the state A includes a state A1 in which energy is only stored in the choke coil and energy is not released to the output side, and a state A2 in which energy is supplied to the choke coil and at the same time energy is released to the output side. A constant output voltage can be obtained by variably controlling the ratio for each period of states A1, B, and A2.

  Also, in the step-up / step-down DC-DC converter control circuit, the step-down operation mode selected when the input voltage is higher than the output voltage due to the fluctuation of the input voltage, the step-up / step-down selected when the input voltage and the output voltage are close to each other In general, the operation mode is divided into a boost operation mode selected when the input voltage is lower than the output voltage, and the period ratios of the states A1, B, and A2 are generally set for each operation mode.

JP 2005-192212 A JP 2005-192323 A

  In the circuit of FIG. 1, the peak current flowing through the coil differs depending on the operation mode such as the step-down operation mode, the step-up / step-down operation mode, and the step-up operation mode. In the step-down operation mode in which the input voltage is higher than the output voltage, energy can be stored in the coil even in the state A2, so that the state A1 can be limited to the minimum necessary period. The period of state A1 in which energy is not supplied to the output side is minimized, and an efficient operation that can discharge energy to the output side while storing energy in the coil can be performed. The peak current of the coil can be reduced. On the other hand, in the step-up operation mode in which the input voltage is lower than the output voltage, energy cannot be stored in the coil in state A2, and energy is exclusively released to the output side. In principle, the step-up operation mode must have a period of state A1. That is, it is necessary to secure a period for stopping energy release to the output side and storing energy in the coil. The efficiency of energy release to the output side is lower than in the step-down operation mode. For this reason, the peak current of the coil increases in the boosting operation mode. In the buck-boost operation mode, which is an intermediate operation mode between the step-down operation mode and the step-up operation mode, the peak current of the coil is also intermediate.

  The peak coil current required for the same load current is different for each operation mode. Therefore, when the operation mode is switched, the required peak current changes abruptly. For example, when switching from the step-down operation mode to the step-up / step-down operation mode, or when switching from the step-up / step-down operation mode to the step-up operation mode, the peak current of the coil required to maintain the same load current increases. However, in the control circuit, the error amplifier responds by detecting a change in the output voltage. For this reason, when the operation mode is switched to an operation mode in which the required peak current increases, the control circuit cannot immediately respond to the switching of the operation mode, and control that increases the peak current of the coil. Must wait until it detects a drop in output voltage. In the step-up / step-down DC-DC converter control circuit, the output voltage VOUT of the step-up / step-down DC-DC converter is transiently lowered due to a response delay accompanying switching of the operation mode.

  The present invention has been proposed in view of the above-described problems. In the step-up / step-down DC-DC converter, the detection resistor is corrected when the operation mode is switched, whereby the output voltage VOUT of the step-up / step-down DC-DC converter is corrected. An object of the present invention is to provide a step-up / step-down DC-DC converter control circuit capable of suppressing a transient drop and a method for controlling the step-up / step-down DC-DC converter.

  A first step-up / step-down DC-DC converter control circuit disclosed in the present application is a step-up / step-down DC-DC converter control circuit that controls a peak current flowing in an inductance element, and a voltage corresponding to a peak current or a current corresponding to the peak current. A first detection resistor for conversion, a detection resistor for converting a peak current or a current corresponding to the peak current into a voltage, a second detection resistor having a resistance value larger than the first detection resistor, and a peak current or a peak current A detection resistor for converting current into voltage, the third detection resistor having a resistance value larger than the second detection resistor, the third detection resistor in the step-down operation mode, and the second detection resistor in the step-up / step-down operation mode. And a first selection circuit that selects the first detection resistor in the boosting operation mode.

  In response to switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode, the detection resistor is changed from the third detection resistor to the second detection resistor, and from the second detection resistor to the first. The resistance value is lowered by switching to the detection resistor.

  Also, a first step-up / step-down DC-DC converter control method disclosed in the present application is a step-up / step-down DC-DC converter control method for controlling a peak current flowing in an inductance element. A step of converting the current corresponding to the current with the first detection resistor, and a voltage corresponding to the peak current or the current corresponding to the peak current with the second detection resistor having a resistance value larger than the first detection resistor in the step-up / step-down operation mode. A step of converting, and a step of converting a voltage of a peak current or a current corresponding to the peak current by a third detection resistor having a resistance value larger than the second detection resistor in the step-down operation mode.

  Thereby, in switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode, the voltage value appearing at both ends of the detection resistor can be reduced according to the same peak current. Thereby, the voltage conversion value of the peak current flowing through the coil can be reduced in accordance with the switching from the step-down operation mode to the step-up / step-down operation mode and the switching from the step-up / step-down operation mode to the step-up operation mode. Utilizing the fact that the control response in the step-up / step-down DC-DC converter control circuit is delayed from the switching of the operation mode, the voltage conversion value is converted to the control circuit in response to the decrease in the voltage conversion value of the peak current immediately after the switching of the operation mode. The value is controlled to the state before the operation mode is switched. As a result, control is performed so that more peak current flows. Response of the control circuit even if the peak current of the coil for supplying the same load current increases in response to switching from the step-down operation mode to the step-up / step-down operation mode and from the step-up / step-down operation mode to the step-up operation mode Regardless of the delay, the peak current can be increased without delay. It is possible to suppress a decrease in output voltage due to switching of the operation mode.

  A second step-up / step-down DC-DC converter control circuit disclosed in the present application is a step-up / step-down DC-DC converter control circuit that controls a peak current flowing through an inductance element, and a detection circuit that detects a current flowing through the inductance element. A variable current circuit that generates a current according to a detection result by the detection circuit, and a detection resistor that converts a voltage generated by the current generated by the variable current circuit. A first current circuit for flowing one current, a second current circuit for flowing a second current corresponding to the peak current or the peak current that is larger than the first current, and a peak current or a current larger than the second current A third current circuit for flowing a third current corresponding to the peak current, a third current circuit selected in the step-down operation mode, and a second current circuit in the step-up / step-down operation mode Selected, and is configured and a second selection circuit for selecting a first current circuit to boost operation mode.

  In response to switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode, the variable current circuit makes the current flowing through the detection resistor variable according to the current flowing through the inductance element. . In this case, the second selection circuit selects a third current circuit that passes a third current that is larger than the second current in the step-down operation mode, and the second current that is larger than the first current in the step-up / step-down operation mode. Is selected, and the first current circuit for supplying the first current is selected in the step-up operation mode.

  Thereby, in switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode, the voltage value appearing at both ends of the detection resistor can be reduced according to the same peak current. Thereby, the voltage conversion value of the peak current flowing through the coil can be reduced in accordance with the switching from the step-down operation mode to the step-up / step-down operation mode and the switching from the step-up / step-down operation mode to the step-up operation mode. Utilizing the fact that the control response in the step-up / step-down DC-DC converter control circuit is delayed from the switching of the operation mode, the voltage conversion value is converted to the control circuit in response to the decrease in the voltage conversion value of the peak current immediately after the switching of the operation mode. The value is controlled to the state before the operation mode is switched. As a result, control is performed so that more peak current flows. Response of the control circuit even if the peak current of the coil for supplying the same load current increases in response to switching from the step-down operation mode to the step-up / step-down operation mode and from the step-up / step-down operation mode to the step-up operation mode Regardless of the delay, the peak current can be increased without delay. It is possible to suppress a decrease in output voltage due to switching of the operation mode.

  A third step-up / step-down DC-DC converter control circuit disclosed in the present application is a step-up / step-down DC-DC converter control circuit that controls a peak current flowing in an inductance element, and a voltage corresponding to the peak current or the peak current is a voltage. A detection resistor to be converted, a first current source for flowing a first correction current through the detection resistor, a second current source for flowing a second correction current larger than the first correction current through the detection resistor, and a second correction current through the detection resistor A third current source for supplying a large third correction current, a third current source in the step-down operation mode, a second current source in the step-up / down operation mode, and a first current source in the step-up operation mode are selected. And 3 selection circuits.

  In response to switching from the step-down operation mode to the step-up / step-down operation mode, and switching from the step-up / step-down operation mode to the step-up operation mode, the detection resistor changes from the third correction current to the second correction current, and from the second correction current to the first. The correction current is reduced by switching to the correction current.

  A second step-up / step-down DC-DC converter control method disclosed in the present application is a step-up / step-down DC-DC converter control method for controlling a peak current flowing through an inductance element, and includes a detection resistor in the step-up operation mode. A step of flowing one correction current, a step of flowing a second correction current larger than the first correction current to the detection resistor in the step-up / step-down operation mode, and a third correction current larger than the second correction current to the detection resistor in the step-down operation mode. A step of flowing.

  Thereby, in switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode, the voltage value appearing at both ends of the detection resistor can be reduced according to the same peak current. The voltage conversion value of the peak current flowing in the coil can be reduced in accordance with switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up operation mode. Utilizing the fact that the control response in the step-up / step-down DC-DC converter control circuit is delayed from the switching of the operation mode, the voltage conversion value is converted to the control circuit in response to the decrease in the voltage conversion value of the peak current immediately after the switching of the operation mode. The value is controlled to the state before the operation mode is switched. As a result, control is performed so that more peak current flows. Response of the control circuit even if the peak current of the coil for supplying the same load current increases in response to switching from the step-down operation mode to the step-up / step-down operation mode and from the step-up / step-down operation mode to the step-up operation mode Regardless of the delay, the peak current can be increased without delay. It is possible to suppress a decrease in output voltage due to switching of the operation mode.

  According to the first, second and third step-up / step-down DC-DC converter control circuits disclosed in the present application, switching from the step-down operation mode to the step-up / step-down operation mode and switching from the step-up / step-down operation mode to the step-up / down operation mode are performed. In addition, the voltage conversion value of the peak current flowing through the coil can be reduced. Since the change in the control response in the step-up / step-down DC-DC converter control circuit is delayed from the switching of the operation mode, immediately after the switching of the operation mode, the voltage conversion value is converted by the control circuit according to the decrease in the voltage conversion value of the peak current. Attempts to control the value to the state before switching the operation mode. As a result, control is performed so that more peak current flows. Even if the peak current of the coil for supplying the same load current increases according to the switching from the step-down operation mode to the step-up / step-down operation mode, and from the step-up / step-down operation mode to the step-up operation mode, the peak current is not delayed. Can be increased. As a result, in the step-up / step-down DC-DC converter control circuit, this occurs due to a response delay accompanying the switching of the operation mode. A transient decrease in the output voltage VOUT of the step-up / step-down DC-DC converter can be suppressed.

  A circuit configuration of the step-up / step-down DC-DC converter including the step-up / step-down DC-DC converter control circuit of the embodiment will be described. In FIG. 3, reference numeral 1 denotes the DC-DC converter control circuit of the first embodiment. In FIG. 4, reference numeral 2 denotes a DC-DC converter control circuit according to the second embodiment. In FIG. 5, 3 is the DC-DC converter control circuit of the third embodiment.

  In the first embodiment (FIG. 3), the input voltage VIN is input to the source terminal and the terminal (LX0) of the PMOS transistor M1. The gate terminal of the PMOS transistor M1 is connected to the terminal (LX2). The drain terminal of the PMOS transistor M1 is connected to the terminal (LX3).

  The terminal (LX4) is connected to one terminal of the coil L1 and the drain terminal of the NMOS transistor M3. The gate terminal of the NMOS transistor M3 is connected to the terminal (LX5). The source terminal of the NMOS transistor M3 is grounded.

  The other terminal of the coil L1 is connected to the drain terminal of the NMOS transistor M4 and the drain terminal of the PMOS transistor M2. The gate terminal of the NMOS transistor M4 is connected to the terminal (LX6). The source terminal of the NMOS transistor M4 is grounded. The gate terminal of the PMOS transistor M2 is connected to the terminal (LX1). The source terminal of the PMOS transistor M2 is connected to the output terminal (VOUT), one terminal of the output capacitor C1 grounded, and the feedback terminal (FB).

  The feedback terminal (FB) is connected to one terminal of the resistance element R1. The other terminal of the resistive element R1 is connected to one terminal of the grounded resistive element R2. The resistance element R1 and the resistance element R2 constitute a voltage dividing circuit. The voltage dividing points of the resistance element R1 and the resistance element R2 are connected to the inverting input terminal of the error amplifier ERA1. The set voltage VREF is input to the non-inverting input terminal of the error amplifier ERA1.

  The output terminal of the error amplifier ERA1 is connected to the inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the reset terminal (R) of the transistor drive circuit SWD. The set terminal (S) of the transistor drive circuit SWD is connected to the oscillator OSC. The output terminal (Q1) of the transistor drive circuit SWD is connected to the terminal (LX1). The output terminal (Q2) of the transistor drive circuit SWD is connected to the terminal (LX2). The output terminal (Q3) of the transistor drive circuit SWD is connected to the terminal (LX5). The output terminal (Q4) of the transistor drive circuit SWD is connected to the terminal (LX6).

  The terminal (LX3) is connected to the non-inverting input terminal of the amplifier AMP1 and one terminal of the resistance element RA. The terminal (LX4) is connected to the inverting input terminal of the amplifier AMP1 and the other terminal of the resistor element RA. The source terminal of the PMOS transistor M5 is connected to the terminal (LX0). The gate terminal of the PMOS transistor M5 is connected to the output terminal of the amplifier AMP1. The drain terminal of the PMOS transistor M5 is connected to one terminal of the first selection circuit SW1 and the non-inverting input terminal of the comparator CMP1. The first other terminal, the second other terminal, and the third other terminal of the first selection circuit SW1, respectively, have one terminal of the grounded first detection resistor RS1, one terminal of the grounded second detection resistor RS2, and One terminal of the grounded third detection resistor RS3 is connected. An operation mode conversion circuit MS is connected to the transistor drive circuit SWD and the first selection circuit SW1.

  Also in the second and third embodiments, the external configuration of the DC-DC converter control circuits 2 and 3 and the configuration of the resistance element R1, the resistance element R2, the error amplifier ERA1, the set voltage VREF, and the transistor drive circuit SWD are the same. The same as in the first embodiment. Therefore, only differences will be described below.

  In the second embodiment (FIG. 4), the terminal (LX3) is connected to the non-inverting input terminal of the amplifier AMP1 and one terminal of the resistor element RA. The terminal (LX4) is connected to the inverting input terminal of the amplifier AMP1 and the other terminal of the resistance element RA. The terminal (LX0) is connected to the source terminal of the PMOS transistor M10, the source terminal of the PMOS transistor M11, and the source terminal of the PMOS transistor M12. The output terminal of the amplifier AMP1 is connected to the gate terminal of the PMOS transistor M10, the gate terminal of the PMOS transistor M11, and the gate terminal of the PMOS transistor M12.

  The drain terminal of the PMOS transistor M10, the drain terminal of the PMOS transistor M11, and the drain terminal of the PMOS transistor M12 are connected to the first one terminal, the second one terminal, and the third one terminal of the second selection circuit SW2, respectively. The other terminal of the second selection circuit SW2 is connected to one terminal of the grounded detection resistor RS and the non-inverting input terminal of the comparator CMP1. The operation mode conversion circuit MS is connected to the transistor drive circuit SWD and the second selection circuit SW2.

  In the third embodiment (FIG. 5), the terminal (LX0) is one terminal of the first current source I1, one terminal of the second current source I2, one terminal of the third current source I3, and the source terminal of the PMOS transistor M5. Connected to. The gate terminal of the PMOS transistor M5 is connected to the output terminal of the amplifier AMP1. The other terminal of the first current source I1, the other terminal of the second current source I2, and the other terminal of the third current source I3 are respectively a first terminal, a second one terminal, and a third one of the third selection circuit SW3. Connected to the terminal. The other terminal of the third selection circuit SW3 is connected to one terminal of the grounded detection resistor RS, the non-inverting input terminal of the comparator CMP1, and the drain terminal of the PMOS transistor M5. The operation mode conversion circuit MS is connected to the transistor drive circuit SWD and the third selection circuit SW3.

  In the first to third embodiments, the voltage dividing circuit constituted by the resistance element R1 and the resistance element R2 has been described as being built in the DC-DC converter control circuits 1 to 3. However, the voltage dividing circuit composed of the resistance element R1 and the resistance element R2 can also be configured as an external element of the DC-DC converter control circuit. In the above description, the PMOS transistor M1, the PMOS transistor M2, the NMOS transistor M3, and the NMOS transistor M4 are configured as external elements of the DC-DC converter control circuits 1 to 3. However, it may be configured to be built in the DC-DC converter control circuit. Here, the DC-DC converter control circuits 1, 2, and 3 can be configured as an integrated circuit, for example.

  Next, the configuration of the operation mode conversion circuit MS (FIG. 6) will be described. The input voltage VIN is input to one terminal of the resistance element R3. The other terminal of the resistive element R3 is connected to one terminal of the grounded resistive element R4. Resistive element R3 and resistive element R4 constitute a voltage dividing circuit. A non-inverting input terminal of the comparator CMP2 and the comparator CMP3 is connected to a voltage dividing point between the resistor element R3 and the resistor element R4. The output voltage VOUT is input to one terminal of the resistance element R5. The other terminal of the resistor element R5 is connected to one terminal of the grounded resistor element R6. Resistive element R5 and resistive element R6 constitute a voltage dividing circuit. A negative terminal of the constant voltage source E1 and a positive terminal of the constant current source E2 are connected to the voltage dividing point of the resistive element R5 and the resistive element R6. The inverting input terminal of the comparator CMP2 is connected to the + terminal of the constant voltage source E1. The inverting input terminal of the comparator CMP3 is connected to the negative terminal of the constant current source E2.

  The output terminal of the comparator CMP2 is connected to the input terminal of the NOR circuit NOR1 and the input terminal of the NAND circuit NAND1. The output terminal of the comparator CMP3 is connected to the input terminal of the NOR circuit NOR1 and the input terminal of the NAND circuit NAND1. The output terminal of the NOR circuit NOR1 is connected to the input terminal of the NOT circuit NOT2 and the input terminal of the NOR circuit NOR2. The output terminal of the NAND circuit NAND1 is connected to the input terminal of the NOT circuit NOT1. The output terminal of the NOT circuit NOT1 is connected to the input terminal of the NOT circuit NOT3 and the input terminal of the NOR circuit NOR2. The output terminal of the NOR circuit NOR2 is connected to the input terminal of the NOT circuit NOT4. The output terminal of the NOT circuit NOT2, the output terminal of the NOT circuit NOT3, and the output terminal of the NOT circuit NOT4 form one bus.

  Next, the operation of the step-up / step-down DC-DC converter including the step-up / step-down DC-DC converter control circuit of the embodiment will be described. As common to the first to third embodiments, the operation mode conversion circuit MS compares the input voltage VIN and the output voltage VOUT. When the input voltage VIN is higher than the voltage value obtained by adding the voltage of the constant voltage source E1 to the output voltage VOUT, a high level signal is output from the output terminal of the NOT circuit NOT2. Low level signals are output from the output terminal of the NOT circuit NOT3 and the output terminal of the NOT circuit NOT4. When the input voltage VIN is lower than the voltage value obtained by adding the voltage of the constant voltage source E1 to the output voltage VOUT and higher than the voltage value obtained by subtracting the voltage of the constant voltage source E2 from the output voltage VOUT, the output terminal of the NOT circuit NOT4 Outputs a high level signal. Low level signals are output from the output terminal of the NOT circuit NOT2 and the output terminal of the NOT circuit NOT3. When the input voltage VIN is lower than the voltage obtained by subtracting the voltage of the constant voltage source E2 from the output voltage VOUT, a high level signal is output from the NOT circuit NOT3 output terminal. Low level signals are output from the output terminal of the NOT circuit NOT2 and the output terminal of the NOT circuit NOT4.

  The output terminal of the NOT circuit NOT2, the output terminal of the NOT circuit NOT3, and the output terminal of the NOT circuit NOT4 are one bus signal. Then, by inputting the bus signal to the transistor drive circuit SWD, it is set in which operation mode the transistor drive circuit SWD operates.

  When a high level signal is output from the output terminal of the NOT circuit NOT2, the transistor drive circuit SWD operates in the step-down operation mode. When a high level signal is output from the output terminal of the NOT circuit NOT4, the transistor drive circuit SWD operates in the step-up / step-down operation mode. When a high level signal is output from the output terminal of the NOT circuit NOT3, the transistor drive circuit SWD operates in the boosting operation mode (FIG. 7).

  In the first embodiment, the detection resistors RS1 to RS3 that detect the peak current IL of the coil L1 are selected by the operation mode conversion circuit MS. In the step-up operation mode, the operation mode conversion circuit MS selects the first detection resistor RS1. In the step-up / step-down operation mode, the operation mode conversion circuit MS selects the second detection resistor RS2 having a resistance value larger than that of the first detection resistor RS1. In the step-down operation mode, the operation mode conversion circuit MS selects the third detection resistor RS3 having a resistance value larger than that of the detection resistor RS2.

  In the second embodiment, the operation mode conversion circuit MS selects the PMOS transistors M10 to M12 that pass a current corresponding to the peak current IL of the coil L1. In the step-up operation mode, the operation mode conversion circuit MS selects the PMOS transistor M10 that passes the first current corresponding to the peak current IL of the coil L1. In the step-up / step-down operation mode, the operation mode conversion circuit MS selects the PMOS transistor M11 that passes a second current that is larger than the first current and that corresponds to the peak current IL of the coil L1. In the step-down operation mode, the operation mode conversion circuit MS selects the PMOS transistor M12 that passes a third current that is larger than the second current and that corresponds to the peak current IL of the coil L1.

  In the third embodiment, the operation mode conversion circuit MS selects the current sources I1 to I3 that flow the correction current IOFFSET to the detection resistor RS that detects the peak current IL of the coil L1. In the step-up operation mode, the operation mode conversion circuit MS selects the first current source I1 through which the first correction current IA1 flows. In the step-up / step-down operation mode, the operation mode conversion circuit MS selects the second current source I2 that flows the second correction current IA2 larger than the first correction current IA1. In the step-down operation mode, the operation mode conversion circuit MS selects the third current source I3 that flows the third correction current IA3 that is larger than the second correction current IA2.

  In the step-up / step-down DC-DC converters according to the first to third embodiments, a state in which energy is accumulated in the coil L1 from the input side (hereinafter, “state A”) and energy from the coil L1 to the output side according to the operation mode. The state to be released (hereinafter referred to as “state B”) is repeated alternately.

  State A includes state A1 in which energy is only stored in coil L1 and energy is not released to the output side, and state A2 in which energy is supplied to coil L1 and energy is released to the output side at the same time. By variably controlling the ratio of each period of the states A1, B, A2, a constant output voltage can be obtained without depending on the fluctuation of the input voltage (FIG. 2).

  The setting of the period ratio of states A1, B, and A2 is different for each operation mode. This is because the difference in voltage value between the input voltage VIN and the output voltage VOUT is related. In the step-down operation mode in which the input voltage VIN is higher than the output voltage VOUT, energy can be stored in the coil L1 even in the state A2, so that the state A1 can be limited to the minimum necessary period. The period of the state A1 in which energy is not supplied to the output side becomes the minimum necessary, and an efficient operation that can discharge energy to the output side while storing energy in the coil L1 can be performed. Thereby, the peak current IL of L1 can be reduced. In contrast, in the step-down operation mode in which the input voltage VIN is lower than the output voltage VOUT, energy cannot be stored in the coil L1 in the state A2, and is a period in which energy is exclusively released to the output side. In principle, the step-up operation mode must have a period of state A1. That is, it is necessary to secure a period for stopping energy release to the output side and storing energy in the coil L1. The efficiency of energy release to the output side cannot be as high as that of the step-down operation mode. For this reason, the peak current IL of the coil L1 increases in the step-up operation mode. In the step-up / step-down operation mode that is an intermediate operation mode between the step-down operation mode and the step-up operation mode, the peak current IL of the coil L1 is also intermediate.

  The peak current IL of the coil L1 required for the same load current is different for each operation mode. Therefore, when the operation mode is switched, the required peak current IL of the coil L1 changes rapidly. When switching from the step-down operation mode to the step-up / step-down operation mode, or when switching from the step-up / step-down operation mode to the step-up operation mode, the peak current IL of the coil L1 required to maintain the same load current increases.

  In the DC-DC converter control circuits 1 to 3, the error amplifier ERA1 responds by detecting the fluctuation of the output voltage VOUT. For this reason, when the operation mode is switched to the operation mode in which the required peak current IL of the coil L1 increases, the control circuit does not respond immediately with the switching of the operation mode. Control for increasing the peak current IL of the coil L1 must wait until a decrease in the output voltage VOUT is detected. In the step-up / step-down DC-DC converter control circuit, the output voltage VOUT decreases transiently due to a response delay associated with switching of the operation mode.

  In order to suppress a transient drop in the output voltage VOUT, in the first embodiment, the detection resistors RS1 to RS3 that detect the peak current IL of the coil L1 are selected for each operation mode.

  When the step-down operation mode is switched to the step-up / step-down mode, the third detection resistor RS3 is switched to the second detection resistor RS2. When the step-up / step-down mode is switched to the step-up mode, the second detection resistor RS2 is switched to the first detection resistor RS1. When switching from the step-down operation mode to the step-up / step-down mode and from the step-up / step-down mode to the step-up mode, the detection resistor is switched to a detection resistor having a smaller resistance value.

  On the other hand, even if the operation mode is switched, the output of the error amplifier ERA1 does not change steeply. Therefore, the voltage between the terminals of the detection resistor (any one of RS1 to RS3) necessary for the comparator CMP1 to output a high level signal does not change. Therefore, immediately after switching from the step-down operation mode to the step-up / step-down mode and immediately after switching from the step-up / step-down mode to the step-up mode, the resistance value of the detection resistor is switched to a smaller resistance value, thereby flowing to the coil L1. The peak current IL can be set to a larger current value.

  After the operation mode is switched, the peak current IL flowing through the coil L1 can be increased regardless of the response delay of the output of the error amplifier ERA1, compared to before the operation mode is switched. As a result, it is possible to suppress a transient decrease in the output voltage VOUT due to a response delay of the error amplifier ERA1 or the like before and after the switching of the operation mode.

  In order to suppress a transient drop in the output voltage VOUT, in the second embodiment, a PMOS transistor (any one of M10 to M12) that supplies a current corresponding to the peak current IL of the coil L1 is selected for each operation mode. .

  When the step-down operation mode is switched to the step-up / step-down mode, the PMOS transistor M12 is switched to the PMOS transistor M11. When the step-up / step-down mode is switched to the step-up mode, the PMOS transistor M11 is switched to the PMOS transistor M10. When switching from the step-down operation mode to the step-up / step-down mode and from the step-up / step-down mode to the step-up mode, the current flowing through the detection resistor RS decreases.

  On the other hand, even if the operation mode is switched, the output of the error amplifier ERA1 does not change steeply. Therefore, the voltage between the terminals of the detection resistor RS necessary for the comparator CMP1 to output a high level signal does not change. Therefore, immediately after switching from the step-down operation mode to the step-up / step-down mode and immediately after switching from the step-up / step-down mode to the step-up / step-down mode, the current flowing through the detection resistor RS decreases, so that the peak current IL flowing through the coil L1 is reduced. A larger current value can be obtained.

  After the operation mode is switched, the peak current IL flowing through the coil L1 can be increased regardless of the response delay of the output of the error amplifier ERA1, compared to before the operation mode is switched. As a result, it is possible to suppress a transient decrease in the output voltage VOUT due to a response delay of the error amplifier ERA1 or the like before and after the switching of the operation mode.

  In order to suppress a transient drop in the output voltage VOUT, in the third embodiment, a current source (any one of I1 to I3) that supplies the correction current IOFFSET to the detection resistor RS that detects the peak current IL of the coil L1. Is selected for each operation mode.

  When the step-down operation mode is switched to the step-up / step-down mode, the third current source I3 is switched to the second current source I2. When the step-up / step-down mode is switched to the step-up mode, the second current source I2 is switched to the first current source I1. When switching from the step-down operation mode to the step-up / step-down mode and from the step-up / step-down mode to the step-up mode, the correction current IOFFSET flowing through the detection resistor RS decreases.

  On the other hand, even if the operation mode is switched, the output of the error amplifier ERA1 does not change steeply. Therefore, the voltage between the terminals of the detection resistor RS necessary for the comparator CMP1 to output a high level signal does not change. Therefore, immediately after switching from the step-down operation mode to the step-up / step-down mode and immediately after switching from the step-up / step-down mode to the step-up / step-down mode, the correction current IOFFSET flowing through the detection resistor RS decreases, and thus the peak flowing through the current coil L1. The current IL can be set to a larger current value.

  After the operation mode is switched, the peak current IL flowing through the coil L1 can be increased regardless of the response delay of the output of the error amplifier ERA1, compared to before the operation mode is switched. As a result, it is possible to suppress a transient decrease in the output voltage VOUT due to a response delay of the error amplifier ERA1 or the like before and after the switching of the operation mode.

  Next, effects of the first to third embodiments will be described. As an effect common to the first to third embodiments, when switching from the step-down operation mode to the step-up / step-down mode, or when switching from the step-up / step-down mode to the step-up mode, the voltage across the terminals of the detection resistor decreases. On the other hand, even if the operation mode is switched, the output of the error amplifier ERA1 does not change steeply. Therefore, the voltage between the terminals of the detection resistor necessary for the comparator CMP1 to output a high level signal does not change.

  Thereby, after the operation mode is switched, the peak current IL flowing through the coil L1 can be increased compared to before the operation mode is switched. The transient decrease in the output voltage VOUT can be suppressed by the peak current IL flowing through the increasing coil L1.

  As a unique effect in the first and second embodiments, when switching from the step-down operation mode to the step-up / step-down mode and from the step-up / step-down mode to the step-up mode, the peak current IL1 flowing in the coil L1 increases as the peak current IL1 increases. The voltage difference between the terminals of the detection resistor increases. Specifically, when the step-down operation mode is switched to the step-up / step-down mode and when the step-up / step-down mode is switched to the step-up / step-down mode, the decrease width of the voltage across the detection resistor increases. Accordingly, the peak current IL flowing through the coil L1 increases. In the step-up / step-down DC-DC converter, the difference in the peak current IL1 between the operation modes increases as the load current increases. Therefore, the difference in the voltage between the terminals of the detection resistor is increased according to the load current by switching the operation mode, so that the difference in the peak current IL1 can be compensated according to the amount of the load current. Regardless of the amount of load current, it is possible to suppress a transient decrease in the output voltage VOUT.

  Thereby, in the step-up / step-down DC-DC converter control circuits 1 to 3, it is possible to suppress a transient decrease in the output voltage VOUT caused by a response delay accompanying the switching of the operation mode.

  In addition, 1st-3rd embodiment can also be combined suitably, respectively.

  For example, the detection resistors RS1 to RS3 selected in the first embodiment and the PMOS transistors M10 to M12 selected in the second embodiment or the current sources I1 to I3 selected in the third embodiment are used in combination. When switching from the step-down operation mode to the step-up / step-down mode and from the step-up / step-down mode to the step-up mode, the noise component appears in the voltage across the detection resistor in the transient state as the detection resistor, current source, and the width of each decrease increase. It becomes easy to mix. By narrowing the reduction width for each detection resistor and current source and using the detection resistor and current source in combination, it is possible to reduce noise components mixed in the voltage applied to both ends of the detection resistor in the transient state.

  Further, the PMOS transistors M10 to M12 selected in the second embodiment and the current sources I1 to I3 selected in the third embodiment may be used in combination. The supply capability of the current that can be passed to the detection resistor RS is increased by the fact that there are two factors that cause the current to flow to the detection resistor RS. Thereby, after the operation mode is switched, the voltage applied to both ends of the detection resistor RS can be rapidly reduced.

  Here, the coil L1 corresponds to an inductance element in claims. The circuit including the resistance element RA, the amplifier AMP1, and the PMOS transistor M5 corresponds to the monitor circuit in the claims. A circuit including the resistance element RA and the amplifier AMP1 corresponds to the detection circuit in the appendix. The comparator CMP1 corresponds to the comparator in the appendix. The PMOS transistor M5 corresponds to the variable current circuit in the remarks. The PMOS transistor M10 corresponds to the first current circuit in the appendix. The PMOS transistor M11 corresponds to the second current circuit in the remarks. The PMOS transistor M12 corresponds to the third current circuit in the remarks.

Hereinafter, various aspects of the invention will be summarized as additional notes.
(Appendix 1)
A step-up / step-down DC-DC converter control circuit for controlling a peak current flowing in an inductance element,
A first detection resistor that converts the peak current or a current corresponding to the peak current into a voltage;
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage, the second detection resistor having a resistance value larger than the first detection resistor;
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage, the resistance value of which is larger than the second detection resistor;
And a first selection circuit that selects the third detection resistor in the step-down operation mode, selects the second detection resistor in the step-up / step-down operation mode, and selects the first detection resistor in the step-up operation mode. A step-up / step-down DC-DC converter control circuit.
(Appendix 2)
An error amplifier;
The comparator according to claim 1, further comprising a comparator that compares a detection value voltage-converted by the first detection resistor, the second detection resistor, or the third detection resistor with an output of the error amplifier. Buck-boost DC-DC converter control circuit.
(Appendix 3)
The step-up / step-down DC-DC converter control according to appendix 1 or 2, wherein the first detection resistor, the second detection resistor, and the third detection resistor are provided on a current path passing through the inductance element. circuit.
(Appendix 4)
4. The step-up / step-down DC-DC converter control circuit according to claim 3, wherein the first detection resistor, the second detection resistor, and the third detection resistor are provided between the inductance element and an input power supply. .
(Appendix 5)
A monitor circuit that generates a current corresponding to the current flowing through the inductance element;
The step-up / step-down DC-DC converter control circuit according to appendix 1 or 2, wherein the first detection resistor, the second detection resistor, and the third detection resistor are connected to the monitor circuit.
(Appendix 6)
The monitor circuit is
A detection circuit for detecting a current flowing through the inductance element;
The step-up / step-down DC-DC converter control circuit according to appendix 5, further comprising: a variable current circuit that supplies a current according to a detection result by the detection circuit.
(Appendix 7)
The variable current circuit is:
A first current circuit for flowing a first current corresponding to the peak current or the peak current;
A second current circuit that is larger than the first current and flows the peak current or a second current corresponding to the peak current;
A third current circuit that is larger than the second current and passes the peak current or a third current corresponding to the peak current;
And a second selection circuit for selecting the third current circuit in the step-down operation mode, selecting the second current circuit in the step-up / step-down operation mode, and selecting the first current circuit in the step-up operation mode. The step-up / step-down DC-DC converter control circuit according to appendix 6.
(Appendix 8)
A step-up / step-down DC-DC converter control circuit for controlling a peak current flowing in an inductance element,
A detection circuit for detecting a current flowing through the inductance element;
A variable current circuit for generating a current according to a detection result by the detection circuit;
A detection resistor that converts a voltage generated by the variable current circuit into a voltage;
The variable current circuit is:
A first current circuit for flowing a first current corresponding to the peak current or the peak current;
A second current circuit that is larger than the first current and flows the peak current or a second current corresponding to the peak current;
A third current circuit that is larger than the second current and passes the peak current or a third current corresponding to the peak current;
And a second selection circuit for selecting the third current circuit in the step-down operation mode, selecting the second current circuit in the step-up / step-down operation mode, and selecting the first current circuit in the step-up operation mode. A step-up / step-down DC-DC converter control circuit.
(Appendix 9)
A first current source for flowing a first correction current;
A second current source for flowing a second correction current larger than the first correction current;
A third current source for flowing a third correction current larger than the second correction current;
And a third selection circuit for selecting the third current source in the step-down operation mode, selecting the second current source in the step-up / step-down operation mode, and selecting the first current source in the step-up operation mode. The step-up / step-down DC-DC converter control circuit according to any one of Supplementary Notes 1, 2, 5 to 8.
(Appendix 10)
A step-up / step-down DC-DC converter control circuit for controlling a peak current flowing in an inductance element,
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage;
A first current source for flowing a first correction current through the detection resistor;
A second current source for flowing a second correction current larger than the first correction current through the detection resistor;
A third current source for flowing a third correction current larger than the second correction current through the detection resistor;
And a third selection circuit for selecting the third current source in the step-down operation mode, selecting the second current source in the step-up / step-down operation mode, and selecting the first current source in the step-up operation mode. A step-up / step-down DC-DC converter control circuit.
(Appendix 11)
11. The step-up / step-down DC-DC converter control circuit according to claim 10, further comprising: an error amplifier; and a comparator that compares a detection value that is voltage-converted by the detection resistor with an output of the error amplifier.
(Appendix 12)
A monitor circuit for generating a current corresponding to the current flowing through the inductance element;
12. The step-up / step-down DC-DC converter control circuit according to appendix 10 or 11, wherein the monitor circuit is connected to the detection resistor.
(Appendix 13)
The monitor circuit is
A detection circuit for detecting a current flowing through the inductance element;
The step-up / step-down DC-DC converter control circuit according to appendix 12, further comprising: a variable current circuit that supplies a current according to a detection result by the detection circuit.
(Appendix 14)
The variable current circuit is:
A first current circuit for flowing a first current corresponding to the peak current or the peak current;
A second current circuit that is larger than the first current and flows the peak current or a second current corresponding to the peak current;
A third current circuit that is larger than the second current and passes the peak current or a third current corresponding to the peak current;
And a second selection circuit that selects the third current circuit in the step-down operation mode, selects the second current circuit in the step-up / step-down / step-up operation mode, and selects the first current circuit in the step-up operation mode. 14. The step-up / step-down DC-DC converter control circuit according to supplementary note 13,
(Appendix 15)
A step-up / step-down DC-DC converter control method for controlling a peak current flowing in an inductance element,
A step of voltage-converting the peak current or a current corresponding to the peak current with a first detection resistor in the step-up operation mode;
Converting the peak current or a current corresponding to the peak current in a step-up / step-down operation mode by a second detection resistor having a resistance value larger than the first detection resistor;
A step-up / step-down DC-DC comprising the step of converting the peak current or a current corresponding to the peak current by a third detection resistor having a resistance value larger than the second detection resistor in the step-down operation mode. Converter control method.
(Appendix 16)
A step-up / step-down DC-DC converter control method for controlling a peak current flowing in an inductance element,
Flowing a first correction current through the detection resistor in the step-up operation mode;
Passing a second correction current larger than the first correction current through the detection resistor in a step-up / step-down operation mode;
And a step of passing a third correction current larger than the second correction current through the detection resistor in the step-down operation mode.

It is a circuit diagram of a prior art. It is a waveform diagram of IL. It is a circuit diagram of a 1st embodiment. It is a circuit diagram of a 2nd embodiment. It is a circuit diagram of a 3rd embodiment. It is a circuit diagram of MS. It is an operation mode diagram corresponding to the action of MS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control circuit of 1st Embodiment 2 Control circuit of 2nd Embodiment 3 Control circuit of 3rd Embodiment 4 Circuit provided with 1st detection resistance, 2nd detection resistance, 3rd detection resistance, and 1st selection circuit 5 Circuit including first current circuit, second current circuit, third current circuit, and second selection circuit 6 Circuit including first current source, second current source, third current source, and third selection circuit AMP1 Amplifier C1 Output capacitor CMP1, CMP2, CMP3 Comparator ERA1 Error amplifier E1, E2 Constant voltage source (FB) Feedback terminal I1 First current source I2 Second current source I3 Third current source L1 Coil (LX0), (LX1), (LX2), (LX3), (LX4), (LX5), (LX6) Terminals M1, M2, M5, M10, M11, M12 PMOS transistor M3, M4 NMOS transistor MS operation Mode conversion circuit NAND1 NAND circuit NOT1, NOT2, NOT3, NOT4 NOT circuit NOR1, NOR2 NOR circuit OSC oscillator (Q1), (Q2), (Q3), (Q4) Output terminal of transistor drive circuit SWD (R) Transistor drive circuit SWD reset terminal R1, R2, R3, R4, R5, R6, RA Resistance element RS1 First detection resistor RS2 Second detection resistor RS3 Third detection resistor RS detection resistor (S) Set terminal SW1 of the transistor drive circuit SWD Selection circuit SW2 Second selection circuit SW3 Third selection circuit SWD Transistor drive circuit (VOUT) Output terminal

IA1 first correction current IA2 second correction current IA3 third correction current IOFFSET correction current IL peak current of coil L1 VIN input voltage VOUT output voltage VREF set voltage

Claims (8)

A step-up / step-down DC-DC converter control circuit for controlling a peak current flowing in an inductance element,
A first detection resistor that converts the peak current or a current corresponding to the peak current into a voltage;
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage, the second detection resistor having a resistance value larger than the first detection resistor;
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage, the resistance value of which is larger than the second detection resistor;
And a first selection circuit that selects the third detection resistor in the step-down operation mode, selects the second detection resistor in the step-up / step-down operation mode, and selects the first detection resistor in the step-up operation mode. A step-up / step-down DC-DC converter control circuit. A monitor circuit that generates a current corresponding to the current flowing through the inductance element;
2. The step-up / step-down DC-DC converter control circuit according to claim 1, wherein the first detection resistor, the second detection resistor, and the third detection resistor are connected to the monitor circuit. The monitor circuit is
A detection circuit for detecting a current flowing through the inductance element;
The step-up / step-down DC-DC converter control circuit according to claim 2, further comprising: a variable current circuit that supplies a current according to a detection result by the detection circuit. A first current source for flowing a first correction current;
A second current source for flowing a second correction current larger than the first correction current;
A third current source for flowing a third correction current larger than the second correction current;
And a third selection circuit for selecting the third current source in the step-down operation mode, selecting the second current source in the step-up / step-down operation mode, and selecting the first current source in the step-up operation mode. The step-up / step-down DC-DC converter control circuit according to any one of claims 1 to 3. A step-up / step-down DC-DC converter control circuit for controlling a peak current flowing in an inductance element,
A detection resistor that converts the peak current or a current corresponding to the peak current into a voltage;
A first current source for flowing a first correction current through the detection resistor;
A second current source for flowing a second correction current larger than the first correction current through the detection resistor;
A third current source for flowing a third correction current larger than the second correction current through the detection resistor;
And a third selection circuit for selecting the third current source in the step-down operation mode, selecting the second current source in the step-up / step-down operation mode, and selecting the first current source in the step-up operation mode. A step-up / step-down DC-DC converter control circuit. A monitor circuit for generating a current corresponding to the current flowing through the inductance element;
The step-up / step-down DC-DC converter control circuit according to claim 5, wherein the monitor circuit is connected to the detection circuit. A step-up / step-down DC-DC converter control method for controlling a peak current flowing in an inductance element,
A step of voltage-converting the peak current or a current corresponding to the peak current with a first detection resistor in the step-up operation mode;
Converting the peak current or a current corresponding to the peak current in a step-up / step-down operation mode by a second detection resistor having a resistance value larger than the first detection resistor;
A step-up / step-down DC-DC comprising the step of converting the peak current or a current corresponding to the peak current by a third detection resistor having a resistance value larger than the second detection resistor in the step-down operation mode. Converter control method. A step-up / step-down DC-DC converter control method for controlling a peak current flowing in an inductance element,
Flowing a first correction current through the detection resistor in the step-up operation mode;
Passing a second correction current larger than the first correction current through the detection resistor in a step-up / step-down operation mode;
And a step of passing a third correction current larger than the second correction current through the detection resistor in the step-down operation mode.

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